WO2006106570A1 - Dispositif a semi-conducteurs - Google Patents

Dispositif a semi-conducteurs Download PDF

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Publication number
WO2006106570A1
WO2006106570A1 PCT/JP2005/006265 JP2005006265W WO2006106570A1 WO 2006106570 A1 WO2006106570 A1 WO 2006106570A1 JP 2005006265 W JP2005006265 W JP 2005006265W WO 2006106570 A1 WO2006106570 A1 WO 2006106570A1
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WO
WIPO (PCT)
Prior art keywords
word line
source
line
transistor
bit line
Prior art date
Application number
PCT/JP2005/006265
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English (en)
Japanese (ja)
Inventor
Hiroyuki Nansei
Original Assignee
Spansion Llc
Spansion Japan Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Spansion Llc, Spansion Japan Limited filed Critical Spansion Llc
Priority to PCT/JP2005/006265 priority Critical patent/WO2006106570A1/fr
Priority to JP2007512374A priority patent/JP5099691B2/ja
Publication of WO2006106570A1 publication Critical patent/WO2006106570A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Definitions

  • the present invention relates to a nonvolatile memory, and more particularly to a nonvolatile memory using a transistor having a plurality of charge storage regions.
  • nonvolatile memories which are semiconductor devices capable of rewriting data
  • technical development for the purpose of miniaturization of the memory cell is being advanced because of the high storage capacity.
  • a floating gate type flash memory that accumulates electric charges in a floating gate has been widely used.
  • memory cells become more miniaturized to achieve higher storage densities, it becomes difficult to design floating gate flash memories.
  • a thin film of a tunnel oxide film is required.
  • the leakage current flowing through the tunnel oxide film increases due to the thin film of the tunnel oxide film, and the charge accumulated in the floating gate is lost due to the introduction of defects in the tunnel oxide film. This will cause a failure in reliability.
  • Flash memory with an ONO (Oxide / Nitride / Oxide) film, such as the Oxide Nitride Oxide Silicon) type.
  • ONO Oxide / Nitride / Oxide
  • This is a flash memory in which electric charges are accumulated in a silicon nitride film layer called a trap layer sandwiched between oxide silicon film layers.
  • charges are accumulated in the silicon nitride film layer, which is an insulating film. Therefore, even if there is a defect in the tunnel oxide film, loss of charges is unlikely to occur as in the floating gate type.
  • Patent Document 1 discloses a (planar accumulation type) transistor having two charge accumulation regions between a gate electrode and a semiconductor substrate.
  • Patent Document 2 discloses a (side wall storage type) transistor having a charge storage region on both side walls of a gate electrode.
  • the source and the drain are interchanged to operate symmetrically.
  • the memory array structure of the flash memory employs a virtual ground method that does not distinguish between a source and a drain.
  • the bit line serves as both a source region and a drain region which are a source region and a drain region, and the bit line extends in the width direction of the word line. For this reason, the current between the source and drain regions of the transistor flows in the extending direction of the word line.
  • Patent Document 1 US Patent No. 6011725
  • Patent Document 2 JP 2004-56095 A
  • the bit line is formed of an ion implantation diffusion region such as arsenic. Therefore, the ion-implanted impurities are diffused in the width direction in the subsequent thermal process, and the bit line width is increased. In addition, the bit line needs to have a low resistance in order to improve the write / erase characteristics. Since the ion implantation is performed at a high energy and high dose, the bit line width is further increased. This hinders miniaturization of the memory cell.
  • An object of the present invention is to provide a semiconductor device capable of miniaturizing a memory cell, excluding the above-described adverse effects caused by the fact that source / drain region force also serves as a line.
  • the present invention provides a transistor comprising a gate electrode formed on a semiconductor substrate, two source / drain regions formed in the semiconductor substrate on both sides of the gate electrode, and a plurality of charge storage regions. And a bit line connected to the source / drain region and a word line connected to the gate electrode, and a direction of a current flowing between the two source / drain regions is
  • the semiconductor device is in the width direction.
  • the bit line can be formed without serving as the source and drain regions. For this reason, it is possible to prevent the bit line from diffusing in the lateral direction by the heat treatment process when forming the word line after forming the bit line or forming the wiring layer. As a result, the memory cell can be miniaturized.
  • the present invention can be a semiconductor device in which the charge storage region is formed between the semiconductor substrate and the gate electrode or on the side wall of the gate electrode. According to the present invention, it is possible to miniaturize a memory cell even in a semiconductor device having a planar storage type or sidewall storage type transistor. Furthermore, in a semiconductor device having a sidewall storage transistor, the direction of the current flowing between the source and drain regions is set to the width direction of the word line, so that the word line and the gate electrode are formed in different layers. There is no need. As a result, the manufacturing process can be simplified.
  • the present invention can be a semiconductor device in which the charge storage region is formed between the semiconductor substrate and the gate electrode or on the side wall of the gate electrode.
  • the present invention may be a semiconductor device in which the word line is formed also as the gate electrode. According to the present invention, the manufacturing process can be simplified.
  • the word line extends in a straight line
  • the bit line extends in the width direction of the word line, and has a zigzag shape having apexes between adjacent word lines
  • Transistors adjacent in the extending direction of the bit line share one of the source and drain regions
  • the bit line is connected to the source and drain region at the apex
  • the bit line connected to one of the source and drain regions of the first transistor is on the opposite side of the word line.
  • the semiconductor device can be connected to one of the source and drain regions of the second transistor adjacent in the direction.
  • the memory cell can be miniaturized by making the bit line zigzag.
  • the present invention may be a semiconductor device in which the first transistor and the second transistor are each connected to a bit line adjacent in the extending direction of the word line.
  • the present invention can be a semiconductor device in which elements adjacent to each other in the word line extending direction are separated using an oxide silicon film. According to the present invention, it is possible to miniaturize a memory cell in which a junction current does not flow between the contact hole and the semiconductor substrate even if the contact hole connecting the bit line and the source / drain region is formed shifted. I'll do it.
  • the word line extends in a zigzag shape
  • the bit line extends in the width direction of the word line, and is a straight line passing through the zigzag apex portion of the word line
  • the transistor may be disposed between adjacent apexes of the word line, and the transistor adjacent in the extending direction of the first line may be a semiconductor device having one source / drain region.
  • the memory cells can be miniaturized by making the word lines zigzag.
  • a semiconductor device in which two adjacent bit lines are respectively connected to two source and drain regions formed on both sides of the word line of one transistor. it can.
  • the present invention may be a semiconductor device in which elements adjacent to each other in the extending direction of the bit line are separated using an oxide silicon film. According to the present invention, it is possible to miniaturize a memory cell in which a junction current does not flow between the contact hole and the semiconductor substrate even if the contact hole connecting the bit line and the source / drain region is formed shifted. I'll do it.
  • the bit line can be formed without serving as the source / drain regions. For this reason, it is possible to prevent the bit lines from being diffused in the lateral direction by the heat treatment process at the time of forming the word lines and forming the wiring layers after forming the bit lines. As a result, the memory cell can be miniaturized.
  • FIG. 1 is a cross-sectional view of a transistor used in a memory cell according to Example 1.
  • FIG. 2 is a top view of the memory cell according to the first embodiment.
  • FIG. 3 is a cross-sectional view of the memory cell according to Example 1, and shows a cross section taken along the line AA in FIG.
  • FIG. 4 is a cross-sectional view of the memory cell according to Example 1, showing a cross section taken along line BB in FIG.
  • FIG. 5 is a cross-sectional view of the memory cell according to Example 1, showing a CC cross section of FIG.
  • FIG. 6 is a cross-sectional view of the memory cell according to Example 1, and is a view showing a DD cross section of FIG.
  • FIG. 7 is a diagram for calculating the memory cell area of the memory cell according to the first embodiment.
  • FIG. 8 is a cross-sectional view of a memory cell according to a modification of Example 1, and is a cross-sectional view corresponding to the AA cross section of FIG.
  • FIG. 9 is a top view of a memory cell according to the second embodiment.
  • FIG. 10 is a cross-sectional view of the memory cell according to the second embodiment, showing a cross section taken along the line AA in FIG.
  • FIG. 11 is a cross-sectional view of the memory cell according to Example 2, showing a cross section taken along line BB in FIG. 2.
  • FIG. 12 is a cross-sectional view of the memory cell according to Example 2, showing the CC cross section of FIG. 2.
  • FIG. 13 is a cross-sectional view of the memory cell according to the second embodiment, and shows a DD cross section of FIG. 2.
  • FIG. 14 is a diagram (No. 1) for calculating the memory cell area of the memory cell according to the second embodiment.
  • FIG. 15 is a diagram (part 2) for calculating the memory cell area of the memory cell according to the second embodiment.
  • FIG. 16 is a cross-sectional view of a transistor used in the memory cell according to Example 3.
  • FIG. 1 shows a cross-sectional structure of a planar storage transistor used in the first embodiment.
  • a LOCOS Local Oxidation of Silicon
  • a field oxide film 30 (acid silicon film: not shown) is applied.
  • An oxide silicon film (tunnel oxide film) 22, a silicon nitride film (trap layer) 24, and an acid silicon film (top oxide film) 26 are formed as an ONO film 28 on the semiconductor substrate 20 by, for example, the CVD method.
  • LOCOS Local Oxidation of Silicon
  • a word line 12 including a gate electrode is formed on the ONO film 28 by, for example, forming a polycrystalline silicon film and etching a predetermined region. For example, arsenic is implanted into a predetermined region, and source / drain regions 14 are formed on both sides of the gate electrode.
  • the ONO film 28 other than the word line 12 is etched. Etching of the ONO film is not indispensable, but for example, when the so-called salicide process, in which the upper part of the word line 12 is silicided and the source and drain regions 14 can also be silicided, is adopted as the word line 12. This is effective because both the source and drain regions 14 can be low resistance.
  • the interlayer insulating film 32 is formed of, for example, an oxide silicon film.
  • Contact holes 16 are formed at predetermined positions of the interlayer insulating film 30.
  • the contact hole 16 is filled with TiZWN or TiZTiN and W, for example, and an A1 wiring layer is formed as the bit line 10.
  • Bit line 10 is connected to source / drain region 14 through contact hole 16.
  • a protective film 34 is formed.
  • planar storage layer type transistor two charge storage regions are formed in the ONO film 28 between the gate electrode (word line) 12 and the semiconductor substrate 20 as in Patent Document 1.
  • FIG. 2 is a top view of the memory cell according to the first embodiment.
  • the protective film 34 and the interlayer insulating film 32 are not shown.
  • the contact hole 16 under the bit line 10a is indicated by a broken line.
  • a plurality of word lines 12a extending in a straight line, and extending in the width direction of the word lines 12a,
  • a plurality of zigzag bit lines 10a having apexes between the lines 12a are formed.
  • a plurality of transistors 11a are formed in the extending direction of the word line 12a and the extending direction of the bit line 10a.
  • two source / drain regions 14a are formed on both sides of the word line 10a which also serves as a gate electrode. At this time, the direction of current flowing between the two source drain regions 14a is the width direction of the word line 12a.
  • the source'drain region 14a is shared with one source'drain region 14a of a transistor adjacent in the extending direction of the bit line 10a.
  • a transistor having the word line (WLn) as the gate electrode is a transistor having the word line (WLn-1) as the gate electrode and a source / drain electrode in a region between the word line (WLn) and the word line (WLn-1). Share 14a.
  • the bit line 10a is connected to the source / drain region 14a at the zigzag approximate vertex, and the bit line connected to the source / drain region 14a on one side of the word line 12a is separated from the word line 12a. On the other hand, it is connected to the source / drain region 14a of the adjacent transistor in the extending direction of the word line 12a.
  • the bit line (BLn) connected to the source 'drain region 14a on the WLn + 1 side of the word line (WLn) is the source' drain 'of the transistor adjacent to the extending direction of the single line 12a on the WLn-1 side. Connected to area.
  • the zigzag bit line 10a is arranged.
  • the word line 12a extends linearly
  • the bit line 10a extends in the width direction of the word line 12a, has a zigzag shape having apexes between adjacent word lines 12a, and bit Transistors adjacent in the extending direction of the line 10a share one source / drain region 14a
  • the bit line 10a is connected to the source / drain region 14a at the apex
  • the first transistor For example, on one side (for example, WLn-1 side) of the first drain (for example, WLn-1) connected to the gate electrode of 11a), 1 of the source / drain region of the first transistor (for example, 11a)
  • the bit line connected to the second line (for example, BLn-2) is connected to the second line adjacent to the word line (for example, WLn-2) on the opposite side (for example, WLn-3 side) in the extending direction of the word line 12a.
  • the transistor Of the scan 'drain region 1 Connected to one.
  • Two adjacent bit lines 10a are connected to source / drain regions 14a of two transistors adjacent to each other in the extending direction of the word line 12a. That is, the first transistor (for example, 11a) and the second transistor are connected to the bit lines (for example, BLn-3 and BLn-2) adjacent to each other in the extending direction of the word line 12a.
  • FIG. 3 is a cross-sectional view taken along the line AA in FIG. 2, and is a cross-sectional view in the word line 12a in the extending direction of the word line 12a.
  • the ONO film 28 and the first drain line 12a are formed on the semiconductor substrate 20 and the field oxide film 30a, and the bit line 10a crosses the first drain line 12a on the field oxide film 30a. No bit line is embedded in the semiconductor substrate 20 below the word line 10a.
  • FIG. 4 is a cross-sectional view taken along the line BB in FIG. 2, and is a cross-sectional view between the word lines 12a in the extending direction of the word lines 12a.
  • the bit line 10a is located on the source / drain region 14a between the field oxide films 30a because of the zigzag shape.
  • Source / drain regions 14a that is, transistors
  • Source / drain regions 14a adjacent in the extending direction of the word line 12a are separated by a field oxide film 30a (acid silicon film).
  • FIG. 5 is a cross-sectional view taken along the line CC in FIG. 2, and is a cross-sectional view inside the transistor in the extending direction of the bit line 10a.
  • Source / drain regions 14a are formed on both sides of the word line (gate electrode) 12a.
  • the bit line 10a is located on the source / drain region 14a and connected through the contact hole 16. Since the bit line 10a is zigzag, the bit line (BLn-1) and the bit line (BLn) appear alternately.
  • FIG. 6 is a cross-sectional view taken along the line DD of FIG. 2, and is a cross-sectional view between transistors in the extending direction of the bit line 10a. Since the transistor adjacent to the extending direction of the word line 12a is isolated, a field oxide film 30a is formed. Bit line 10a is located on word line 12a and the same bit line (BLn) appears. The ONO film 28 other than the word line 12a has been removed.
  • FIG. 7 is a diagram for calculating the memory cell area of the first embodiment.
  • Bit line 10a The minimum size of-line 12a and source 'drain regions 14a and F, when a 2F pitch, one side is 2 2F next memory cell area, the memory cell area can be 8F 2.
  • the direction in which current flows between the source and drain regions 14a is the width direction of the word line 12a.
  • the source / drain region connection that is, the bit line
  • the source and drain regions are exposed outside the first drain line in the first embodiment, it can be connected by wiring through the contact hole.
  • the bit line does not spread laterally due to the heat treatment process at the time of forming the side line 12a after forming the bit line and forming the wiring layer, which is necessary in the buried bit line method.
  • the memory cell can be miniaturized.
  • the ion implantation for forming the source / drain region 14a can be performed with low energy and low dose, and the short channel effect of the transistor can be prevented.
  • the bit line 10a is formed in a zigzag shape and is connected to the source / drain region at the approximate vertex. As a result, the memory cell can be further miniaturized.
  • the source / drain regions 14a are separated from each other by a field oxide film 30a (an acid silicon film).
  • a field oxide film 30a an acid silicon film
  • element isolation can be performed using an STI (Shallow Trench Isolation) method.
  • the configuration and the manufacturing method can be the same as those in Example 1 except that the element is isolated using the buried oxide film 30b (acid silicon film) using the STI method.
  • FIG. 8 is a cross-sectional view corresponding to the AA cross section of FIG. This is the same as in Fig. 3 except that the element is isolated using a buried oxide film 30b using the STI method.
  • Example 2 Example 2 is an example in which a planar storage transistor is used and elements are separated using the STI method.
  • FIG. 9 is a top view of the memory cell according to the second embodiment.
  • the protective film 34 and the interlayer insulating film 32 are not shown.
  • the contact hole 16 below the bit line 10b is indicated by a broken line.
  • a plurality of linear bit lines passing through the portion are formed.
  • the bending direction of the word line 12b is the same for a plurality of word lines.
  • a plurality of transistors l ib are arranged in the extending direction of the word line 12b and the extending direction of the bit line 10b.
  • each transistor l ib two source / drain regions 14b are formed on both sides of the word line 12b which also serves as a gate electrode.
  • the direction of the current flowing between the two source / drain regions 14b is the width direction of the word line 12b.
  • each transistor l ib is arranged approximately in the middle between adjacent apexes of the word line 12b, and shares the source / drain region 14b with the transistor adjacent in the extending direction of the word line 12b! / RU
  • the bit line 10b is connected to the source / drain region 14b! /.
  • the word line 12b extends in a zigzag shape
  • the bit line 10b extends in the width direction of the word line 12b, and is a straight line passing through the zigzag apex portion of the word line 12b.
  • l ib is disposed between adjacent apexes of the word line 12b, and transistors adjacent to each other in the extending direction of the first line 12b share one source / drain region.
  • two adjacent bit lines (for example, BLn-2 and BLn-3) are connected to two source drains formed on both sides of a word line (for example, WLn) of one transistor (for example, ib). Each is connected to a region.
  • FIG. 10 is a cross-sectional view taken along the line AA in FIG.
  • a word line 12b that also serves as a gate gate electrode is formed on the ONO film 28 on the semiconductor substrate 20 .
  • Source and drain regions 14b are formed on both sides of the word line 12b.
  • Interlayer insulating film 32 having contact hole 16 is formed on semiconductor substrate 20 and word line 12b.
  • a bit line 10b connected to the source / drain region 14b through the contact hole 16 is formed on the interlayer insulating film 32.
  • a protective film 34 is formed on the interlayer insulating film 32 and the bit line 10b. Adjacent acid between adjacent transistors The element is isolated by the oxide film 30b (silicon oxide film).
  • FIG. 11 is a cross-sectional view taken along the line BB of FIG. 9, and is a cross-sectional view in the extending direction of the word line 12b across the apex of the word line 12b.
  • the word line 12b is formed on the buried oxide film 30b, and the source / drain region 14b between the word lines 12b is connected to the bit line 10b through the contact hole 16. Every other bit line 10b is connected to a source / drain region 14b. When connected to the source / drain region 14b, the bit line 10b is connected to the source / drain region 14b at the apex of the other word line 12b. Since the word line 12b is zigzag shaped, the same word line (WLn) appears.
  • FIG. 12 is a cross-sectional view taken along the line CC of FIG. 9, and is a cross-sectional view in the bit line 10b extending in the bit line 10b extending direction.
  • the word line 12b is formed on the buried oxide film 30b, and the source / drain region 14b between the word lines 12b is connected to the bit line 10b through the contact hole 16.
  • the bit line 10b crosses over the word line 12b, and the bit line is embedded in the semiconductor substrate 20 below the bit line 10b.
  • FIG. 13 is a cross-sectional view taken along the line DD of FIG. 9, and is a cross-sectional view between the bit lines 10b extending in the bit line 10b extending direction.
  • the semiconductor substrate 20 between the word lines 12b is separated by a buried oxide film 30b.
  • the transistors adjacent to the extending direction of the bit line 10b are separated by the buried oxide film 30b.
  • FIG. 14 is a diagram for calculating the memory cell area of the second embodiment.
  • the minimum dimension of the bit line 10b, the single drain line 12b, and the source / drain region 14b is F, and one side of the zigzag is 3F.
  • the length of the side of the bit line extending direction of the memory cell is 52 / 2F
  • the length of the side of the extending direction of the memory line is 32Z2F
  • the memory cell area can be 7.5 F 2. .
  • the minimum dimension of the bit line 10b, the word line 12b, and the source / drain region 14b is F, and one side of the zigzag is 22 F.
  • the length of the side of the bit line extending direction of the memory cell is (2 + 2) F
  • the length of the side of the extending direction of the word line is 2 2F
  • the area of the memory cell is (4 + 2 2) F 2 (approximately 6.83F 2 ).
  • the memory cell area can be made smaller than in the first embodiment.
  • Example 2 as in Example 1, the flow direction between the source and drain regions is changed.
  • the width direction of the first drain line 12b is used.
  • the bit line 10b can be formed without (including) the source / drain region 14b.
  • miniaturization of the memory cell and the short channel effect can be prevented as in the first embodiment.
  • the bit line 10b passes through the approximate apex of the zigzag word line 12b and is connected to the source / drain region 14b. Thereby, the memory cell can be further miniaturized.
  • the transistors are separated from each other by a buried oxide film 30b.
  • the contact hole 16 is formed on the buried oxide film 30b. No junction current will flow through. Therefore, the alignment margin of the contact hole 16 can be reduced, and the memory cell can be miniaturized. Note that the same effect can be obtained even if the device is isolated using the LOCOS method as in the first embodiment.
  • Example 3 is an example using a sidewall storage type transistor.
  • Figure 16 shows the cross-sectional structure of the sidewall storage transistor.
  • the element isolation region 30 (not shown) is formed by using the STI method or the LOCOS method in the same manner as the planar storage type transistor.
  • a silicon oxide film 21 is formed on the semiconductor substrate 20 by, for example, a thermal oxidation method.
  • a word line 12 that also serves as a gate electrode is formed by, for example, forming a polycrystalline silicon film and etching a predetermined region.
  • An oxide silicon film 23 and a silicon nitride film (charge storage region) 29 are formed as side walls on the side portion of the gate electrode (word line) 12 by the sidewall method, for example, using the CVD method.
  • An oxide silicon film 25 is formed on the entire surface.
  • arsenic is implanted into a predetermined region, and source / drain regions 14 are formed on both sides of the gate electrode 12 (word line).
  • the interlayer insulating film 32 is formed of an oxide silicon film.
  • Contact holes 16 are formed at predetermined locations in the interlayer insulating film 30.
  • the contact hole 16 is filled with, for example, TiZWN or TiZTiN and W, and a wiring layer of, for example, A1 is formed as the bit line 10.
  • the bit line 10 is connected to the source / drain region 14 through the contact hole 16.
  • a protective film 34 is formed.
  • the silicon nitride film 29 formed on both sides of the word line 12 also serving as the gate electrode can be used as a charge storage region.
  • the memory cell formed as described above is, for example, a memory cell arranged as in the first embodiment or the second embodiment. It can be.
  • a memory cell arranged as in the first embodiment or the second embodiment. It can be.
  • a word line is further formed on a gate electrode. This is because the charge storage region is formed on the side wall of the gate electrode, so that it is difficult to extend the word line so as to include the gate electrode in the direction of current flow between the source and drain regions. .
  • the direction of the current flowing between the source and drain regions 14 can be the width direction of the word line. This eliminates the need to form the word line and the gate electrode as separate layers. That is, the word line can be formed so as to also serve as the gate electrode. As described above, the manufacturing process can be simplified. Further, the same effects as those of the first embodiment and the second embodiment can be obtained.
  • the power described in detail for the preferred embodiment of the present invention is not limited to the specific embodiment, and various modifications can be made within the scope of the gist of the present invention described in the claims. Deformation can be changed.
  • a SONOS type memory was used, but a memory using nanocrystals as a trap layer or a high dielectric constant material known as a so-called high-k film was used for the trap layer, tunnel insulating layer, or top layer.
  • the present invention can also be applied to a memory.

Abstract

La présente invention décrit un dispositif à semi-conducteurs doté d'une électrode de grille (12) formée sur un substrat à semi-conducteurs (20), de deux régions de source et de drain (14) formées dans le substrat à semi-conducteurs des deux côtés de l'électrode de grille, d'un transistor possédant deux régions d'accumulation de charge ou plus, d'une ligne de bits (10) reliée aux régions de source et de drain, ainsi que d'une ligne de mots (12) reliée à l'électrode de grille. La direction d'un courant passant entre les deux régions de source et de drain se fait dans la direction de la largeur de la ligne de mots. Puisque la direction du courant passant entre les régions de source et de drain se fait dans la direction de la largeur de la ligne de mots, la ligne de bits peut être formée séparément des régions de source et de drain. Il est ainsi prévu un dispositif à semi-conducteurs dans lequel une cellule de mémoire est micro-miniaturisée.
PCT/JP2005/006265 2005-03-31 2005-03-31 Dispositif a semi-conducteurs WO2006106570A1 (fr)

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PCT/JP2005/006265 WO2006106570A1 (fr) 2005-03-31 2005-03-31 Dispositif a semi-conducteurs
JP2007512374A JP5099691B2 (ja) 2005-03-31 2005-03-31 半導体装置

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* Cited by examiner, † Cited by third party
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