WO2006098513A1 - Procédé de traitement thermique et procédé de cristallisation de semi-conducteur - Google Patents

Procédé de traitement thermique et procédé de cristallisation de semi-conducteur Download PDF

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Publication number
WO2006098513A1
WO2006098513A1 PCT/JP2006/305884 JP2006305884W WO2006098513A1 WO 2006098513 A1 WO2006098513 A1 WO 2006098513A1 JP 2006305884 W JP2006305884 W JP 2006305884W WO 2006098513 A1 WO2006098513 A1 WO 2006098513A1
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layer
carbon
heat
heat treatment
semiconductor
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PCT/JP2006/305884
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English (en)
Japanese (ja)
Inventor
Toshiyuki Sameshima
Nobuyuki Andoh
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National University Corporation Tokyo University Of Agriculture And Technology
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Priority to JP2007508259A priority Critical patent/JPWO2006098513A1/ja
Publication of WO2006098513A1 publication Critical patent/WO2006098513A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H01L21/02686—Pulsed laser beam
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02422—Non-crystalline insulating materials, e.g. glass, polymers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/326—Application of electric currents or fields, e.g. for electroforming
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
    • H01L27/1281—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor by using structural features to control crystal growth, e.g. placement of grain filters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1296—Multistep manufacturing methods adapted to increase the uniformity of device parameters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate

Definitions

  • the present invention relates to a method for heat-treating a material to be processed, and particularly to a method for efficiently heat-treating a semiconductor material or a device in a short time and a method for crystallizing a semiconductor by the heat treatment.
  • Bipolar and MOS type transistors using single crystal silicon as elements constituting electronic devices, and polycrystalline silicon thin film transistors are widely used. Since transistor fabrication is formed on crystalline semiconductors, the formation of crystalline semiconductors is extremely important.
  • crystallization techniques are important for thin-film transistors formed on insulators and insulating film layers.
  • a method of heating at a high temperature of 60 to 100 ° C. for 2 to 20 hours using an electric furnace is known (for example, see Patent Document 1). .
  • Patent Document 1 Japanese Patent Laid-Open No. 2 0 0 4 — 2 2 2 4 3
  • Patent Document 2 Japanese Patent Laid-Open No. 2 0 0 4 — 3 1 1 6 1 5 Disclosure of Invention
  • An object of the present invention is to solve such a problem and to instantaneously and efficiently heat a minute portion of a material to be processed.
  • an instantaneous heat treatment that makes it possible to manufacture an electronic device such as a transistor having good characteristics. It is to provide a method and apparatus.
  • the present invention as set forth in claim 1 uses a carbon layer or a layer containing carbon as a thin film heating element, and the thin film heating element is directly or has a thickness of lOnn! It is formed on the material to be processed through a heat transfer layer of ⁇ 100 / zm, and is heated locally by applying pulse energy to the carbon layer or the layer containing carbon. It is characterized by heat-treating the semiconductor material that is the material to be treated from the surface side by heat transfer.
  • the thin-film heating element der Ru carbon layer also regions pulse width l of the municipal district from 10 ⁇ cm 2 in a layer containing a carbon to 10- 2 cm 2 ( and it is characterized in the this heating treatment the region defined in a short time Ri by the and this give T 7 s or more 10- 2 s following energy scratch.
  • the needle-shaped electrode by bringing the needle-shaped electrode into contact with the carbon layer that is the heat generation layer or the carbon-containing layer, only the needle-shaped electrode contact portion is used by using Joule heat generated by the current supplied from the needle-shaped electrode. Allows local heating.
  • the carbon layer or the layer containing a single bond is used as a thin film heating element, directly or with a thickness of ⁇ ! It is formed to overlap with an amorphous semiconductor material through a heat transfer layer of ⁇ 1 ⁇ ⁇ ⁇ , and gives a pulse-like energy to the carbon layer or the carbon-containing layer as the thin film heating element. It is characterized by a heat treatment method in which the amorphous semiconductor material is heated from the surface side by locally heating by heat transfer.
  • the carbon layer or the layer containing carbon is used as a thin film heating element, and impurities are introduced directly or through a heat transfer layer having a thickness of 10 nm to 100 / m.
  • the carbon layer, which is the thin-film heating element, or the carbon-containing layer is locally heated by applying pulsed energy to the amorphous semiconductor material containing the carbon. Impurities of the amorphous semiconductor material containing the impurities are activated by transmission, and the semiconductor layer is made into a conductor.
  • the invention described in claim 7 is characterized in that a semiconductor element including a plurality of layer structures is used as a material to be heated, and the semiconductor element is heated to improve electrical characteristics of the semiconductor element. Is.
  • the carbon layer or a layer containing carbon is formed on an amorphous semiconductor directly or via a heat transfer layer having a thickness of 10 nm to 100 / zm, and the carbon layer Or containing carbon
  • the layer is heated locally by applying pulsed energy locally to the part that functions as a transistor to heat the layer, and the amorphous semiconductor is heat-treated by the generated heat. This is a method for crystallizing a semiconductor characterized by this.
  • the amorphous semiconductor is limited as containing an impurity.
  • a crystalline semiconductor thin film can be formed.
  • an amorphous semiconductor as the material to be processed and performing the heat treatment by the heat treatment method of the present invention, the amorphous semiconductor can be melted and crystallized by heat.
  • FIG. 1 is an explanatory view of a method for heat-treating a material to be treated in the heat treatment method of the present invention.
  • FIG. 2 is an explanatory diagram when the heat treatment of the present invention is performed by a pulse laser.
  • Figure 3 is a graph showing the frequency characteristics of the light reflectance of a carbon film, which is a black body.
  • FIG. 4 is an explanatory diagram showing a heat treatment of the heat treatment of the present invention by excimer laser irradiation.
  • FIG. 5 is an explanatory diagram for performing heat treatment by excimer laser irradiation when the present invention is not used.
  • Figure 6 is a graph showing the results of crystallization accelerated by heating with laser irradiation.
  • FIG. 7 is an explanatory diagram when heating is performed by Joule heat generated by a pulse current.
  • FIG. 8 is an explanatory diagram of a method for performing local heating by Joule heat.
  • FIG. 9 is a diagram for explaining ion implantation in the pretreatment using the present invention. is there.
  • FIG. 10 is a diagram showing that a heat transfer layer and a carbon layer are deposited on the material layer to be processed after ion implantation.
  • FIG. 11 is an explanatory diagram of a method for activating impurities by heat treatment using light irradiation according to the present invention.
  • FIG. 12 is a conceptual diagram of a method for activating impurities by heat treatment using Joule heat according to the present invention.
  • Figure 1 3 is because a view showing a material to be treated was subjected to property modification of the insulating film and the semiconductor body surface is a layer structure by heat treating process of the present invention 0
  • Fig. 14 is a diagram showing that a force layer was formed on the material to be processed shown in Fig. 13.
  • FIG. 15 is a view showing a form in which the carbon layer is removed after the material to be treated shown in FIG. 14 is heat-treated.
  • FIG. 16 is an explanatory view of manufacturing a thin film transistor as a semiconductor element including a layer structure, and then performing heat treatment by light irradiation according to the method of the present invention.
  • FIG. 17 is an explanatory diagram of fabricating a thin film transistor as a semiconductor element including a layer structure and then performing a heating process by Joule heat according to the method of the present invention.
  • Figure 18 is a graph showing the degree of crystallization of silicon after heating by Joule heat. O o Best Mode for Carrying Out the Invention
  • FIG. 1 is a conceptual diagram of the heat treatment method of the present invention.
  • the principle of operation is that, for example, a glass substrate is used as the substrate 0 0 1, and a material layer 0 0 2 to be processed is formed thereon.
  • An example of the material layer to be processed is silicon.
  • a heat transfer layer 0 0 3 is formed thereon.
  • Heat transfer layer material An example is S i O 2.
  • a carbon film or a film containing carbon is formed as a thin film heating element 0 04 on the heat transfer layer of Si 0 2.
  • pulse energy is locally applied to the carbon film or the carbon-containing film as a thin film heating element to generate heat.
  • the material to be treated is heated by the generated heat.
  • the thickness of the heat transfer layer 0 3 should be 10 nm or more, and if it is 10 0 ⁇ or less, the heat quickly propagates through the heat transfer layer 0 3 and heats the material to be processed 0 0 2 can do.
  • the carbon layer as a thin film heating element or the layer containing carbon is heated by combining the heat transfer layer of 100 / zm or less and the material to be heated.
  • the thickness of the carbon layer or carbon-containing layer of the thin film heating element is large, the amount of heat required to heat the carbon layer or the carbon-containing layer itself to a high temperature is required, and the material to be heated is heated. The total amount of heat required to do so increases and heating efficiency deteriorates. Therefore, the thickness of the carbon layer, which is a thin-film heating element, or the layer containing carbon is preferably about 100 / m or less in order to sufficiently exert the heating effect.
  • FIG. 2 is an explanatory diagram when the heat treatment of the present invention is performed by a pulsed laser beam. 10- 7 s or more 10- 2 s pulse width less laser light 0 0 5 irradiating the heat generating layer 0 0 4. By irradiating the heat generation layer 0 0 4 with the laser light 0 0 5, the heat generation layer 0 4 4 absorbs the laser light and is converted into heat energy. The generated heat is transferred to the material to be processed 0 0 2 through the heat transfer layer 0 0 3. If only this preparative-out area of the irradiation light to 10- 1 0 cm 2 or more 10 2 cm 2, Ru can and this heat treatment is performed at an energy of small pulse light.
  • the force consisting of carbon or a layer containing carbon as a thin film heating element As shown in Fig. 3, the single layer has a light reflectance, and the wavelength of the laser beam is 0.
  • laser light with a single wavelength but also a wide range of light with a wavelength of 2 ⁇ m to 20 ⁇ m can be used efficiently as light for energy supply.
  • a xenon lamp can be used.
  • FIG. 4 shows an example in which the heat treatment of the present invention using pulsed laser light is applied to heat crystallization of a silicon film.
  • a 25 nm amorphous silicon film 0 02 as a material to be processed was formed on a glass substrate 0 1, and a 5 nm Si02 film 0 3 was formed thereon as a heat transfer layer.
  • a carbon layer having a thickness of lOO nm was formed thereon with a notch.
  • Fig. 5 shows an example of a sample made of silicon film only.
  • Fig. 6 is a graph showing the laser energy dependence of the crystallization rate of the silicon film when the carbon layer is irradiated with laser and when the silicon film is directly irradiated with laser. From Fig. 6, it can be seen that when the laser is irradiated on the carbon layer, a higher crystallization rate is obtained than when the silicon film is directly irradiated with the laser, and the bonding is performed with a small energy of 200 mJ / cm 2. It can be seen that a crystallization ratio of 0.8 was obtained.
  • the light reflectivity of carbon at a laser wavelength of 308 nm is 15%, which is small compared to the light reflectivity of 55% of the silicon film.
  • the carbon film absorbs laser light efficiently, and the underlying silicon film The silicon film is highly heated when heated to a higher temperature. This can also be understood from the fact that the crystallization rate is high.
  • FIG. 7 is an explanatory diagram when the heat treatment of the present invention is performed by Joule heat generated by a pulse current.
  • a glass substrate is used as the substrate 0 0 1, and a material layer 0 0 2 to be processed is formed thereon.
  • An example of the heat-treated material layer is silicon.
  • a heat transfer layer 0 0 3 is formed thereon.
  • An example of the heat transfer layer material is SiO2.
  • a carbon film or a film containing carbon is formed as the thin film heating element 0.
  • an electrode 0 0 6 and an electrode 0 0 7 are formed.
  • the electrodes 0 6 and 0 7 are preferably made of a material having a sufficiently low resistance value, and metal is suitable.
  • the above treatment can be applied to heat crystallization of a silicon film.
  • FIG. 8 is an example of a heating method applying the method of FIG. 7, and is an example suitable for performing local heating.
  • a glass substrate is used as the substrate 0 0 1, and a Si 0 2 film is formed as a heat transfer layer 0 0 3 on the silicon film that is the material layer 0 0 2 formed on the glass substrate.
  • a carbon film or a film containing carbon is formed on the thin film heat generating layer 0 4.
  • Electrodes 0 0 6 and 0 0 7 are formed to supply current. By making the electrode 06 very small, the current density in the vicinity of the electrode 06 becomes very large. Therefore, a large Joule heat density is generated, and efficient heating is possible with relatively little input energy.
  • a 25 nm thick amorphous amorphous silicon film was formed on a glass substrate 0 0 1 as a silicon film of the material to be processed 0 2.
  • a 5 nm Si02 heat transfer layer 0 3 was formed thereon.
  • a metal probe having a diameter of 100 ⁇ was used as electrodes 0 0 6 and 0 0 7, and was brought into contact with the carbon film 0 0 4.
  • the resistance between the electrodes was 600 ⁇ .
  • a voltage of 120V was applied between electrodes 0 0 6 and 0 0 7 for 2 ms. After voltage application, the silicon film under the probe electrode crystallized in the range of about 100 ⁇ m diameter.
  • Figure 18 shows the result.
  • Figure 18 shows the crystallized part and the Raman scattering spectrum of the initial film.
  • a very strong crystalline silicon TO phonon peak is observed at 516 cm-1, and a low-frequency broad peak in the initial film is observed. It can be seen that it became very small after crystallization. This result indicates that the silicon film was well crystallized by Joule heating using a carbon film.
  • the shape of the electrode 06 is a circle, but the shape is not limited to a circle and can be changed as appropriate.
  • the electrode contact area 10- 1 0 cm 2 or more 10- 2 cm 2 localized heating of the lower region of this and no electrodes to introduce a large amount of power if the following can be achieved.
  • the shape of the electrode 0 7 is shown to be rectangular and has a larger area than the electrode 0 6, but if necessary, the shape of both electrodes can be changed to, for example, the electrode 0 0 very small area cormorants yo of 6, for example, 10 1 is 0 cm possible two or more 10- 2 cm 2 or less and child.
  • FIG. 9 is a conceptual diagram of impurity activation by the heat treatment method of this heating.
  • a semiconductor film 0 1 1 is formed on a glass substrate of a substrate 0 0 1.
  • impurities are implanted by an ion implantation method.
  • the heat transfer layer 0 0 3 is formed on the semiconductor film 0 11 1 into which impurities are implanted, and the heat generation layer 0 0 4 is formed on the heat transfer layer 0 0 3. Then, a carbon layer or a layer containing carbon is formed.
  • pulse light is irradiated to generate 0 0 4 heat, and 0 1 1 is heat-treated for impurity activation treatment.
  • electrodes 0 0 6 and 0 0 7 for supplying current are formed on the heating layer 0 0 4 of FIG. 8 _ b as shown in FIG. Heat treatment is performed by applying a pulse current, and impurity activation processing is performed.
  • FIG. 13 shows a conceptual diagram of the method.
  • an oxide film 0 2 which is a material layer to be processed
  • a semiconductor surface which is a substrate 0 1 1
  • lattice defects 0 1 2 are generated at the interface.
  • a carbon layer thin film heating element is stacked on the oxide film 0 0 2, and the heat treatment method of the present invention is used.
  • heat treatment is performed at a short time, eg, 10 / zs.
  • defects 0 12 in the semiconductor interface and oxide film are reduced, and an interface having good electrical characteristics can be obtained.
  • the carbon layer is removed after the heat treatment.
  • the heat treatment method of the present invention can reduce defects and improve the interface of the semiconductor Z insulator.
  • the heat treatment method of the present invention is also effective for improving characteristics by heat treatment of MOSFETs, bipolar transistors, laser diodes and the like formed on a semiconductor substrate.
  • FIG. 1 6 is!
  • Semiconductors Bruno 3 comprises a layer structure, as a 'child to prepare a thin film preparative La Njisuta is the conceptual diagram applying by Ri heat treatment in the light irradiation by Method towards present invention thereafter .
  • a semiconductor layer 0 0 2 is formed on a substrate 0 0 1, a gate insulating film 0 0 9 is formed thereon, a gate electrode 0 1 3 is formed, and then a source region is formed by ion implantation or the like.
  • Impurities are implanted into 0 1 4 and the drain region 0 1 5. Further, a source electrode 0 1 6 and a drain electrode 0 1 7 are formed. After the passivation layer 0 18 is formed, a carbon layer or a layer containing a strong bond is formed as the heat generating layer 0 4, and the heat treatment method of the present invention is performed. 0
  • electrodes 0 06 and 0 07 are formed as shown in FIG.
  • a crystalline semiconductor thin film can be formed.
  • a crystalline thin film transistor can be fabricated using this crystalline semiconductor thin film as a channel layer.
  • An electronic device equipped with a plurality of thin-film transistors can be formed by using part or all of this crystalline thin-film transistor fabrication method.
  • An n-type or p-type semiconductor layer can be formed by heating a semiconductor layer containing an impurity using the heat treatment method of the present invention and activating the impurity. If an impurity that generates a hole carrier is mixed in a part of an n-type semiconductor, or an impurity that generates an electron carrier is mixed in a part of a p-type semiconductor, the present invention By heating the semiconductor layer containing impurities using this heat treatment method, the semiconductor P n junctions can be formed.
  • the insulating film can be modified by heat-treating the insulating film using the heat treatment method of the present invention.
  • the substrate surface can be protected with a good quality insulating film.
  • a field-effect transistor can be fabricated using a modified insulating film.
  • a semiconductor surface protective insulating film can be fabricated using the modified insulating film.
  • the interface characteristics can be improved by heat-treating the interface of the insulating film Z semiconductor using the heat treatment method of the present invention.

Abstract

L’invention permet de contrôler avec précision la direction de culture cristalline et la formation d’interface de grain cristallin d’un matériau semi-conducteur, de rendre uniforme la densité de défaut dans un transistor et de réduire la fluctuation des caractéristiques comme le seuil, la mobilité et le courant de fuite. On empile une couche de transfert thermique et une couche de carbone comme corps générateur de chaleur sur le matériau semi-conducteur devant subir un traitement thermique, on applique un faisceau laser ou une tension à la couche de carbone pour que la couche de carbone génère de la chaleur, et on chauffe le matériau semi-conducteur à travers la couche de transfert thermique.
PCT/JP2006/305884 2005-03-18 2006-03-17 Procédé de traitement thermique et procédé de cristallisation de semi-conducteur WO2006098513A1 (fr)

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Cited By (5)

* Cited by examiner, † Cited by third party
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JP2010114412A (ja) * 2008-11-04 2010-05-20 Samsung Mobile Display Co Ltd 薄膜トランジスタ、その製造方法及びそれを含む有機電界発光表示装置
JP2010153847A (ja) * 2008-11-28 2010-07-08 Sumitomo Chemical Co Ltd 半導体基板の製造方法、半導体基板、電子デバイスの製造方法、および反応装置
JP2011054788A (ja) * 2009-09-02 2011-03-17 Toyota Motor Corp 半導体素子、半導体モジュール及びそれらの製造方法
JP2014042044A (ja) * 2009-08-13 2014-03-06 Samsung Display Co Ltd 薄膜トランジスタの製造方法及びそれを含む有機電界発光表示装置の製造方法
KR101905445B1 (ko) * 2016-04-27 2018-10-10 한국과학기술원 트랜지스터 손상 치료 방법 및 이를 이용한 디스플레이 장치

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6221209A (ja) * 1985-07-19 1987-01-29 Nec Corp 高周波アニ−ル方法
JPH0677250A (ja) * 1992-08-25 1994-03-18 Tdk Corp 薄膜トランジスタの製造方法
JP2002289520A (ja) * 2001-03-23 2002-10-04 Japan Science & Technology Corp 薄膜発熱体によるパルス通電熱処理方法及び熱処理装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0715881B2 (ja) * 1984-12-20 1995-02-22 ソニー株式会社 半導体薄膜の熱処理方法
JPS63297293A (ja) * 1987-05-29 1988-12-05 Hitachi Ltd 結晶成長法
JP3214931B2 (ja) * 1992-10-22 2001-10-02 鐘淵化学工業株式会社 多結晶シリコン薄膜およびその形成法
JP3932445B2 (ja) * 2000-05-31 2007-06-20 ソニー株式会社 半導体装置の製造方法
JP4627961B2 (ja) * 2002-09-20 2011-02-09 株式会社半導体エネルギー研究所 半導体装置の作製方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6221209A (ja) * 1985-07-19 1987-01-29 Nec Corp 高周波アニ−ル方法
JPH0677250A (ja) * 1992-08-25 1994-03-18 Tdk Corp 薄膜トランジスタの製造方法
JP2002289520A (ja) * 2001-03-23 2002-10-04 Japan Science & Technology Corp 薄膜発熱体によるパルス通電熱処理方法及び熱処理装置

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010114412A (ja) * 2008-11-04 2010-05-20 Samsung Mobile Display Co Ltd 薄膜トランジスタ、その製造方法及びそれを含む有機電界発光表示装置
JP2010153847A (ja) * 2008-11-28 2010-07-08 Sumitomo Chemical Co Ltd 半導体基板の製造方法、半導体基板、電子デバイスの製造方法、および反応装置
US8709904B2 (en) 2008-11-28 2014-04-29 Sumitomo Chemical Company, Limited Method for producing semiconductor substrate, semiconductor substrate, method for manufacturing electronic device, and reaction apparatus
JP2014042044A (ja) * 2009-08-13 2014-03-06 Samsung Display Co Ltd 薄膜トランジスタの製造方法及びそれを含む有機電界発光表示装置の製造方法
US8871616B2 (en) 2009-08-13 2014-10-28 Samsung Display Co., Ltd. Methods of fabricating thin film transistor and organic light emitting diode display device having the same
JP2011054788A (ja) * 2009-09-02 2011-03-17 Toyota Motor Corp 半導体素子、半導体モジュール及びそれらの製造方法
KR101905445B1 (ko) * 2016-04-27 2018-10-10 한국과학기술원 트랜지스터 손상 치료 방법 및 이를 이용한 디스플레이 장치

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