Classifications

• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K3/00—Apparatus or processes for manufacturing printed circuits
  • H05K3/22—Secondary treatment of printed circuits
  • H05K3/24—Reinforcing of the conductive pattern
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/02—Details
  • H05K1/03—Use of materials for the substrate
  • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/02—Details
  • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K3/00—Apparatus or processes for manufacturing printed circuits
  • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
  • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
  • H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
  • H05K3/3465—Application of solder
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/851—Dispositions of multiple connectors or interconnections
  • H10W72/874—On different surfaces
  • H10W72/879—Bump connectors and bond wires
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
  • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
  • Y10T29/00—Metal working
  • Y10T29/49—Method of mechanical manufacture
  • Y10T29/49002—Electrical device making
  • Y10T29/49117—Conductor or circuit manufacturing
  • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
  • Y10T29/49155—Manufacturing circuit on or in base
  • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base

Definitions

• the present invention relates to a ceramic wiring board used as a semiconductor element mounting board and the like, a manufacturing method thereof, and a semiconductor device using the same.
• An insulating ceramic substrate such as an aluminum nitride substrate or a nitride nitride substrate is used as a mounting substrate for various semiconductor elements such as an optical semiconductor element such as a laser diode or a photodiode.
• an optical semiconductor element such as a laser diode or a photodiode.
• a wiring layer is formed on the surface by applying a thin film forming technique such as a vacuum deposition method, a PVD method such as a sputtering method, or a CVD method. (For example, see Patent Document 1).
• FIG. 4 is a cross-sectional view showing the structure of a conventional ceramic wiring board.
• reference numeral 1 denotes an insulating ceramic substrate having, for example, aluminum nitride sintered body strength, and the surface thereof is made of Au through a base metal layer 2 which is T and a first diffusion prevention layer 3 which is made of Pt.
• a body layer 4 is formed.
• a solder layer 6 having an Au—Sn alloy force is formed on a connection portion (electrode connection portion) of the main conductor layer 4 with the semiconductor element via a second diffusion prevention layer 5 having a Pt isotropic force. .
• the surface of the solder layer 6 is covered with an Au layer 7 to prevent oxidation.
• the base metal layer 2, the first diffusion prevention layer 3, and the Au layer (main conductor layer) 4 are also laminated in this order on the lower surface side of the insulating ceramic substrate 1.
• a formed conductor layer is provided.
• the lower conductive layer is used as a bonding metal layer when the insulating ceramic substrate 1 is mounted on an external circuit board or in a package.
• the conductor layer on the bottom side may be used as a ground conductor layer.
• the second diffusion preventing layer 5 interposed between the main conductor layer 4 and the solder layer 6 described above is used when the semiconductor element is bonded and fixed via the Au—Sn alloy or the like of the solder layer 6. This prevents the Au in the main conductor layer 4 from diffusing into the solder layer 6 which also has an Au-Sn alloy isotropic force.
• the alloy composition becomes excessive (Au H), and the Au-Sn alloy cannot be completely melted at the soldering temperature (heating temperature). As a result, the bonding strength is reduced.
• Patent Document 1 Japanese Patent Laid-Open No. 2002-252316
• An object of the present invention is to suppress the generation of vacancies based on the reaction between a solder layer and a diffusion prevention layer when bonding a semiconductor element on a ceramic wiring board via a solder layer. It is an object of the present invention to provide a ceramic wiring board capable of preventing a reduction in bonding strength of semiconductor elements, a manufacturing method thereof, and a semiconductor device using such a ceramic wiring board.
• a ceramic wiring board includes a ceramic substrate, a wiring portion having a base metal layer, a first diffusion prevention layer, and a first Au layer, which are sequentially laminated on the surface of the ceramic substrate. And a wiring layer comprising a second diffusion prevention layer, a hole suppressing layer, and a connection part having a solder layer containing at least Sn, which are formed on the wiring part and stacked in order.
• a method for manufacturing a ceramic wiring board includes: laminating a base metal layer, a first diffusion prevention layer, and a first Au layer in this order on the surface of the ceramic substrate; Forming a connection portion in the wiring layer by sequentially laminating a second diffusion prevention layer, a hole suppressing layer, and a solder layer containing at least Sn on the wiring portion. It is characterized by doing.
• a semiconductor device includes a ceramic wiring board according to an aspect of the present invention, and an electrical and mechanical device on the wiring layer of the ceramic wiring board via the solder layer. And a semiconductor element connected to the semiconductor device.
• FIG. 1 is a cross-sectional view showing a configuration of a ceramic wiring board according to an embodiment of the present invention.
• FIG. 2 is a cross-sectional view showing a modified example of the ceramic wiring board shown in FIG.
• FIG. 3 is a diagram showing a configuration of a semiconductor device according to an embodiment of the present invention.
• FIG. 4 is a cross-sectional view showing a main configuration of a conventional ceramic wiring board.
• FIG. 1 is a cross-sectional view showing a configuration of a ceramic wiring board according to an embodiment of the present invention.
• a ceramic wiring substrate 10 shown in FIG. 1 has a ceramic substrate 11 as an insulating substrate.
• the ceramic substrate 11 include aluminum nitride (A1N) and silicon nitride (Si N).
• Oxide ceramics sintered body containing 4 2 3 as the main component is used.
• thermal conductivity For example, nitride ceramics are preferably used.
• silicon carbide (SiC) is also suitable for the substrate because of its thermal conductivity. However, since silicon carbide has conductivity, an insulating film is formed on the surface and applied to the substrate 11.
• a wiring layer 12 is formed on the main surface 11 a of the ceramic substrate 11.
• the wiring layer 12 is formed by, for example, a vacuum deposition method, a sputtering method, an ion plating method, a molecular beam epitaxy (MBE) method, a laser deposition method, a PVD method such as an ion beam deposition method, a thermal CV D method, a plasma CVD method.
• the film is formed by a thin film formation method such as a CVD method such as a photo-CVD method or a plating method.
• the wiring layer 12 has a wiring part 13 and a connection part 14.
• the wiring portion 13 has a base metal layer 15, a first diffusion prevention layer 16, and a first Au layer 17 as a main conductor layer, which are sequentially stacked on the ceramic substrate 11.
• the base metal layer 15 contributes to improvement in adhesion and adhesion strength between the ceramic substrate 11 and the wiring layer 12.
• the base metal layer 15 for example, at least one selected from Ti, Zr, Hf, Nb, Cr, Ta, and N and alloys based on these are used. Of these, when nitride ceramics are applied to the ceramic substrate 11, it is preferable to apply active metals such as Ti, Zr, Hf, and Nb.
• the thickness of the base metal layer 15 is not particularly limited, but is preferably in the range of 0.1 to 0.4 m, for example.
• the first diffusion preventing layer 16 prevents diffusion of elements between the ceramic substrate 11 or the base metal layer 15 and the first Au layer 17.
• the first diffusion preventing layer 16 for example, at least one selected from Pt, Pd and N and an alloy based on these are used.
• the first diffusion preventing layer 16 is appropriately selected depending on the constituent elements of the base metal layer 15 and the like. When Ni is applied to the base metal layer 15, other elements are used.
• the thickness of the first diffusion preventing layer 16 is preferably in the range of 0.1 to 0.4 m, for example.
• the first Au layer 17 functions as a main conductor layer of the wiring portion 13.
• the thickness of the first Au layer 17 is preferably in the range of 0.1 to 0.3 m, for example. If the thickness force of the first Au layer 17 is less than O. 1 m, the function as the main conductor layer may be deteriorated. Even if the thickness of the first Au layer 17 exceeds 0.3 m, it will not be possible to obtain any further effect, but will increase the manufacturing cost.
• the wiring unit 13 has a wiring pattern corresponding to a desired circuit shape, for example.
• a connecting portion 14 having a solder layer 18 is provided at a position where the wiring portion 13 is connected to the semiconductor element.
• connection part 14 is provided in a desired shape at a position corresponding to the electrode of the semiconductor element bonded and mounted on the ceramic wiring board 10, and has a function of electrically and mechanically connecting the wiring part 13 and the semiconductor element. It is what has.
• the connecting portion 14 has a shape corresponding to the electrode of the semiconductor element, for example, a shape such as a rectangle or a circle, and the size is also the same.
• Such a connection portion 14 includes a second diffusion prevention layer 19, a hole suppression layer 20, and a solder layer 18 that are sequentially stacked at desired positions on the wiring portion 13.
• the solder layer 18 also has a solder material strength including at least Sn.
• the solder layer 18 is made of Sn alone or Sn alloy containing at least one selected from Au, Ag, Al, Bi, Cu, Cr, Ga, Ge, Ni, Pt, Si, Ti, and Zn. It is done. Of these, the solder layer 18 is preferably composed of a Sn alloy.
• the amount of Sn in the Sn alloy is appropriately selected according to the type of elements used in combination, and is generally in the range of 15 to 99.9 mass%, for example.
• Typical examples of such Sn alloys (solder alloys) include Au—Sn alloys, Ag—Sn alloys, Cu—Sn alloys, and the like.
• the thickness of the solder layer 18 is preferably in the range of 1 to 5 ⁇ m, for example. If the thickness of the solder layer 18 is less than 1 ⁇ m, it reacts with the Au film provided on the electrode of the semiconductor element when it is bonded to the semiconductor element (mixing of the solder layer and the Au film), and compositional deviation tends to occur. As a result of this composition shift, the bonding layer is cured and stress is generated, which causes a defect such as a crack entering a semiconductor element (for example, a laser diode). On the other hand, even if the thickness exceeds 5 m, not only a further bonding effect cannot be obtained, but this also increases the manufacturing cost.
• the solder layer 18 is not limited to one formed of one kind of Sn alloy, and may be formed of a laminated film of two or more kinds of Sn alloys having different compositions, for example.
• the Sn alloy to be applied is not limited to two or more kinds of Sn alloys having different constituent elements, but may be two or more kinds of Sn alloys having different composition ratios of the same constituent elements.
• the melting state of the solder layer 18 can be controlled by configuring the solder layer 18 with two or more kinds of Au—Sn alloys having different composition ratios, that is, a laminated film of Au—Sn alloys having different melting temperatures. .
• the second diffusion preventing layer 19 prevents the diffusion of elements between the first Au layer 17 as the main conductor layer and the solder layer 18 having, for example, Sn alloy strength. Especially from Sn alloy etc. This prevents the Au in the main conductor layer from diffusing into the resulting solder layer 18 and the alloy composition from becoming Au-rich.
• the second diffusion preventing layer 19 is preferably formed of at least one selected from Pt, Pd and Ni and alloys based on these.
• the thickness of the second diffusion preventing layer 19 is preferably in the range of 0.05 to 1 ⁇ m. If the thickness of the second diffusion prevention layer 19 is less than 0.05 m, the above-described effect of preventing the diffusion of elements may not be sufficiently obtained. On the other hand, even if the thickness of the second anti-diffusion layer 19 is set to exceed l / z m, no further effect can be obtained, and conversely an increase in manufacturing cost will be caused.
• the hole suppressing layer 20 interposed between the second diffusion preventing layer 19 and the solder layer 18 has a second diffusion preventing layer when the solder layer 18 is heated and melted to join the semiconductor element. It prevents the 19 constituent elements (Pt, Pd, Ni, etc.) from reacting with Sn in the solder layer 18 to generate vacancies near the interface.
• the pore suppression layer 20 is preferably formed of Au or an Au—Sn alloy containing 85 mass% or more of Au.
• the reaction between the constituent elements of the second diffusion prevention layer 19 and Sn in the solder layer 18 can be suppressed. It can be suppressed.
• An Au-rich Au-Sn alloy containing 85 mass% or more of Au can achieve the same effect as the Au layer.
• the Sn itself may be involved in the reaction to generate pores. In other words, if the amount of Au is 85% by mass or more, it is possible to prevent Sn reaction that causes vacancies.
• the thickness of the hole suppressing layer 20 made of Au or an Au-rich Au-Sn alloy is preferably in the range of 30 to 500 nm. If the thickness of the vacancy suppression layer 20 is less than 30 nm, the diffusion of Sn cannot be completely suppressed, and the vacancy generation suppression effect may be reduced. On the other hand, when the thickness of the void suppression layer 20 made of Au or an Au-rich Au—Sn alloy exceeds 500 nm, the force depending on the thickness of the solder layer 18 Au in the void suppression layer 20 and the solder layer 18 May mix and cause a composition shift of the solder layer 18. The thickness of the pore suppression layer 20 is more preferably in the range of 100 to 300 nm.
• the semiconductor element is made of Au or an Au-rich Au—Sn alloy and has a thickness of 30 to 500 nm.
• the surrounding hole suppression layer 20 between the second diffusion prevention layer 19 and the solder layer 18, the second diffusion without causing an increase in the melting point due to a change in the composition of the solder layer 18 or the like. It is possible to suppress the formation of vacancies based on the reaction between the constituent elements of the prevention layer 19 and Sn in the solder layer 18 (diffusion of Sn). Therefore, it is possible to increase the bonding strength of the semiconductor element and the like, and to prevent an increase in the resistance of the connection portion 14 and an increase in the operating current of the semiconductor element based on the resistance. These contribute to the improvement of the reliability and operating characteristics of the semiconductor element.
• FIG. 1 shows a structure in which the second diffusion prevention layer 19 and the pore suppression layer 20 have the same shape as the solder layer 18, but the second diffusion prevention layer 19 is shown in FIG.
• the solder layer 18 may have a wider shape. That is, the outer periphery of the second diffusion preventing layer 19 may have a shape that protrudes from the end of the solder layer 18. It is preferable that the outer peripheral portion of the second diffusion preventing layer 19 protrudes from the end portion of the solder layer 18 over the entire periphery, but a part thereof may protrude from the end portion of the solder layer 18.
• the second diffusion preventing layer 19 having the shape as described above, the reaction with the first Au layer 17 due to the wetting and spreading of the solder layer 18 at the time of heat bonding, and the occurrence of defects based thereon are suppressed. It becomes possible to do. That is, the solder layer 18 is heated and melted and spreads when the semiconductor element or the like is joined. At this time, according to the second diffusion preventing layer 19 wider than the solder layer 18, wetting and spreading of the solder layer 18 can be suppressed. In other words, the wet spreading area of the solder layer 18 can be limited to the second diffusion prevention layer 19 having low wettability with respect to Sn alloy or the like.
• the shape of the second anti-diffusion layer 19 is such that its outer periphery protrudes from the end of the solder layer 18 in the range from 1 m to 100 m in order to obtain the effect of suppressing the expansion of the wet spreading area of the solder layer 18 It is preferable. [0033] If the amount of protrusion of the second diffusion preventing layer 19 from the end of the solder layer 18 is smaller than 1 ⁇ m, the solder layer 18 may melt and spread over the second diffusion preventing layer 19 when the solder layer 18 melts. There is.
• the protrusion amount of the second diffusion preventing layer 19 is more preferably equal to or more than the height of the solder layer 18. Considering the formation density of the connection portion 14 and the like, it is more preferable that the amount of protrusion of the second diffusion preventing layer 19 is 50 ⁇ m or less.
• the surface of the solder layer 18 is covered with an Au layer (third Au layer) 21 as shown in FIG.
• the Au layer 21 functions as an anti-oxidation layer for the solder layer 18. Furthermore, in this embodiment, the structure in which the wiring layer (metal laminated film) 12 is formed only on the main surface 11a of the ceramic substrate 11 has been described. However, as shown in FIG. The metal layer 15, the first diffusion preventing layer 16, and the Au layer 17 as the main conductor layer may be laminated in order.
• the conductor layer on the back surface ib side of the ceramic substrate 11 is used as a bonding metal layer, a ground conductor layer, or the like when the ceramic substrate 11 is mounted on an external circuit substrate or in a package.
• FIG. 3 shows the structure of a laser device to which the semiconductor device of the present invention is applied.
• 30 is a two-wavelength laser diode.
• the two-wavelength laser diode 30 includes, for example, a first light emitting element portion 31 having an emission wavelength of 650 nm and a second light emitting element portion 32 having an emission wavelength of 780 nm.
• Each of these light emitting element portions 31 and 32 is formed by crystal growth of a semiconductor layer on a GaAs substrate 33.
• Each light emitting element portion 31, 32 has electrodes 34, 35 individually.
• a common electrode 36 is formed on the back side of the GaAs substrate 33.
• Such a two-wavelength laser diode 30 is mounted on the ceramic wiring board 10 of the above-described embodiment.
• the ceramic wiring board 10 includes a first wiring layer 12A and a second wiring layer 12B, and has a wiring part 13 and a connection part 14, respectively.
• the electrode 34 of the first light emitting element portion 31 is joined to the connection portion 14 of the first wiring layer 12A.
• the electrode 35 of the second light emitting element portion 32 is joined to the connection portion 14 of the second wiring layer 12B.
• the two-wavelength laser diode 30 is composed of the first and second wiring layers 12A of the ceramic wiring board 10. 12B and the connection part 14 are electrically and mechanically connected. These constitute a laser device to which the semiconductor device of the present invention is applied.
• FIG. 3 shows an embodiment in which a laser diode is applied as a semiconductor element bonded and mounted on a ceramic wiring substrate, but the semiconductor device of the present invention is not limited to this.
• the semiconductor device of the present invention can be applied to a semiconductor device in which various semiconductor elements are mounted on a ceramic wiring board, but is particularly effective for a semiconductor device in which an optical semiconductor element such as a laser diode or a photodiode is mounted. .
• a substrate made of an aluminum nitride sintered body having a diameter of 75 mm and a height of 0.2 mm was prepared as the ceramic substrate 11.
• the first diffusion prevention layer 16 consisting of a 0.1 m thick Ti film to a base metal layer 15 and a 0.0 mm thick Pt film is formed on the surface by a notch method.
• a first Au layer 17 having a thickness of 0.5 m was sequentially laminated as the main conductor layer.
• the second diffusion prevention layer 19 and the void are formed by sputtering.
• the pore suppression layer 20 was laminated in order.
• the constituent materials and thicknesses of these layers 19 and 20 are as shown in Table 1, respectively.
• a solder layer 18 having a thickness of 2 m made of a Sn alloy having a composition of 70 mass% Au—30 mass% Sn was formed on the upper surface of the hole suppressing layer 20 by vacuum deposition. Each sample was diced to 2 mm ⁇ 2 mm and then subjected to the characteristic evaluation described later.
• a sample was prepared in the same manner as in Examples 1 to 7 except that the composition of the solder layer 18 was changed, and subjected to the characteristic evaluation described later.
• the composition of the solder layer 18 in Examples 12 to 16 is as shown in Table 1.
• a sample was prepared in the same manner as in Examples 1 to 7 except that the constituent material and thickness of the pore suppression layer 20 were changed, and subjected to the characteristic evaluation described later.
• the constituent materials and thickness of the pore suppression layer 20 in Examples 17 to 20 are as shown in Table 1.
• a sample was prepared in the same manner as in Examples 1 to 7 except that the formation of the pore suppression layer 20 was omitted, and was subjected to the characteristic evaluation described later.
• 70 mass% Au is applied to the solder layer 18.
• Comparative Example 2 is 82% by mass in solder layer 18
• Comparative Example 3 has 95 mass in solder layer 18
• Example 10 0.2 Au 100 70 Au-30Sn
• Sickle example 12 Pt 0.2 Au 100 65 Au-35Sn
• each wiring board on a heater block maintained at a temperature of about 330 to 350 ° C, and place the Si chip on the wiring board for bonding after about 5 seconds. .
• it is heated to a temperature of about 250-260 ° C
• a Cu-Sn solder alloy layer it is heated to a temperature of about 240-260 ° C.
• the Si chip is formed by depositing a 0.05 111 thick film, a 0.1 ⁇ m thick Pt film, and a 1.0 m thick Au film in this order on the bonding surface with the wiring board.
• mm XO.3mmX height 0.4mm. The mounting of the Si chip The test was carried out on four wiring boards.
• the Si chip and the wiring board are cut and polished perpendicularly to the bonding surface, and the inside of the bonding layer is observed by an electron microscope from the cross-sectional direction.
• the presence or absence of pores was evaluated.
• Judgment of the presence or absence of vacancies in the bonding layer is ⁇ when all observation samples have no vacancies, and one or more of the four observation samples have vacancies with a cross section of 1Z3 or less. ⁇ indicates that a hole is observed, X indicates that one or more samples have holes observed in a cross section with a length of 1Z3 or more, X indicates that all four observation samples have holes in the cross section XX It was.
• Example 7 since the thickness of the pore suppression layer was lOnm, some pores were observed inside the bonding layer. From the results of Examples including Example 7, it can be seen that the thickness of the pore suppression layer is preferably in the range of 30 to 500 nm. On the other hand, in Comparative Examples 1 to 3 in which the hole suppressing layer is not applied, holes are generated even in the deviation, and as a result, the adhesion to the semiconductor element is poor.
• a thickness of 0.0! ! ! ! of! ! A base metal layer 15 made of a film, a first diffusion prevention layer 16 made of a Pt film having a thickness of 0.2 m, and a first Au layer 17 having a thickness of 0.5 as a main conductor layer were laminated in this order.
• m is formed on the first Au layer 17 by a vacuum deposition method, a hole suppressing layer 20 made of an Au film having a thickness of lOOnm, and a thickness of 2 / A solder layer 18 made of a Sn alloy film having a composition of 65 mass% Au—35 mass% Sn of zm was formed in order.
• the shape of the second diffusion preventing layer 19 is such that the end force of the solder layer 18 protrudes by a predetermined length.
• the amount of protrusion of the second diffusion preventing layer 19 with respect to the solder layer 18 was ⁇ m in Example 21 and 50 ⁇ m in Example 22.
• Each of these samples was diced to 2 mm ⁇ 2 mm, and the characteristics were measured and evaluated in the same manner as in the previous examples.
• the complete melting time and wet spread state of the solder layer were measured and evaluated as follows. Table 3 shows the evaluation results for each example. The evaluation of the solder layer was also performed for Comparative Example 1 described above.
• the wiring board of each example was placed on the heater block, and while the inert gas was blown to prevent the surface of the oxide film from being formed on the surface, the gloss change of the solder layer surface was reduced by about 60%.
• the meltability (wettability) of the solder layer was evaluated by observing for 2 seconds. This utilizes the phenomenon that when the melting point of the solder layer rises above the holding temperature, a high melting point phase precipitates and the surface gloss is weakened.
• the determination of the complete melting time of the solder layer was evaluated by the time during which the surface gloss was maintained.
• the wet spreading state of the solder layer was observed and evaluated with a metal microscope (100 times magnification).
• the case where the wetting and spreading area of the solder layer was only on the second diffusion prevention layer was evaluated as X, and the case where the wetting and spreading area of the solder layer protruded onto the first Au layer was evaluated as X.
• Example 21 ⁇ ⁇ ⁇ 60 ⁇ 1892
• Example 22 ⁇ ⁇ ⁇ 60 ⁇ 2075 Comparative Example 1 XXX 13 X 242
• the reaction of the solder layer 18 with the first Au layer is achieved by making the shape of the second diffusion prevention layer 19 protrude from the end of the solder layer 18. It is possible to suppress an increase in melting point based on. As a result, the adhesion of the semiconductor element can be improved with high reproducibility.
• the ceramic wiring board of the present invention since the void suppressing layer is interposed between the second diffusion preventing layer and the Sn-containing solder layer, the bonding strength of the semiconductor element due to the generation of voids is low. It is possible to suppress an increase in operating current and down. Such a ceramic wiring board is useful as a substrate for mounting semiconductor elements. Furthermore, by using the ceramic wiring board of the present invention, it is possible to provide a semiconductor device having excellent reliability and operating characteristics with good reproducibility.

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• Engineering & Computer Science (AREA)
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• Microelectronics & Electronic Packaging (AREA)
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• Parts Printed On Printed Circuit Boards (AREA)
• Manufacturing Of Printed Wiring (AREA)

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