WO2006041161A1 - 配線基板及びその製造方法 - Google Patents
配線基板及びその製造方法 Download PDFInfo
- Publication number
- WO2006041161A1 WO2006041161A1 PCT/JP2005/018972 JP2005018972W WO2006041161A1 WO 2006041161 A1 WO2006041161 A1 WO 2006041161A1 JP 2005018972 W JP2005018972 W JP 2005018972W WO 2006041161 A1 WO2006041161 A1 WO 2006041161A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- layer
- bump
- metal foil
- opening
- insulating layer
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4647—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer around previously made via studs
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0347—Overplating, e.g. for reinforcing conductors or bumps; Plating over filled vias
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0355—Metal foils
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/0969—Apertured conductors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09745—Recess in conductor, e.g. in pad or in metallic substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
- H05K2203/0703—Plating
- H05K2203/0733—Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
Definitions
- the present invention relates to a wiring board that performs interlayer connection with bumps and a method for manufacturing the same, and more particularly to a multilayer wiring board having two or more wiring layers.
- the present invention relates to a novel wiring board in which a conductor layer formed on a bump is composed of a copper foil and a plating layer, and ensures reliability of connection and bonding, and a method for manufacturing the same.
- the invention described in Patent Document 1 relates to a selective etching method and a selective etching apparatus for bump formation.
- a multilayer wiring circuit board manufacturing technique one of the main copper layers for bump formation is used.
- a multilayer circuit board is formed by forming an etching noria layer on the surface and using a wiring circuit board forming member having a copper foil for forming a conductor circuit on the main surface of the etching barrier layer as a base and processing it appropriately.
- a technique for obtaining the above is disclosed.
- the copper layer of the wiring circuit board forming member is selectively etched to form bumps for interlayer connection, and the bumps are filled with an insulating layer. Insulate between.
- a copper foil for forming a conductor circuit is formed on the upper surface of the insulating layer and bumps.
- a wiring film is formed by selectively etching the upper and lower copper foils. As a result, a multilayer wiring board having upper and lower wiring films and having the wiring films connected by bumps is formed.
- Patent Document 1 Japanese Patent Laid-Open No. 2003-129259 Disclosure of the invention
- the copper foil and the bump are electrically connected by molding thermocompression bonding, so that the connection reliability is low.
- a copper foil for forming a conductor circuit is formed on the insulating layer and the upper surface of the bump after the bump is formed.
- the copper foil is bonded to the insulating layer by thermocompression bonding.
- the copper foil and the insulating layer are bonded by a so-called anchor effect by the resin constituting the insulating layer entering the fine irregularities on the surface of the copper foil.
- the copper foil and the front end surface of the bump are simply in contact with each other, and there are many problems in terms of connection reliability, such as a connection failure caused by a slight external force with weak bonding force.
- connection reliability between the copper foil and the bump is low, and the insulating material (resin material) that can be used for the insulating layer in order to ensure the reliability is greatly restricted. Then, he also has a defect.
- the thickness of the insulating layer is limited to 60 m or less, and the insulating material used also has a high glass transition point and a low linear expansion coefficient. Having limited to insulating materials. These restrictions are not preferable, because they lead to restrictions on the design of multilayer wiring boards and increased manufacturing costs!
- the present invention has been proposed in view of such a conventional situation, and can sufficiently ensure the connection reliability between the wiring layer (conductor layer) and the bump, and also has a restriction on the insulating layer.
- the purpose is to provide a wiring board with a small amount of metal, and further to provide a manufacturing method thereof.
- the present invention includes a wiring layer disposed on one side of an insulating layer, and a bump disposed inside the insulating layer and electrically connected to the wiring layer.
- the wiring layer includes: a patterned metal foil; an opening formed on the metal foil, with a front end surface of the bump exposed on a bottom surface; and the metal foil and the front end surface of the bump.
- It is a wiring board having a close contact layer and a metal layer for electrically connecting the metal foil and the bump.
- the present invention is the wiring board in which another wiring layer is disposed on the opposite surface of the insulating layer, and the wiring layers located on both surfaces of the insulating layer are electrically connected by the bumps.
- the present invention is the wiring board, wherein the adhesive layer has a connection layer formed by an electrolytic plating method.
- the present invention is the wiring board in which a concave portion is formed on the tip end surface of the bump, and the adhesive layer is in close contact with the concave portion.
- the insulating layer around the bump is exposed at the bottom surface of the opening, and the adhesive layer is in close contact with the insulating layer at the bottom surface of the opening.
- the adhesive layer is formed by electrolyzing the tip surface of the bump, the wiring layer, a base conductive layer in close contact with the insulating layer on the bottom surface of the opening, and the base conductive layer. It is a wiring substrate having a connection layer grown by a method.
- the metal foil has a thickness of 5 m or more and 10 m or less
- the adhesion layer has a thickness of 10 ⁇ m or more and 15 ⁇ m or less.
- the present invention provides a step of attaching a metal foil having an opening on an insulating layer having a bump with an exposed end surface exposed therein so that the end surface of the bump is exposed on the bottom surface of the opening; Production of a wiring board having a step of growing a connection layer on the tip surface of the bump and the metal foil by an electrolytic plating method, and patterning the connection layer and the metal foil to form a wiring layer Is the method.
- the present invention is a method for manufacturing a wiring board in which a connection conductive layer is grown after a base conductive layer is grown at least on the bottom surface of the opening by an electroless plating method.
- the present invention is the method for manufacturing a wiring board, wherein the insulating layer is exposed on a bottom surface of the opening, and the base conductive layer is formed on at least the insulating layer on the bottom surface of the opening.
- the present invention also includes a step of attaching a metal foil on an insulating layer having a bump inside, and a step of forming an opening at a position on the bump of the metal foil to expose a front end surface of the bump. And a step of growing a connection layer on the front end surface of the bump and the metal foil by an electroplating method, and a step of patterning the connection layer and the metal foil to form a wiring layer.
- the present invention is the method for manufacturing a wiring board, wherein the insulating layer is exposed on a bottom surface of the opening, and the base conductive layer is formed on at least the insulating layer on the bottom surface of the opening.
- a major feature of the wiring board of the present invention is that the conductor layer connected to the bump is composed of a metal foil and a plating layer.
- the metal foil is formed to ensure bonding strength with respect to the insulating layer, and as described above, the resin constituting the insulating layer enters the fine irregularities on the surface of the metal foil, so that the insulating layer is formed by a so-called anchor effect. Are firmly bonded to each other.
- an opening is formed in the metal foil corresponding to the bump, and the adhesive layer is formed in contact with the tip end surface of the bump in the opening.
- the plated layer is in a state of being firmly bonded to the front end surface of the bump by so-called metal bonding, so that the electrical connection between the bump and the plated layer is sufficiently ensured, and connection reliability is ensured.
- the conductor layer may be composed of only the adhesive layer. In this case, it is difficult to ensure adhesion to the insulating layer.
- the surface of the insulating layer may be roughened to form irregularities, and the adhesive layer may enter here, but the surface roughness of the insulating layer should be appropriate. It is difficult to control the thickness of the plating layer, and even if appropriate irregularities are formed, the plating layer does not penetrate sufficiently, and in reality it is difficult to ensure sufficient adhesion.
- the insulating layer is limited to a resin material with good adhesion to adhesion
- the plating layer is limited to plating with good adhesion to the resin material to improve the adhesion between the insulating layer and the plating layer.
- the conductor layer connected to the bump is composed of the metal foil and the adhesive layer, and the adhesion to the insulating layer is ensured by the metal foil, so that the electrical contact with the bump is achieved. Connection is ensured by a mating layer. Therefore, both electrical connection reliability and mechanical connection reliability are compatible, and restrictions on the materials used and an increase in manufacturing costs are avoided.
- the present invention electrical connection reliability between the wiring layer (conductor layer) and the bump can be sufficiently ensured, and at the same time, the mechanical connection strength between the insulating layer and the conductor layer is sufficient. It is possible to secure. Therefore, according to the present invention, it is possible to provide a highly reliable wiring board. Further, in the present invention, a resin material, an eyeglass used for an insulating layer or an adhesive layer. Since there are few restrictions on the wiring material, etc., the material design of the wiring board can be facilitated, and the increase in manufacturing cost can be suppressed.
- FIG. 1 shows a manufacturing process of the first embodiment
- (a) is a cross-sectional view showing a clad material
- (b) is a cross-sectional view showing a bump forming step
- (c) is an insulating layer.
- (D) is a sectional view showing a metal foil laminating step
- (e) a sectional view showing a fitting resist layer forming step
- (f) a sectional view showing a fitting layer forming step
- (d) g) is a cross-sectional view showing a fitting resist layer peeling step
- (h) is a cross-sectional view showing a conductor layer patterning step.
- FIG. 2 shows the manufacturing process of the second embodiment, wherein (a) is a cross-sectional view showing a metal foil bonding step, (b) is a cross-sectional view showing an opening forming step, and (c) fitting. Cross-sectional view showing the resist layer forming process, (d) Cross-sectional view showing the fitting layer forming step, (e) Cross-sectional view showing the fitting resist layer peeling step, (f) showing the conductor layer patterning step It is sectional drawing.
- FIG. 3 A manufacturing process of a modified example, showing steps after the steps of FIGS. 1 (a) to (: c), (a) is a cross-sectional view showing a metal foil bonding step, and (b) fits. Cross-sectional view showing an adhesive resist layer forming process, (c) a cross-sectional view showing a base adhesive layer forming process, (d) a sectional view showing an adhesive layer forming process, and (e) an adhesive resist layer peeling process. Sectional view (f) is a sectional view showing the conductor layer patterning process.
- FIG. 4 is a cross-sectional view of a wiring board in which a base conductive layer is formed on the bottom surface of a large-diameter opening by an electroless plating method, and a connection layer is grown thereon by an electrolytic plating method.
- Each embodiment is a multilayer wiring board in which wiring layers are formed on both surfaces of an insulating layer.
- the present invention is not limited to this, for example, bumps may connect the wiring layer and other conductors.
- a structure in which insulating layers and wiring layers are alternately stacked may be employed.
- This embodiment is an example of a manufacturing process in which openings are formed in advance in a metal foil constituting a conductor layer, and a wiring board manufactured thereby.
- a bump metal foil 1 for forming a bump, an etching barrier layer 2 made of Ni, and a first wiring layer are formed.
- a clad material formed by laminating the first metal foil 3 is prepared.
- the etching barrier layer 2 is a material having etching selectivity with respect to the bump metal foil 1 and serving as an etching stopper when the bump metal foil 1 is etched. Etchants that etch will not etch or have a slow etch rate.
- the etching barrier layer 2 has conductivity, and the bump metal foil 1 and the first metal foil 3 are electrically connected via the etching noor layer 2. Accordingly, the first wiring layer 14 and the bump 4 described later are electrically connected via the etching barrier layer 2.
- the first metal foil 3 is formed by etching the bump metal foil 1 and the etching barrier layer 2 before the force patterning that is finally formed into a wiring layer by patterning. It also functions as a support for supporting the bumps.
- the bump metal foil 1 is etched to form bumps 4.
- the bump metal foil 1 is etched with an acidic etchant. It is preferable to carry out in combination with etching with an alkaline etching solution. That is, after forming a resist film (not shown) as a mask on the bump metal foil 1.
- Etching force of 1 Etching depth by this acidic etching solution is smaller than the thickness of the bump metal foil 1 and is performed within a range where the etching barrier layer 2 is not exposed.
- the remaining portion of the bump metal foil 1 is etched with an alkaline etching solution (eg, ammonium hydroxide).
- an alkaline etching solution eg, ammonium hydroxide.
- the alkaline etching solution hardly invades Ni constituting the etching noble layer 2. Therefore, the etching barrier layer 2 functions as a stopper for etching with the alkaline etching solution.
- the pH of the alkaline etching solution is preferably 8.0 or less.
- the etching barrier layer 2 can also be removed. In this case, only the Ni that is the etching barrier layer 2 is removed by etching, and the first metal foil 3 therebelow is removed. Use almost no erosion! / ⁇ etchant.
- the insulating layer 5 is formed so as to fill the gaps between the bumps 4, and after the formation of the insulating layer 5, the front end surfaces 4a of the bumps 4 are exposed. For example, polishing the surface
- the insulating layer 5 can be formed, for example, by applying a resin material such as polyimide, or by thermocompression bonding of a resin film.
- a resin material such as polyimide
- thermocompression bonding of a resin film any material can be selected according to the characteristics and the like, in particular, it is not necessary to consider the adhesion to the galling, glass transition point, linear expansion coefficient and the like. Also, its thickness is not limited.
- a second metal foil 6 to be a second wiring layer is bonded onto the tip of the bump 4 by a technique such as thermocompression bonding.
- openings 7 are formed in advance in the second metal foil 6 corresponding to the positions of the bumps 4.
- the opening 7 of the second metal foil 6 can be formed by various methods.
- mechanical drilling such as drilling, laser drilling force, etching It can be formed by drilling or the like.
- the size of the opening 7 is substantially the same as the size of the front end surface 4a of the bump 4.
- the size of the opening 7 is set to the bump 4 Preferred to set larger than the size of.
- the opening 7 needs to have a certain size.
- the size of the opening 7 may be determined in consideration of the above matters according to the design of the wiring board.
- the diameter of the front end surface 4a of the bump 4 is about 50 ⁇ m, and therefore the diameter of the opening 7 is preferably set to about 80 ⁇ m or more and 120 ⁇ m or less.
- an alignment marker such as an alignment hole is formed in the second metal foil 6 or the insulating layer 5 so that they are accurately aligned with each other. It is preferable to paste them together.
- the surface of the second metal foil 6 can be designed with an emphasis on adhesion to the insulating layer 5 without considering the electrical connection with the bumps 4. For example, if the surface of the second metal foil 6 on the side in contact with the insulating layer 4 is made rough and fine irregularities are formed, the resin material constituting the insulating layer 4 enters here, and the anchor effect causes Mechanical connection strength is ensured. Alternatively, an oxide film may be formed on the surface of the second metal foil 6 in contact with the insulating layer 4 in consideration of adhesion to the insulating layer 4. Further, the thickness of the second metal foil 6 is compensated by a later-described adhesive layer, and therefore may be about 5 ⁇ m to 10 ⁇ m.
- a plating resist layer 8 is formed so as to cover the entire surface of the bump metal foil 1 on the back surface side.
- the plating resist layer 8 is formed so that a plating layer is not formed on the bump metal foil 1.
- the bump metal foil 1 is used to compensate for the thin bump metal foil 1.
- this adhesive resist layer 8 need not be formed.
- connection layer 9 is formed.
- the connection layer 9 is formed on the entire surface where the second metal foil 6 is bonded, including the inside of the opening 7. Since the connection layer 9 is formed on the second metal foil 6 and the bumps 4, it can be composed of a plated metal layer grown by electrolytic plating.
- the thickness of the connection layer 9 formed by the electroplating method is about 10 m to 15 m, whereby the thickness of the entire conductor layer combined with the thickness of the second metal foil 6 is obtained. Can be about 20 m.
- connection layer 9 After the formation of the connection layer 9, as shown in Fig. 1 (g), the plating resist layer 8 formed on the back side is peeled off, and as shown in Fig. 1 (h), the conductive layers on both the front and back sides are formed.
- the second metal foil 6 and the connection layer 9 and the first metal foil 3) are patterned according to the desired wiring pattern to form the first wiring layer 14 from the first metal foil 3.
- a second wiring layer 15 is formed from the second metal foil 6.
- the second wiring layer 15 includes a patterned second metal foil 6 and a connection layer 9 on the surface thereof.
- the patterning can be performed by ordinary phytolitho technology and etching technology.
- both the tip surface 4a of the bump 4 and the connection layer 9 and between the same connection layer 9 and the second metal foil 6 are strengthened by metal bonding.
- the bumps 4 and the second metal foil 6 constituting the second wiring film 15 are connected by the connection layer 9. Thereby, electrical connection reliability is sufficiently ensured.
- the second metal foil 6 and the insulating layer 5 are bonded with sufficient mechanical strength and good adhesion.
- the insulating layer 5 is exposed around the front end surface 4a of the bump 4, and the electrolytic plating does not grow in that portion.
- the metal foil 6 is no longer electrically connected.
- a second metal foil 6 having a large opening 7 is pasted and a plating resist layer 8 is pasted on the surface of the first metal foil 3 on the back surface (Fig.
- a base conductive layer 10 is formed on the surface of the insulating layer 5 exposed around the tip surface 4a of the bump 4 by an electroless plating method (FIG. (C)).
- the base conductive layer 10 also grows on the surface of the second metal foil 6 and the tip surface 4 a of the bump 4.
- the force underlying conductive layer 10 that also grows on the surface of the plating resist layer 8 needs to be formed on at least the surface of the insulating layer 5.
- the underlying conductive layer 10 is preferably in contact with the second metal foil 6.
- connection layer 9 grows on the surface of the base conductive layer 10 on the second metal foil 6 side by the electrolytic plating method ((d) in the figure) ).
- the plating layer in this example has a two-layer structure of the base conductive layer 10 and the connection layer 9.
- the plating resist layer 8 is peeled off (FIG. (E)) and the base conductive layer 10 and the connection layer 9 are put together to pattern the second metal foil 6 in the same manner as described above.
- a wiring substrate 12 is obtained in which the second wiring layer 16 and the bump 4, which are composed of the base conductive layer 10 and the connection layer 9, are electrically connected to each other by the base conductive layer 10 and the connection layer 9.
- connection layer 9 is in close contact with the tip 4a of the bump 4, the second metal foil 6 surface, and the portion constituting the inner peripheral surface of the opening 7, and the electrical and mechanical 1S
- the underlying conductive layer 10 is mechanically and electrically connected to the tip surface 4a of the bump 4, the surface of the second metal foil 6, and the inner peripheral surface of the opening 7.
- the connection layer 9 is formed on the lower conductive layer 10, and the electrical conductivity and strength are improved, and the connection is ensured.
- the underlying conductive layer 10 can be formed not only by an electroless plating method but also by a dry plating method such as a sputtering method or a vapor deposition method.
- the present embodiment is an example of a manufacturing process in the case where an opening is formed after a metal foil constituting a conductor layer is previously bonded onto an insulating layer, and a wiring board manufactured thereby.
- the formation of the bump and the insulating layer is the same as the process of the first embodiment, and the invention is omitted here.
- second metal foil 6 is bonded together. At this time, no opening is formed in the second metal foil 6, and therefore, the second metal foil 6 can be bonded without special positioning.
- openings 7 are formed in the second metal foil 6 corresponding to the positions where the bumps 4 are formed.
- the opening 7 can be formed by using the same technique as described in the first embodiment. However, in the case of this embodiment, mechanical drilling such as drilling is difficult.
- the opening 7 is formed by a drilling force by etching or a drilling force by etching.
- a drilling force by etching it is necessary to perform a drilling process corresponding to the position of the bump 4, and a force for drilling while aligning with respect to some reference, for example, a drilling force by etching.
- drilling is performed by patterning based on the bump 4 formation pattern.
- connection layer 9 is formed.
- the manufacturing process after the opening 7 is formed is the same as in the first embodiment. That is, as shown in FIG. 2 (c), after forming the plating resist layer 8 covering the entire surface of the bump metal foil 1 on the back side, the connection layer 9 is formed as shown in FIG. 2 (d). To do.
- the connection layer 9 is formed on the entire surface where the second metal foil 6 is bonded, including the inside of the opening 7 (inside the recess 4b of the bump 4).
- the plating resist layer 8 formed on the back side is peeled off as shown in FIG.
- the conductor layer consisting of the metal foil 6 and the connection layer 9 and the first metal foil 3) are patterned according to the desired wiring pattern, and the first metal foil 3 to the first wiring layer. 14 is formed, and the second wiring layer 15 is formed from the second metal foil 6.
- the second wiring layer 15 includes a second metal foil 6 that has been turned and a connection layer 9 on the surface thereof.
- connection layer 9 and the second metal foil 6 that are the same between the tip surface 4a of the bump 4 and the connection layer 9 are firmly bonded by metal bonding. Therefore, sufficient electrical connection reliability is ensured.
- connection reliability will be further improved.
- the second metal foil 6 and the insulating layer 5 are bonded with sufficient mechanical strength and good adhesion, even in the wiring board of this embodiment, electrical connection reliability and mechanical Connection reliability is achieved and a highly reliable wiring board is realized in all aspects.
- connection layer 9 that connects the second metal foil 6 and the bump 4 is at least on the tip of the bump 4 and the surface of the second metal foil 6 that forms the inner side surface of the opening 7.
- the bumps 4 need not be formed on the surface of the second metal foil 6 outside the opening 7.
- the connection layer 9 is grown to the extent that the opening 7 is filled, the electrical connection is more reliable, and when the opening 7 is filled, the second wiring layer 16 is patterned. Convenient when going to Jung.
- Metal foils are suitable for the first and second metal foils 3 and 6 and the bump metal foil 1, but the present invention is not limited thereto, and various other types of copper alloy foils may be used. Metal or conductive material films can be used. The first metal foil 3 and the second metal foil 6 are different materials.
- the insulating layer 5 is a flexible material, and the wiring boards 11 to 13 of the present invention are It has flexibility and can be bent, but the present invention is not limited thereto.
- the insulating layer 5 may be a material that is not tightly foldable. Also, it may be a multi-layer structure, or it may be a laminate of a material that is rigid and flexible.
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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JP2006540985A JPWO2006041161A1 (ja) | 2004-10-15 | 2005-10-14 | 配線基板及びその製造方法 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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JP2004300891 | 2004-10-15 | ||
JP2004-300891 | 2004-10-15 |
Publications (1)
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WO2006041161A1 true WO2006041161A1 (ja) | 2006-04-20 |
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PCT/JP2005/018972 WO2006041161A1 (ja) | 2004-10-15 | 2005-10-14 | 配線基板及びその製造方法 |
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WO (1) | WO2006041161A1 (ja) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0715140A (ja) * | 1993-06-25 | 1995-01-17 | Hitachi Chem Co Ltd | 多層プリント配線板の製造方法 |
JPH07263862A (ja) * | 1994-03-18 | 1995-10-13 | Hitachi Ltd | 多層配線基板の製造方法 |
JP2004047587A (ja) * | 2002-07-09 | 2004-02-12 | Eastern Co Ltd | 配線回路基板の製造方法および配線回路基板 |
-
2005
- 2005-10-14 WO PCT/JP2005/018972 patent/WO2006041161A1/ja active Application Filing
- 2005-10-14 JP JP2006540985A patent/JPWO2006041161A1/ja not_active Withdrawn
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0715140A (ja) * | 1993-06-25 | 1995-01-17 | Hitachi Chem Co Ltd | 多層プリント配線板の製造方法 |
JPH07263862A (ja) * | 1994-03-18 | 1995-10-13 | Hitachi Ltd | 多層配線基板の製造方法 |
JP2004047587A (ja) * | 2002-07-09 | 2004-02-12 | Eastern Co Ltd | 配線回路基板の製造方法および配線回路基板 |
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JPWO2006041161A1 (ja) | 2008-05-22 |
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