WO2006041013A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- WO2006041013A1 WO2006041013A1 PCT/JP2005/018556 JP2005018556W WO2006041013A1 WO 2006041013 A1 WO2006041013 A1 WO 2006041013A1 JP 2005018556 W JP2005018556 W JP 2005018556W WO 2006041013 A1 WO2006041013 A1 WO 2006041013A1
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- WIPO (PCT)
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- semiconductor device
- semiconductor chip
- resin layer
- external connection
- semiconductor
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Definitions
- the present invention relates to a semiconductor device having substantially the same size as a semiconductor chip.
- CSP chip size packages
- MCM multichip modules
- FIG. 12 is a schematic cross-sectional view showing the structure of a conventional semiconductor device having a chip size package structure.
- the semiconductor device 71 includes a semiconductor chip 72.
- a functional element 72a is formed on one surface of the semiconductor chip 72, and an insulating film 73 is formed so as to cover the functional element 72a.
- An opening 73a is formed in the insulating film 73 to expose the electrode of the functional element 72a.
- a rewiring 74 having a predetermined pattern is formed on the insulating film 73.
- the rewiring 74 is connected to the electrode of the functional element 72a through the opening 73a of the insulating film 73.
- a protective resin layer 77 is provided on the one surface of the semiconductor chip 72 so as to cover the insulating film 73 and the rewiring 74.
- the side surface of the semiconductor chip 72 and the side surface of the protective resin layer 77 are flush with each other, and the outer shape of the semiconductor device 71 has a substantially rectangular parallelepiped shape. Therefore, the size of the semiconductor device 71 substantially matches the size of the semiconductor chip 72 when viewed from the direction perpendicular to the semiconductor chip 72.
- columnar external connection terminals 75 penetrating the protective resin layer 77 are erected.
- a solder ball 76 as an external connection member is joined to the tip of the external connection terminal 75.
- This semiconductor device 71 can be mounted on a mounting substrate by bonding solder balls 76 to electrode pads formed on the mounting substrate.
- FIG. 13 shows the structure of a conventional semiconductor device having a multichip module structure.
- the semiconductor device 81 includes a wiring board 82, a semiconductor chip 83 stacked on the wiring substrate 82, and a semiconductor chip 84 stacked on the semiconductor chip 83.
- Functional elements 83a and 84a are formed on one surface of each of the semiconductor chips 83 and 84, respectively.
- the semiconductor chip 83 is bonded onto the wiring board 82 in a so-called face-up state in which the surface on which the functional element 83a is formed is directed to the opposite side of the wiring board 82.
- a semiconductor chip 84 is joined in a face-up posture with the functional element 84a facing away from the semiconductor chip 83.
- An interlayer sealing material 86 is interposed between the semiconductor chip 83 and the semiconductor chip 84.
- the semiconductor chip 83 When viewed from the direction perpendicular to the surface on which the functional elements 83a and 84a are formed, the semiconductor chip 83 is located on the periphery of the surface where the semiconductor chip 84 of the semiconductor chip 83 larger than the semiconductor chip 84 is bonded. There is a region where 84 is not opposed. In this region, an electrode pad 83b connected to the functional element 83a is formed. An electrode pad 84b connected to the functional element 84a is formed on the periphery of the surface of the semiconductor chip 84 where the functional element 84a is formed.
- the wiring board 82 When viewed from the direction perpendicular to the wiring board 82, the wiring board 82 is larger than the semiconductor chip 83.
- the semiconductor chip 83 faces the peripheral portion of the surface of the wiring board 82 to which the semiconductor chip 83 is bonded. There are no areas. In this region, an electrode pad (not shown) is provided, and the electrode pad and the electrode pads 83b and 84b are connected via bonding wires 87 and 88, respectively.
- the semiconductor chips 83 and 84 and the bonding wires 87 and 88 are sealed with a mold resin 89.
- a solder ball 85 as an external connection member is provided on the surface of the wiring substrate 82 opposite to the surface to which the semiconductor chip 83 is bonded.
- the electrode pads to which the bonding wires 87 and 88 of the wiring board 82 are connected are redistributed on the surface and inside of the wiring board 82 and connected to the solder balls 85.
- Patent Document 1 Japanese Patent Laid-Open No. 2002-118224
- Patent Document 2 Japanese Patent Laid-Open No. 2000-270721
- the solder balls 76 are two-dimensionally arranged on the surface of the protective resin layer 77 opposite to the semiconductor chip 72 (hereinafter referred to as “bottom surface”) 7 la. (Area array)
- the solder balls 85 are two-dimensional (area) on the surface (hereinafter referred to as “bottom surface”) 81a of the wiring board 82 opposite to the semiconductor chips 83, 84. It is arranged in an array.
- solder balls 76 and 85 provided in the inner regions of the bottom surfaces 71a and 81a are favorably applied to the electrode pads on the mounting board. It was difficult to confirm whether or not the joint was connected.
- voids may be introduced into the solder balls 76 and 85 when the solder balls are formed.
- the solder balls 76 and 85 in which the voids are introduced may cause poor connection to the mounting board.
- the semiconductor device 81 shown in FIG. 13 requires a wiring substrate 82 larger than the semiconductor chip 83 in order to secure the connection region for the bonding wires 87 and 88.
- the size of the semiconductor device 81 (package), in particular, the size force viewed perpendicularly to the wiring board 82 becomes larger than the semiconductor chips 83 and 84. For this reason, the mounting area of the semiconductor device 81 with respect to the mounting substrate is large.
- the semiconductor device 71 shown in FIG. 12 When using the semiconductor device 71 shown in FIG. 12 to mount a plurality of semiconductor chips 72 on a mounting substrate, the plurality of semiconductor devices 71 must be mounted side by side on the mounting substrate. Therefore, a large mounting area is required.
- An object of the present invention is to provide a semiconductor device capable of easily confirming a bonding state with a mounting substrate when bonded to the mounting substrate.
- Another object of the present invention is to provide a semiconductor device having a chip size and capable of improving the reliability of external connection.
- Still another object of the present invention is to have a multi-chip module structure and a low mounting area. It is to provide a reduced semiconductor device.
- a semiconductor device of the present invention includes a first semiconductor chip having a first functional surface on which a first functional element is formed, a protective resin layer formed on the first functional surface, and the first functional surface.
- a bottom exposed surface that is formed at a peripheral portion on the functional surface and is exposed from the bottom surface located on the opposite side of the first functional surface side of the protective resin layer, and a side exposed surface exposed from the side surface of the protective resin layer And an external connection terminal for electrical connection with the outside.
- the external connection terminal since the external connection terminal has an exposed surface on the side surface of the protective resin layer, when the semiconductor device is mounted on the mounting substrate, the external connection terminal is connected to the electrode pad on the mounting substrate. Since the connection state can be easily visually recognized, the connection (bonding) state between the semiconductor device and the mounting substrate can be easily confirmed.
- the semiconductor device and the mounting substrate can be connected by, for example, solder.
- the solder can be formed in advance as a film on the electrode pad of the mounting substrate as cream solder or a melted and solidified product thereof. Since it is difficult for voids to be introduced into such a form of solder, the reliability of external connection can be improved.
- this semiconductor device can be connected to the mounting substrate not only through the exposed surface having the bottom surface force but also through the exposed surface having the side force in the external connection terminal, the high bonding strength and the connection reliability. Can be secured.
- the external connection terminal may be electrically connected to the first semiconductor chip (first functional element).
- an external connection terminal that may be provided with an insulating film in which an opening for exposing the electrode of the first functional element is formed on the first functional surface is provided through the opening of the insulating film. 1 is connected to the rewiring connected to the electrode of the functional element.
- the semiconductor device of the present invention is formed in the central region inward from the peripheral region where the external connection terminals are formed on the first functional surface.
- a heat dissipating terminal having an exposed surface on the bottom surface may be further included.
- the heat generated in the first semiconductor chip can be dissipated through the heat dissipation terminal. Since the heat dissipating terminal has an exposed surface on the bottom surface of the protective resin layer, heat can be dissipated efficiently.
- the heat dissipating terminal is an external connection located on the periphery of the first functional surface. It can be made large enough not to contact the terminal, and this can improve the heat dissipation of the heat dissipation terminal.
- the heat radiating terminal may be electrically connected to the first functional element through an opening formed in the insulating film, for example, by rewiring.
- the heat radiation terminal may be a power supply wiring for supplying a voltage to the first functional element or a ground wiring for grounding the first functional element. In this case, the operation of the first semiconductor chip (functional element) can be stabilized.
- the heat radiating terminal may not be electrically connected to the first functional element.
- the heat dissipation terminal can have the same material force as the external connection terminal.
- the external connection terminal and the heat dissipation terminal can be formed together by electrolytic plating.
- the semiconductor device of the present invention has a second functional surface on which a second functional element is formed, and is connected to the first semiconductor chip with the second functional surface opposed to the first functional surface, and
- the semiconductor device may further include a second semiconductor chip having a size smaller than that of the first semiconductor chip in a plan view perpendicular to the functional surface.
- the semiconductor device of the present invention is mounted on the mounting substrate with the bottom surface of the protective resin layer from which the external connection terminals are exposed facing the mounting substrate. As a result, the first semiconductor chip and the second semiconductor chip are stacked on the mounting substrate. Therefore, this semiconductor device can reduce the mounting area as compared with the case where the first semiconductor chip and the second semiconductor chip are separately mounted on the mounting substrate in the lateral direction.
- the second semiconductor chip has a size that can be included in a region occupied by the first semiconductor chip in a plan view perpendicular to the first functional surface. Therefore, although it is a multi-chip module, its mounting area can be reduced to the size of the first semiconductor chip viewed perpendicularly to the first functional element.
- a concave portion may be formed on the side surface of the protective resin layer.
- the external connection terminal is formed along the inner surface of the concave portion, and has a shape corresponding to the inner shape of the concave portion. You may include the concave part which has.
- the concave surface portion extends along the inner surface of the concave portion formed on the side surface of the protective resin layer. Is formed. Therefore, on the side surface of the protective resin layer, the exposed surface of the external connection terminal (the surface of the concave portion) has a curved surface (curved surface or bent surface), and the exposed surface of the external connection terminal is a flat surface. The surface area is large. As a result, the bonding area (solder wetted area) with the mounting substrate can be increased and the bonding strength can be increased.
- the side surface of the first semiconductor chip and the side surface of the protective resin layer may be substantially flush with each other.
- the protective resin layer can protect the structure on the first functional surface side and reduce the mounting area of the semiconductor device.
- This semiconductor device includes a semiconductor substrate in which a plurality of first semiconductor chips are fabricated (for example,
- a semiconductor wafer In this case, for example, the semiconductor substrate is electrically connected to the functional element of each first semiconductor chip in a region extending across the adjacent first semiconductor chips when the semiconductor substrate is viewed vertically, and the protective substrate is protected.
- a columnar electrode that penetrates the oil layer in the thickness direction (direction orthogonal to the semiconductor substrate) can be formed.
- the semiconductor device of the present invention can be manufactured by cutting the semiconductor substrate along the boundary between the adjacent first semiconductor chips.
- the cut columnar electrode becomes an external connection terminal.
- the one on the side surface of the protective resin layer is flush with the side surface of the protective resin layer.
- the external connection terminal includes a concave portion formed in the concave portion, for example, a semiconductor substrate on which a plurality of first semiconductor chips are formed is viewed vertically from the semiconductor substrate.
- a through hole that penetrates the protective resin layer in the thickness direction may be formed in a region spanning adjacent first semiconductor chips.
- the conductive film becomes an external connection terminal, and a semiconductor device having a concave portion in a recess formed by cutting a through hole is obtained. Can be manufactured.
- the through-hole is not densely filled with the conductive film, the first semiconductor chip adjacent to the adjacent first semiconductor chip is produced by such a production method as compared with the method of production from the semiconductor substrate on which the columnar electrode is formed.
- the dicing blade used when cutting the semiconductor substrate along the boundary can reduce wear of tools such as a cutting die.
- the external connection terminal is formed on the main body portion embedded in the protective resin layer and on the surface of the main body portion, and has the bottom exposed surface and the side exposed surface. It includes a coating film that is highly recyclable!
- the coating film can maintain good solder wettability and improve the connection reliability with the mounting board. For example, the coating film is difficult to oxidize from the main body V, made of material! /, Or even! /.
- FIG. 1 is an illustrative sectional view showing a structure of a semiconductor device according to a first embodiment of the present invention.
- FIG. 2 is a schematic bottom view of the semiconductor device shown in FIG.
- FIG. 3A is a schematic bottom view for explaining the method for manufacturing the semiconductor device shown in FIGS. 1 and 2.
- FIG. 3B is a schematic bottom view for explaining another method for manufacturing the semiconductor device shown in FIGS. 1 and 2.
- FIG. 3C is an illustrative cross-sectional view for explaining a method for manufacturing a semiconductor device including an external connection terminal having a main body portion and a coating film.
- FIG. 3D is an illustrative cross-sectional view for explaining a method for manufacturing a semiconductor device including an external connection terminal having a main body portion and a coating film.
- FIG. 4 is an illustrative sectional view showing a structure of a semiconductor device according to a second embodiment of the present invention.
- 5 is a schematic bottom view of the semiconductor device shown in FIG.
- FIG. 6 is an illustrative sectional view showing a structure of a semiconductor device according to a third embodiment of the present invention.
- FIG. 7 is a schematic sectional view showing a structure of a semiconductor device according to a modification of the semiconductor device shown in FIG.
- FIG. 8 is a schematic sectional view showing the structure of a semiconductor device according to a fourth embodiment of the present invention.
- FIG. 9 is a schematic bottom view of the semiconductor device shown in FIG. 8.
- FIG. 10 is a schematic perspective view of the semiconductor device shown in FIGS. 8 and 9, showing the vicinity of the external connection terminals.
- FIG. 11 is a schematic bottom view for illustrating the method for manufacturing the semiconductor device shown in FIGS. 8 and 9.
- FIG. 12 is a schematic cross-sectional view showing the structure of a conventional semiconductor device having a chip size package structure.
- FIG. 13 is a schematic cross-sectional view showing the structure of a conventional semiconductor device having a multichip module structure.
- FIG. 1 is a schematic cross-sectional view showing the structure of a semiconductor device according to the first embodiment of the present invention
- FIG. 2 is a schematic bottom view thereof.
- the semiconductor device 1 is a so-called chip size package (CSP) and includes a semiconductor chip 2.
- CSP chip size package
- a functional element 2a is formed on one surface (functional surface 2F) of the semiconductor chip 2, a functional element 2a is formed.
- the functional element 2a may be a transistor, for example.
- An insulating film 4 covering the functional element 2a is formed on the functional surface 2F.
- the insulating film 4 is formed with an opening 4a that exposes the electrode of the functional element 2a.
- the rewiring 5 electrically connected to the electrode of the functional element 2a through the opening 4a is formed.
- a protective resin layer 12 is formed on the insulating film 4 so as to cover the rewiring 5.
- the side surface 2S of the semiconductor chip 2 and the side surface 12S of the protective resin layer 12 are substantially flush with each other, and the outer shape of the semiconductor device 1 has a substantially rectangular parallelepiped shape.
- the rewiring 5 has a plurality of external connection terminals 10 penetrating the protective resin layer 12 in the thickness direction and having metal force. Yes.
- the external connection terminals 10 are arranged at substantially equal distances from the side surface 12S that is orthogonal to these side surfaces.
- the external connection terminal 10 is formed in a quadrangular prism shape.
- the external connection terminal 10 has a side exposed surface 10S exposed from the side surface 12S of the protective resin layer 12, and a bottom exposed surface 10B where the bottom surface 12B force is also exposed.
- the side exposed surface 10S and the bottom exposed surface 10B are substantially flush with the side surface 12S and the bottom surface 12B, respectively.
- the semiconductor device 1 can be mounted on the mounting substrate 15 via the side exposed surface 10S and the bottom exposed surface 10B of the external connection terminal 10. At this time, the electrode node 15P formed on the surface of the mounting substrate 15 can be connected to the side exposed surface 10S and the bottom exposed surface 10B with the solder 16 (FIG. 1 shows the mounting substrate 15 and the electrode pad 15P). And solder 16 is indicated by a two-dot chain line.)
- the external connection terminal 10 is formed in the peripheral portion of the protective resin layer 12 (semiconductor device 1), and is not formed in the inner region. Since the external connection terminal 10 has the side exposed surface 10S on the side surface 12S of the protective resin layer 12, the connection portion between the external connection terminal 10 and the mounting board 15 can be easily and directly recognized.
- the solder 16 whose state can be easily confirmed can be formed in advance in the form of a film on the electrode pad 15P of the mounting substrate 15 as cream solder or a melted and solidified product thereof. Since voids are difficult to be introduced into the solder 16 having such a configuration, the reliability of the external connection of the semiconductor device 1 is improved.
- FIG. 3A is a schematic bottom view for explaining the method for manufacturing the semiconductor device 1.
- the semiconductor device 1 can be manufactured by a semiconductor substrate having a plurality of semiconductor chips 2 built therein.
- FIG. 3A shows a semiconductor wafer (hereinafter simply referred to as “wafer”) W as such a semiconductor substrate.
- the region extending over the adjacent semiconductor chips 2 in the wafer W is electrically connected to the functional element 2a of each semiconductor chip 2, and the protective resin layer 12 is formed in a thickness.
- a columnar electrode 17 penetrating in a direction (a direction orthogonal to the wafer W) is formed.
- the columnar electrode 17 can be formed by, for example, electroplating.
- the semiconductor device 1 can be manufactured by cutting the wafer W with a dicing blade or a cutting die along the boundary B (shown by a one-dot chain line in FIG. 3A) of the adjacent semiconductor chips 2.
- the cut columnar electrode 17 becomes the external connection terminal 10. Therefore, the side exposed surface 10S of the external connection terminal 10 is a flat surface that is flush with the side surface 12S of the protective resin layer 12 (see FIG. 2).
- each semiconductor chip 2 is formed across the boundary B in the adjacent portion of the semiconductor chip 2 as shown in FIG.
- a plurality of pairs of columnar electrodes 17A spaced apart from each other in the orthogonal direction may be provided.
- the interval between the columnar electrodes 17A constituting each pair can be made narrower than the allowance by the die cinder blade.
- the external connection terminal On the side exposed surface 10S and the bottom exposed surface 10B of the external connection terminal 10, a coating film made of a material having higher solder wettability than the external connection terminal 10 may be formed. That is, the external connection terminal may include a portion corresponding to the external connection terminal 10 forming the main body portion and a coating film formed on the surface of the main body portion.
- the main body (corresponding to the external connection terminal 10) is made of a material that easily forms an oxide film on its surface (for example, copper), and this oxide film is sufficiently formed. Even if the solder wettability is lost, the coating film can maintain good solder wettability and improve the connection reliability with the mounting substrate 15.
- FIG. 3C and FIG. 3D are schematic cross-sectional views for explaining a method of manufacturing a semiconductor device including an external connection terminal having a main body portion and a coating film.
- a wafer W on which a plurality of semiconductor chips 2 shown in FIG. 3A or FIG. 3B is formed is used. It is intended.
- the columnar electrode 17, the protective resin layer 12, and the rewiring 5 and the insulating film 4 are passed through in the thickness direction (direction perpendicular to the wafer W), and a groove 18 reaching the surface layer portion of the wafer W is formed.
- the columnar electrode 17 has an exposed surface 17S (cut surface) to the groove 18 and an exposed surface 17B from the bottom surface 12B of the protective resin layer 12.
- the wafer W-force is immersed in a plating solution.
- a nickel (Ni) layer and a gold (Au) layer are sequentially formed on the exposed surfaces 17S and 17B by electroless plating.
- a film 19B is formed.
- the wafer W is cut along the boundary B of the adjacent semiconductor chips 2 by a dicing blade thinner than the dicing blade used to form the groove 18 (see FIG. 3D).
- the dicing blade is inserted into the groove 18 so as not to contact the coating film 19B.
- the semiconductor device 1A including the external connection terminal 19 including the main body portion 19A obtained by cutting the columnar electrode 17 and the coating film 19B formed on the surface thereof is obtained.
- the surface force of the wafer W on the side opposite to the side where the grooves 18 are formed may be cut by a dicing blade.
- the coating film 19B can be collectively formed on the plurality of semiconductor chips 2 by performing electroless plating without completely cutting the wafer and W.
- the coating film 19B has a bottom exposed surface 19BB exposed from the bottom surface 12B of the protective resin layer 12, and a side exposed surface 19BS exposed from the side surface 12S of the protective resin layer 12.
- the coating film 19B has a force side exposed surface 19BS formed so as to rise slightly from the surface of the main body portion 19A, and is substantially flush with the side surface 2S of the semiconductor chip 2.
- the semiconductor device 1A can be mounted on the mounting substrate 15 by soldering via the side exposed surface 19BS and the bottom exposed surface 19BB of the external connection terminal 19. Even when the main body 19A does not have sufficient solder wettability (may not be present), the coating film 19B maintains good solder wettability and reliability of connection to the mounting board 15 Can improve In the above manufacturing method, instead of immersing Ueno and W in the plating solution to perform electroless plating, the wafer W is immersed in a solder bath (molten solder) and soldered to the exposed surfaces 17S and 17B. A coating film that also has strength may be formed. In this case, it is possible to obtain a semiconductor device including an external connection terminal in which a coating film such as a solder cover is formed on the surface of the main body portion 19A.
- a solder bath molten solder
- FIG. 4 is a schematic cross-sectional view of a semiconductor device according to the second embodiment of the present invention
- FIG. 5 is a schematic bottom view thereof.
- parts corresponding to those shown in FIGS. 1 and 2 are given the same reference numerals as those in FIGS.
- the semiconductor device 21 is provided with a heat radiation terminal 22 at the center of the semiconductor chip 2 in a plan view in which the bottom surface 12B is viewed vertically.
- the heat dissipating terminal 22 is erected from a rewiring 5A formed on the insulating film 4.
- the insulating film 4 has an opening 4b that exposes the electrode of the functional element 2a.
- the rewiring 5A is electrically connected to the electrode of the functional element 2a through the opening 4b. Therefore, the heat radiating terminal 22 is electrically connected to the functional element 2a.
- the heat dissipation terminal 22 penetrates the protective resin layer 12 in the thickness direction, and has an exposed surface 22B on the bottom surface 12B of the protective resin layer 12.
- the bottom surface 12B and the exposed surface 22B are almost flush with each other.
- the semiconductor device 21 can be mounted on the mounting substrate via the bottom exposed surface 10B, the side exposed surface 10S of the external connection terminal 10, and the exposed surface 22B of the heat dissipation terminal 22.
- the mounting board may be provided with electrode pads corresponding to the heat radiation terminals 22 in addition to electrode pads corresponding to the external connection terminals 10.
- the electrode pads formed on the surface of the mounting substrate and the side exposed surface 10S, the bottom exposed surface 10B, and the exposed surface 22B can be connected by solder.
- the exposed surface 22B is so large that the exposed surface 22B, the bottom exposed surface 10B, and the side exposed surface 10S are not short-circuited by the solder during mounting. Since the heat radiating terminal 22 is formed in the inner region of the protective resin layer 12, the joint between the exposed surface 22B and the electrode pad formed on the mounting substrate cannot be directly seen, but the exposed surface 22B By making it large, reliable joining is easily achieved.
- the semiconductor device 21 can dissipate heat generated in the semiconductor chip 2 via the heat dissipation terminal 10. Therefore, the heat dissipation of the semiconductor device 21 is high. By increasing the exposed surface 22B, the heat dissipation of the semiconductor device 21 is improved.
- the heat radiating terminal 22 may be a power supply wiring for supplying a voltage to the functional element 2a or a ground wiring for grounding the functional element 2a. In this case, the operation of the semiconductor chip 2 (functional element 2a) can be stabilized.
- the heat dissipation terminal 22 may have the same material force as that of the external connection terminal 10, for example.
- the external connection terminal 10 and the heat dissipation terminal 22 are formed together by electrolytic plating. it can.
- FIG. 6 is a schematic sectional view showing the structure of a semiconductor device according to the third embodiment of the present invention.
- the semiconductor device 31 is a multichip module that includes a first semiconductor chip 32 and a second semiconductor chip 33.
- a first functional element 32a is formed on one surface (first functional surface 32F) of the first semiconductor chip 32.
- An insulating film 4 that covers the functional element 32a is formed on the first functional surface 32F. Openings 4a and 4c are formed in the insulating film 4 to expose the electrodes of the functional element 2a.
- a rewiring 5B electrically connected to the electrode of the functional element 32a through the opening 4c is formed.
- a second functional element 33a is formed on one surface (second functional surface 33F) of the second semiconductor chip 33.
- the second semiconductor chip 33 is joined with the second functional surface 33F facing the first functional surface 32F (insulating film 4) of the first semiconductor chip 32 with a predetermined distance between the second semiconductor chip 33 and the insulating film 4. Yes.
- the electrode of the second functional element 33a is electrically connected to the rewiring 5B through the connection member 36. Thereby, the first functional element 32a and the second functional element 33a are electrically connected.
- An underfill layer 37 is filled in a gap between the insulating film 4 and the second semiconductor chip 33.
- the second semiconductor chip 33 has the first semiconductor chip 33 in a plan view perpendicular to the first functional surface 32F.
- the size of the second semiconductor chip 33 is approximately the center of the second semiconductor chip 33.
- the external connection terminals 10 are arranged so as to surround the second semiconductor chip 33.
- the second semiconductor chip 33 is sealed by the protective resin layer 12 and has an exposed surface from the protective resin layer 12.
- the semiconductor device 31 is a multichip module. However, the mounting area is reduced to the size of the first semiconductor chip 32 as viewed perpendicular to the first functional surface 32F.
- FIG. 7 is a schematic cross-sectional view showing the structure of a semiconductor device according to a modification of the semiconductor device 31.
- parts corresponding to the parts shown in FIG. 6 are denoted by the same reference numerals as in FIG.
- the semiconductor device 41 includes a second semiconductor chip 33A instead of the second semiconductor chip 33.
- the second semiconductor chip 33A has a larger thickness than the second semiconductor chip 33.
- the back surface (the surface opposite to the second functional surface 33F) of the second semiconductor chip 33A is exposed from the protective resin layer 12, and is substantially flush with the bottom surface 12B. As a result, the second semiconductor chip
- FIG. 8 is a schematic sectional view showing the structure of a semiconductor device according to the fourth embodiment of the present invention
- FIG. 9 is a schematic bottom view thereof.
- parts corresponding to those shown in FIGS. 1 and 2 are given the same reference numerals as those in FIGS.
- the semiconductor device 51 includes a film-like external connection terminal 52 instead of the columnar external connection terminal 10 of the semiconductor device 1 shown in FIG.
- FIG. 10 is a schematic perspective view of the semiconductor device 51 and shows the vicinity of the external connection terminal 52.
- a semi-cylindrical groove 53 is formed in the side surface 12S of the protective resin layer 12 in the thickness direction of the protective resin layer 12.
- the external connection terminal 52 includes a concave surface portion 54 formed along the inner surface of the groove 53 and a flat portion 55 formed in the vicinity of the groove 53 on the bottom surface 12B of the protective resin layer 12.
- the concave portion 54 and the flat portion 55 are integrally formed.
- Concave part 54 is electrically connected to rewiring 5.
- the curved surface (exposed surface) is a semicircular arc surface corresponding to the inner surface of the semi-cylindrical groove 53.
- the flat portion 55 extends from the tip of the concave surface portion 54 on the bottom surface 12B side in an inward direction toward the bottom surface 12B.
- this semiconductor device 51 can be mounted on the mounting substrate via the concave surface portion 54 and the flat portion 55 of the external connection terminal 52. At this time, the electrode pad formed on the surface of the mounting substrate and the concave surface portion 54 and the flat portion 55 can be connected by solder.
- the concave surface portion 54 has a curved surface, its surface area is larger than the side exposed surface 10S of the external connection terminal 10 that forms a flat surface. As a result, the bonding area with the mounting substrate (the wetted area of the solder) can be increased, and the bonding strength can be increased.
- FIG. 11 is a schematic bottom view for explaining the method for manufacturing the semiconductor device 51.
- the semiconductor device 51 can be manufactured from a semiconductor substrate on which a plurality of semiconductor chips 2 are formed.
- FIG. 11 shows a wafer W as such a semiconductor substrate.
- a through hole 56 is formed in a region extending across adjacent semiconductor chips 2 in the wafer W when the wafer W is viewed vertically.
- Conductive films 57 electrically connected to the functional elements 2a of the respective semiconductor chips 2 are formed on the inner surface of the through hole 56 and the bottom surface 12B in the vicinity of the through hole 56.
- the conductive film 12B is formed across the adjacent semiconductor chips 2, and extends in a direction orthogonal to the boundary (shown by a one-dot chain line in FIG. 11) B between these semiconductor chips 2.
- the conductive film 57 can be formed, for example, by electrolytic plating.
- the through hole 56 is not densely filled with the conductive film 57, and the inner region of the conductive film 57 in the through hole 56 is a cylindrical hole.
- the semiconductor device 51 can be manufactured by cutting the wafer W along a boundary B between adjacent semiconductor chips 2 with a dicing blade, a cutting die, or the like.
- the cut conductive film 57 becomes the external connection terminal 52, and the conductive film 57 formed on the inner surface of the through hole 56 becomes the concave surface portion 54.
- the wafer W on which the columnar electrodes 17 and 17A are formed is cut by such a manufacturing method (see FIGS. 3A and 3B). As compared with the above, it is possible to reduce wear of a tool such as a dicing blade or a cutting die used when cutting the wafer W along the boundary between the adjacent semiconductor chips 2.
- each of the external connection terminals 10 has an exposed surface on the force side surface 12S and the bottom surface 12B that are electrically connected to the electrode of the functional device 2a via the rewiring 5, and the functional device
- An external connection terminal that is not electrically connected to the electrode 2a may be provided.
- Such external connection terminals can also contribute to bonding to the mounting substrate.
- the heat radiating terminal 22 may not be electrically connected to the semiconductor chip 2.
- One semiconductor device may be provided with a heat dissipation terminal and a second semiconductor chip.
- the heat dissipation terminal (less than the heat dissipation terminal 22 shown in FIGS. 4 and 5) is placed in the gap between the second semiconductor chip 33 and the external connection terminal 10. Terminal) is provided.
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Abstract
Description
Claims
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US11/596,755 US20070284735A1 (en) | 2004-10-14 | 2005-10-06 | Semiconductor Device |
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JP2004300532A JP4620994B2 (ja) | 2004-10-14 | 2004-10-14 | 半導体装置 |
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US (1) | US20070284735A1 (ja) |
JP (1) | JP4620994B2 (ja) |
KR (1) | KR20070067072A (ja) |
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DE202008005708U1 (de) * | 2008-04-24 | 2008-07-10 | Vishay Semiconductor Gmbh | Oberflächenmontierbares elektronisches Bauelement |
JP6509602B2 (ja) * | 2014-04-09 | 2019-05-08 | ローム株式会社 | 半導体装置 |
JP7088409B2 (ja) * | 2019-04-03 | 2022-06-21 | 株式会社村田製作所 | モジュール、端子集合体、及びモジュールの製造方法 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001313349A (ja) * | 2000-04-28 | 2001-11-09 | Oki Electric Ind Co Ltd | 半導体装置及びその製造方法 |
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JPS5852846A (ja) * | 1981-09-25 | 1983-03-29 | Oki Electric Ind Co Ltd | 半導体装置の製造方法 |
US5922517A (en) * | 1996-06-12 | 1999-07-13 | International Business Machines Corporation | Method of preparing a substrate surface for conformal plating |
US6285085B1 (en) * | 1997-08-13 | 2001-09-04 | Citizen Watch Co., Ltd. | Semiconductor device, method of fabricating the same and structure for mounting the same |
US6228681B1 (en) * | 1999-03-10 | 2001-05-08 | Fry's Metals, Inc. | Flip chip having integral mask and underfill providing two-stage bump formation |
US6696765B2 (en) * | 2001-11-19 | 2004-02-24 | Hitachi, Ltd. | Multi-chip module |
-
2004
- 2004-10-14 JP JP2004300532A patent/JP4620994B2/ja active Active
-
2005
- 2005-10-06 CN CNB200580025765XA patent/CN100470770C/zh active Active
- 2005-10-06 KR KR1020077002527A patent/KR20070067072A/ko active IP Right Grant
- 2005-10-06 US US11/596,755 patent/US20070284735A1/en not_active Abandoned
- 2005-10-06 WO PCT/JP2005/018556 patent/WO2006041013A1/ja active Application Filing
- 2005-10-12 TW TW094135537A patent/TW200620624A/zh unknown
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001313349A (ja) * | 2000-04-28 | 2001-11-09 | Oki Electric Ind Co Ltd | 半導体装置及びその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
US20070284735A1 (en) | 2007-12-13 |
CN100470770C (zh) | 2009-03-18 |
JP2006114696A (ja) | 2006-04-27 |
TWI373122B (ja) | 2012-09-21 |
JP4620994B2 (ja) | 2011-01-26 |
KR20070067072A (ko) | 2007-06-27 |
TW200620624A (en) | 2006-06-16 |
CN1993825A (zh) | 2007-07-04 |
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