Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/67—Thin-film transistors [TFT]
  • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
  • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
  • H10D30/6748—Group IV materials, e.g. germanium or silicon carbide having a multilayer structure or superlattice structure
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
  • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/751—Insulated-gate field-effect transistors [IGFET] having composition variations in the channel regions

Definitions

• This invention relates in general to semiconductor devices and in particular to forming semiconductor devices with strained channel regions.
• Electron and hole motilities maybe enhanced with the utilization of strained (e.g. with a bi-axial tensile strain) silicon for the channel region, especially for devices built from wafers having semiconductor or insulator configurations (SOI).
• a strained silicon layer maybe formed by depositing a layer of silicon on a template layer (e.g. silicon germanium).
• a condensation process is performed on the silicon germanium template to relax the layer prior to the deposition of silicon.
• a condensation process includes the oxidization of the silicon germanium template layer. With such a process, a layer of SiO 2 is grown on top of the template layer with the germanium of the consumed portion of the template layer diffused into the remaining portion of the silicon germanium layer below to enrich the remaining portion. The oxide is subsequently etched off prior to the deposition of the strained silicon.
• germanium may not adequately diffuse to the remaining portion of the silicon germanium layer. Accordingly, there may be a relatively high concentration of germanium at the top portion of the remaining layer as opposed to the germanium concentration of the lower portion of the silicon germanium layer. These differences in germanium concentration in the template layer may cause dislocations which could lead to a dysfunctional semiconductor device formed in the area of the dislocations.
• Figure 1 is a partial cross sectional view of one embodiment of a wafer during a stage in the manufacture of a semiconductor device according to the present invention.
• Figure 2 is a partial cross sectional view of one embodiment of a wafer during another stage in the manufacture of a semiconductor device according to the present invention.
• Figure 3 is a partial cross sectional view of one embodiment of a wafer during another stage in the manufacture of a semiconductor device according to the present invention.
• Figure 4 is a partial cross sectional view of one embodiment of a wafer during another stage in the manufacture of a semiconductor device according to the present invention.
• providing a layer of template layer material with a graded concentration of germanium may provide for a more uniform grade of germanium after a condensation process has been performed on the layer.
• Figure 1 is a partial cross sectional view of a wafer 101 during a stage in the manufacture of a semiconductor device.
• wafer 101 includes a semiconductor substrate 103 with an insulator layer 105 (e.g. oxide) located on substrate 103.
• Silicon layer 106 e.g. 100 A
• layers 106, layer 105, and substrate 103 are formed by a SEVIOX process or by bonding one silicon wafer on an oxide layer of another wafer.
• wafer 101 has a semiconductor on insulator (SOI) configuration. In other embodiments, wafer 101 may have other types of SOI configurations (e.g. silicon on sapphire or quartz).
• a silicon germanium layer 107 is formed on silicon layer 106.
• the germanium concentration of layer 107 is graded from a high concentration at the lower part of layer 107 to a lower concentration at the top portion of layer 107.
• layer 107 is epitaxially grown by a chemical vapor deposition (CVD) process.
• CVD chemical vapor deposition
• a germanium containing gas e.g. germane or germanium tetrachloride
• a silicon containing gas e.g. silane or di-chloro silane
• the concentration of germanium is 50% at the bottom of layer 107 and is gradually reduced to 10% at the top of layer 107.
• the concentration of germanium at the bottom of layer 107 may range from 100% germanium to 10% germanium.
• the concentration germanium at the top portion ot layer i ⁇ v may range rrom ⁇ -z ⁇ %.
• layer 107 may have different germanium concentrations at both the top and bottom portions.
• layer 107 has a thickness of 700A with a grade of germanium from 30% at the bottom to 10% at the top. In other embodiments, layer 107 may be of other thicknesses. In some embodiments, the thickness of layer 107 depends upon the concentration of germanium at the bottom of layer 107 and the concentration of germanium at the top of layer 107, as well as the ability to change the germanium concentration during the CVD process.
• the germanium concentration of layer 107 is characterized as back graded in that upper portions have a lower germanium concentration that lower portions.
• layer 107 may include portions where the germanium concentration is not back graded.
• layer 107 may be formed on insulator layer 105 where initially, the germanium concentration is zero but increases rapidly (e.g. 30 %). The germanium concentrations of this upper portion would then be back graded to a lower concentration (e.g. 10 % ) at a top portion.
• the ratio of the germanium containing gas to silicon containing gas in a CVD process may be adjusted linearly or in a step wise fashion. In some embodiments, the number of steps of a step wise process is dependent upon the desired change in germanium concentration.
• Figure 2 shows a partial cross sectional view of wafer 101 after a condensation process has been performed on wafer 101.
• the top portion of layer 107 (see Figure 1) is consumed to grow a silicon oxide layer 209 on the remaining portion of the silicon germanium layer 207.
• germanium from layer 107 diffuses into layer 106 (such as layer 106 effectively mergers with the remaining portion of layer 107.
• layer 207 includes both layer 106 and the remaining portion of layer 107.
• other types of condensation operations may be utilized that increase the germanium concentration in a remaining portion of the layer.
• germanium trom the consumed top portion of layer 107 diffuses to the remaining portion (layer 207).
• the concentration of germanium in layer 207 is relatively uniform after the condensation process. As compared with some prior art processes, there is a relative lack of germanium build up at the top portion of layer 207. In one embodiment, the concentration of germanium in layer 207 is about 35% + 2 % across the thickness of layer 207. However, the resultant germanium concentrations of layer 207 may be of other values in other embodiments and/or of other gradients.
• the condensation process is performed at 1050 C for 30 minutes with 6% HCL gas (e.g. at a 6% concentration). However, other condensation processes at other temperatures (up to 1200 C and above), for other durations, and/or in the presence of other gases.
• layer 207 has a thickness of 40nm.
• Another advantage of using a silicon germanium of different concentrations is that it may allow for a condensation process at lower temperatures (e.g. 1050 C as opposed to 1200 C processes in some examples) and/or shorter condensation times.
• having a higher concentration of germanium at the bottom portion of layer 107 provides a second driving force for diffusion, where geranium atoms diffuse upward in layer 107 due to the lower concentration of germanium at those higher portions.
• This second driving force for diffusion is in addition to the driving force of diffusion of germanium from the germanium in the top portion of layer 107 from being consumed due to condensation.
• One advantage of performing a condensation process at lower temperatures is that it may avoid melting which may occur in layer 207. With some embodiments, the higher concentration of germanium reduces the melting point of silicon germanium. Thus, the ability to perform condensation processes at lower temperatures may be beneficial.
• a silicon cap layer (not shown) may be formed on silicon germanium layer 107 prior to the condensation of layer 107.
• Figure 3 is a partial cross section of wafer 101 after oxide layer 209 has been removed (e.g. by a HF wet etch) and a layer 305 of strained silicon has been epitaxially deposited on silicon germanium layer 207.
• Layer 207 serves as a template layer for depositing layer 305 where the lattice of layer 305 generally has the same lattice constant as that of layer 207.
• layer 305 has a thickness ot ZUU A, but may nave other thicknesses in other embodiments.
• layer 207 is relaxed after the condensation process. Accordingly, the lattice of silicon layer 305 will have a tensile strain in order to match the lattice constant of layer 207. In other embodiments, layer 207 may have another strain characteristic (e.g. partially relaxed). The strain characteristic of layer 207 is more relaxed than the strain concentration of layer 107.
• layer 305 may be performed on layer 305 including processes set forth in the application entitled "Template Layer Formation,” having a common assignee, having a docket number SC12851ZP POl, and being filed concurrently, all of which is incorporated by reference in its entirety.
• further processes include a post bake with a chorine bearing gas.
• FIG. 4 shows a partial cross sectional view of wafer 101 after the formation of transistor 401.
• Transistor 401 includes a gate 403 formed on gate oxide 407. Gate oxide 407 is formed on strain silicon layer 305.
• Transistor 307 also includes a spacer 405 formed over layer 305.
• transistor 401 includes source/drain regions 411 and 409 formed e.g. by implanting of dopants into layer 305 and 207 at select regions.
• Transistor 401 includes a channel region 413 formed (in the embodiment shown) in strained silicon layer 305.
• the template layer material may include other components such as carbon as in silicon germanium carbon, silicon tin, and germanium carbon.
• Wafer 101 may include other transistors (not shown).
• layer 107 may be selectively formed on some areas of wafer 101. In other embodiments, layer 107 is formed on all of wafer 101.
• a condensation process may be selectively performed on all of layer 107. hi other embodiments, the condensation process is performed on select areas of the wafer where other areas are masked. For example, it may be desirable for layer 305 to have different strain characteristics in the N-channel regions and P-channel regions.
• a method of forming a semiconductor structure includes providing a wafer having a semiconductor on insulator (SOI) configuration.
• the wafer includes a first semiconductor layer over an insulator.
• the tirst semiconductor layer is made of at least two components.
• the first semiconductor layer includes a first portion overlying a second portion of the first semiconductor layer.
• the first portion includes a first concentration of a first component of the at least two components and wherein the second portion includes a second concentration of the first component of the at least two components.
• the first concentration is less than the second concentration.
• the method further includes performing a condensation process on the first semiconductor layer to consume a portion of the first semiconductor layer and to form a material including a second component of the at least two components over a remaining portion of the first semiconductor layer.
• the method also includes removing the material and forming a second semiconductor layer including the second component over the remaining portion after the removing the material.
• a method of forming a semiconductor structure includes providing a wafer.
• the wafer includes a first semiconductor layer.
• the first semiconductor layer includes silicon and germanium.
• the first semiconductor layer includes a first portion having a first concentration of germanium and a second portion having a second concentration of germanium.
• the first portion overlies the second portion.
• the first concentration is less than the second concentration.
• the method also includes performing a condensation process on the first semiconductor layer to consume a portion of the first semiconductor layer and to form a material including silicon overlying a remaining portion of the first semiconductor layer.
• the method still further includes removing the material including silicon and forming a second semiconductor layer including silicon over the remaining portion after the removing the material including silicon.
• a method of forming a semiconductor device includes providing a wafer having a semiconductor on insulator (SOI) configuration.
• the wafer includes a first semiconductor layer over an insulator.
• the first semiconductor layer includes germanium and silicon.
• the first semiconductor layer includes a first portion of the first semiconductor layer overlying a second portion of the first semiconductor layer.
• the first portion includes a first concentration of germanium and wherein the second portion includes a second concentration of germanium. The first concentration is less than the second concentration.
• the method also includes performing an oxidation process on the first semiconductor layer to consume a portion of the first semiconductor layer and to form an oxi ⁇ e on a remaining poraon or me ⁇ rst semiconductor layer, i ne metno ⁇ sun rurtner includes removing the oxide and forming a second semiconductor layer including silicon over the remaining portion using the remaining portion as a template layer after the removing the oxide.
• the method also includes forming a transistor including a channel region. At least a portion of the channel region is located in the second semiconductor layer.

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• Engineering & Computer Science (AREA)
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• Condensed Matter Physics & Semiconductors (AREA)
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• Manufacturing & Machinery (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
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• Recrystallisation Techniques (AREA)
• Thin Film Transistor (AREA)

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• 2004
  • 2004-08-17 US US10/919,952 patent/US7241647B2/en not_active Expired - Fee Related
• 2005
  • 2005-08-08 KR KR1020077003816A patent/KR20070047307A/ko not_active Withdrawn
  • 2005-08-08 JP JP2007527945A patent/JP2008510320A/ja active Pending
  • 2005-08-08 CN CNB2005800279288A patent/CN100472761C/zh not_active Expired - Fee Related
  • 2005-08-08 WO PCT/US2005/029113 patent/WO2006023492A1/en not_active Ceased
  • 2005-08-12 TW TW094127426A patent/TWI371087B/zh not_active IP Right Cessation

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