Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B82—NANOTECHNOLOGY
  • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
  • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B82—NANOTECHNOLOGY
  • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
  • B82Y40/00—Manufacture or treatment of nanostructures
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D48/00—Individual devices not covered by groups H10D1/00 - H10D44/00
  • H10D48/30—Devices controlled by electric currents or voltages
  • H10D48/32—Devices controlled by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
  • H10D48/36—Unipolar devices
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/117—Shapes of semiconductor bodies
  • H10D62/118—Nanostructure semiconductor bodies
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/117—Shapes of semiconductor bodies
  • H10D62/118—Nanostructure semiconductor bodies
  • H10D62/119—Nanowire, nanosheet or nanotube semiconductor bodies
  • H10D62/121—Nanowire, nanosheet or nanotube semiconductor bodies oriented parallel to substrates
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
  • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
  • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10S438/00—Semiconductor device manufacturing: process
  • Y10S438/962—Quantum dots and lines
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
  • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10S977/00—Nanotechnology
  • Y10S977/70—Nanostructure
  • Y10S977/762—Nanowire or quantum wire, i.e. axially elongated structure having two dimensions of 100 nm or less
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
  • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10S977/00—Nanotechnology
  • Y10S977/70—Nanostructure
  • Y10S977/813—Of specified inorganic semiconductor composition, e.g. periodic table group IV-VI compositions
  • Y10S977/815—Group III-V based compounds, e.g. AlaGabIncNxPyAsz
  • Y10S977/818—III-P based compounds, e.g. AlxGayIn2P
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
  • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10S977/00—Nanotechnology
  • Y10S977/902—Specified use of nanostructure
  • Y10S977/932—Specified use of nanostructure for electronic or optoelectronic application
  • Y10S977/936—Specified use of nanostructure for electronic or optoelectronic application in a transistor or 3-terminal device
  • Y10S977/938—Field effect transistors, FETS, with nanowire- or nanotube-channel region

Definitions

• the invention relates to a nanoscale FET, and in particular to a FET using nanowire and nanotube technology.
• MOS metal oxide semiconductor
• MIS metal insulator semiconductor
• US2003/0148562 proposes a field effect transistor with a carbon nanowire forming a source, channel and drain region and a surrounding nanotube gate.
• a boron nitride nanotube insulator is proposed as an insulator between the nanowire channel and the nanotube gate.
• US2003/0178617 presents self-aligned carbon nanowire structures, mostly using vertical nanowires but including in one embodiment horizontal nanowires formed with chemical groups, on the ends and then aligned by providing complimentary chemical groups where the nanowires are to be assembled. For example, complementary strands of DNA are said to make suitable complementary groups.
• US 2004/0036128 describes another carbon nano-structure, in this case using carbon nanotubes. In one embodiment, the nanotubes are grown horizontally from drain catalyst contacts.
• nanowire superlattices i.e. nanowires containing more than one material
• the details of growing nanowire superlattices are contained in Gudiksen et al, "Growth of nanowire superlattice structures for nanoscale photonics and electronics", Nature, volume 415, pages 617 to 620 (2002).
• VLS vapour-liquid-solid
• the low diameter clusters are created by laser ablation of a metal target which generates a suspension of metal clusters.
• the metal atoms may be for example of gold.
• a transistor device comprising: a continuous linear nanostructure having a doped source region, a doped drain region and a channel region between the source and drain regions; and an insulated gate adjacent to the channel region for controlling conduction in the channel region between the source and drain regions.
• the source and drain regions are nanowires and the channel region is a nanotube extending between the source and drain regions.
• nanowire is reserved for solid wire nanostructures, i.e. is not used for hollow nanostructures, and the term nanotube is used for nanostructures with a hollow interior.
• nanotubes Precisely controlled doping of nanotubes is technically difficult and accordingly it would be very difficult to simply use a nanotube extending from a source region through a channel region to a drain region, since it would be necessary to dope the source and drain regions which in that instance would be in the form of a nanotube.
• a nanotube is used for the channel and a nanowire for the source and drain regions it is possible to dope the source and drain regions and still get advantages from a nanotube channel.
• the nanotube channel has thin walls and accordingly will, in use, be fully inverted and this gives rise to good transistor properties. Further, the fact that the channel is fully inverted can reduce the importance of misalignment and this can improve the manufacturability of the device.
• the nanostructures are formed of a semiconductor material instead of carbon. Doping of semiconductors is more straightforward.
• the channel nanotube region is undoped to enhance mobility of the device.
• the thickness of the nanowire source and drain regions can be made larger in regions spaced away from the nanotube channel than adjacent to the nanotube channel to facilitate contacting the device, both improving manufacturability and improving the contact resistance by having a large contact area.
• the transistor is formed on a substrate having a first major surface; a plurality of said continuous nanostructures extend across the first major surface substantially parallel to one another in a longitudinal direction; a thin gate insulating layer extends laterally over the channel regions of the plurality of nanostructures; and a conductive gate material extends laterally over the thin gate insulating layer.
• substantially parallel is not intended to imply that the nanostructures need to be exactly straight or all precisely aligned, and some variation in direction either within a single nanostructure or between different nanostructures is acceptable.
• the channel region of the nanotube may be in the range 5 to 100 nm long.
• the wall thickness of the channel region of the nanotube may be in the range 2 to 20 nm.
• the invention in another aspect, relates to a method of manufacture of a transistor, including: commencing growth of a nanostructure by growing a doped region in the form of a nanowire to form the source or drain; continuing the growth of the nanostructure under changed growth conditions to grow an undoped channel region in the form of a nanotube; and continuing the growth of the nanostructure by growing a doped region in the form of a nanowire to form the other of the source or drain; and forming an insulated gate adjacent to the channel region.
• the transistion between the nanotube and nanowire regions may conveniently be made by varying the growth temperature. Accordingly, source and drain regions may be grown at a temperature below a predetermined transition temperature and the channel region at a temperature above the predetermined transition temperature. In the case of an InP nanotube the transition temperature may be 500 0 C.
• the invention may include growing channel region of the nanostructure to have a first width and growing the source and drain regions to have a maximum width at least three times the first width.
• the method includes: providing a substrate; providing a plurality of catalytic starting points for growing nanostructures; commencing growth of a nanostructure by growing doped regions in the form of a nanowire starting from the catalytic starting points, continuing the growth of the nanostructure under changed growth conditions to grow a channel region in the form of a nanotube; and continuing the growth of the nanostructure by growing a doped region in the form of a nanowire to form the other of the source or drain; forming a dielectric layer as a gate insulator over the channel region of the nanostructures; and forming a conductive gate material over the dielectric layer.
• the channel region is preferably grown undoped.
• a particularly convenient method of providing a plurality of catalytic starting points includes: depositing a plurality of thin lines of catalyst metal extending longitudinally across the substrate; depositing an insulator over the thin lines of catalyst metal; etching the insulator and catalyst metal in a window to exposing the ends of the thin lines of catalyst metal at the edge of the window as the catalytic starting points.
• Figure 1 illustrates a side view of first stage in the manufacture of a transistor according to an embodiment of the invention
• Figure 2 is a top view of the first stage of Figure 1 ;
• Figure 3 is a top view of a second stage in the manufacture of a transistor according to the embodiment.
• Figure 4 is a top view of a third stage in the growth of a transistor according to the embodiment.
• Figure 5 is a section view of the nanostructure used in the invention.
• a substrate 2 is provided having a first major surface 4, shown on top in Figure 1.
• a silicon substrate is widely available and convenient.
• a thin gold layer is deposited on the substrate, and patterned to form a plurality of thin gold lines 6 running in parallel on the first major surface 4.
• An oxide layer 8 is deposited over the whole surface.
• a window 10 is then patterned and etched through both the oxide layer 8 and the gold lines 6 to expose the substrate 2 in the window.
• the window 10 is conveniently square or rectangular having opposed edges 12 running perpendicular to the gold lines 6.
• the ends 14 of the gold lines at the opposed edges form catalytic starting points for the growth of the nanostructures. Growth of nanostructures 18 then commences. In the specific embodiment described, InP nanostructures 18 are grown though the skilled person will be able to apply the technique to other materials as required.
• the properties of nanostructures as grown depend on the growth conditions and in particular the temperature.
• the initial growth is carried out using growth conditions to grow doped nanowire regions 20, without a hollow interior, of InP, and a diameter of order 20nm.
• such nanowire growth can be carried out at a temperature below 500 0 C.
• the growth conditions can be varied to provide a tapering region 22, either over the whole of the doped nanowire regions or alternatively only after an initial section of constant width. This can provide a wider nanowire in the regions to be contacted by the source and drain contacts than in the region adjacent to the channel.
• the dopant is removed and the temperature raised above 500°C, so that undoped nanotubes are grown to form a channel region 24.
• the length of the channel region may conveniently be of order 5 to 100nm, and the width of the nanotubes of order 20 to 100nm.
• the wall thickness may be 2 to 20nm
• the growth conditions are then changed again and growth continued to form doped nanowire regions 26.
• part of the region may be a tapering region 22.
• the second doped nanowire regions 26 can be formed using the same growth conditions as the first doped nanowire regions 20.
• the changes in the growth conditions can be sufficiently abrupt to create a very abrupt boundary between the channel region 24 and surrounding doped regions 20,26, and the doping in the source and drain can also be readily controlled.
• a VLS method may be used in which the substrate is placed on a temperature controlled alumina block and the substrate temperature stabilised. Then, a beam of an ArF laser is focussed on an InP target to vaporise InP which grows on the gold catalyst.
• the transition temperature of the transition between nanowire and nanotube growth is 500 0 C for undoped InP but varies a little for doped InP.
• a growth temperature of 485°C or less grows nanowires and a temperature of above 53O 0 C grows tubes.
• a growth temperature of 480 0 C grows nanotubes.
• a temperature of less than 480 0 C grows a solid nanowire, and a temperature of greater than 515 0 C grows nanotubes.
• nanotubes with a wall thickness of 2nm and a diameter or 27 nm were grown. The wall thickness of the nanotubes can be varied by varying the growth temperature above the transition temperature.
• a higher temperature is used to grow thinner walls.
• variation of the substrate temperature from 480 0 C to 550 0 C resulted in the wall thickness changing from about 14nm to 9nm respectively.
• nanostructure growth will in fact commence from both opposed edges 12 of the window 10, although this is largely irrelevant in view of the symmetrical nature of the nanostructures.
• a thin dielectric layer 30 is laid over the channel regions 24 of the nanostructures 18.
• this is a thin layer of silicon dioxide.
• a gate material 32 is then deposited over the surface.
• the gate material is of metal though polysilicon may also be used.
• Gate 32 patterning then follows. Contacts, including source contact 34 and drain contact 36, are then made to the doped regions.
• Figure 5 is an illustrative section view of the nanostructure formed showing the central nanotube region 24 with thin walls and the end source and drain regions 20,26 which are filled.
• the patterning steps may use electron beam lithography, though deep ultraviolet (DUV) or especially extreme ultraviolet (EUV) lithography may also be used.
• DUV deep ultraviolet
• EUV extreme ultraviolet
• the advantages of the device architecture include a device architecture with many degrees of freedom that can be implemented in a variety of materials, with different source drain doping and a variety of dimensions to enable the devices to be tailored to various requirements.
• the whole nanostructure can be grown in a single process.
• the very narrow channel region can be sufficiently small so that quantum effects increase the mobility.
• the channel can be fully inverted, which can avoid problems caused by gate misalignment thereby making the device more manufactureable.
• Both NMOS and PMOS devices can be manufactured in high mobility materials using the invention. Further, the dopant activation energies and transitions can be tuned to obtain a single atom abruptness from doped regions 20, 26 to the undoped channel region 24.
• the gate can be deposited all around the channel regions 24 leading to improved performance.

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• Engineering & Computer Science (AREA)
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• General Physics & Mathematics (AREA)
• Manufacturing & Machinery (AREA)
• Thin Film Transistor (AREA)
• Insulated Gate Type Field-Effect Transistor (AREA)
• Element Separation (AREA)

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• 2004
  • 2004-07-16 GB GBGB0415891.1A patent/GB0415891D0/en not_active Ceased
• 2005
  • 2005-07-12 CN CNB2005800239721A patent/CN100521237C/zh not_active Expired - Fee Related
  • 2005-07-12 AT AT05759916T patent/ATE524831T1/de not_active IP Right Cessation
  • 2005-07-12 US US11/632,738 patent/US7838368B2/en active Active
  • 2005-07-12 EP EP05759916A patent/EP1771888B1/en not_active Expired - Lifetime
  • 2005-07-12 JP JP2007520958A patent/JP2008507127A/ja not_active Withdrawn
  • 2005-07-12 WO PCT/IB2005/052313 patent/WO2006008703A2/en not_active Ceased

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