Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F30/00—Computer-aided design [CAD]
  • G06F30/30—Circuit design
  • G06F30/36—Circuit design at the analogue level
  • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F30/00—Computer-aided design [CAD]
  • G06F30/30—Circuit design
  • G06F30/39—Circuit design at the physical level

Definitions

• the present invention relates to the automated design, layout and verification of integrated circuits and, more particularly, to the co-simulation and co-verification of both the optical and electrical circuit 1 arrangements present in a silicon-based opto-electronic circuits.
• E-CAD computer-aided design
• IC integrated circuit
• E-CAD electronic CAD
• the E-CAD tools support digital, analog or mixed signal integrated electronic circuits.
• IC designers use libraries of circuit, gate and/or logic elements that are available through the well-known E-CAD software tools, or develop "custom" tools in-house to meet specific needs.
• the power of the standardized E-CAD tools has significantly fueled the growth and maturity of the IC industry.
• Integrated circuit designs may employ custom, semi-custom, or a combination of custom and semi-custom design methodologies.
• Customer refers to the creation of a new physical layout for each design.
• Semi-custom refers to the use of predefined circuit elements, such as “gate array” and “standard cell” elements.
• Gate arrays employ a set of pre-defined functions fabricated on a semiconductor wafer that may be later interconnected to implement a design.
• Standard cell technologies provide a library of low-level circuit functions each having a predefined physical layout.
• the predefined physical layout typically have a common dimension such as width or height such that they may be placed in rows and blocks, the order determined by functions to be implemented and routing of interconnect between cells or groups of cells.
• a designer may partition a design into various functional blocks and then design circuitry for each functional block or re-use a design for a functional block if a previous design meets size, power and performance criteria.
• Circuit design most frequently employs a hardware descriptive language (HDL) that specifies circuit elements and the connection between elements.
• HDL hardware descriptive language
• Verilog® is a commonly used HDL and is the topic of IEEE Std 1364. Verilog is a registered - trademark of Cadence Design Systems, headquartered in San Jose, California. Verilog may be used to specify the initial design, to provide input to simulation and synthesis tools, and to check post-layout operation.
• a version of HDL suitable for use with analog circuits (A-HDL), or for Very high speed integrated circuit HDL (VHDL) - including VHDL-AMS for analog/mixed signal applications, are also known in the art.
• the pre-defined set of cells of a standard cell library may not provide a desired function, or may not provide the speed, size or power consumption desired.
• new cells may be created, or a custom block of logic incorporating the desired function and capabilities may be designed.
• the design of the custom block of logic may employ "SPICE" (Special Programs for Interactive Circuit Elements) to specify and simulate the design.
• SPICE Programs for Interactive Circuit Elements
• Some product versions of SPICE support both logical and timing simulation.
• SPICE simulation is extremely slow when compared to simulation employing an HDL netlist model. When designs include both standard cell and custom logic sections, a problem arises when attempting to simulate the entire design.
• the custom logic may exist simply as a "black box” wherein operation of standard cell and custom logic are separately simulated; simulation comprising both sections is not performed.
• a behavioral model such as may be written in the C programming language, may be employed for function simulation, but such models do not allow for timing analysis.
• the optics industry is in a similar state today as the electronic IC industry was in the 1960's. As such, today's optics industry lacks a common technology platform to integrate different components (building blocks) to make a subsystem. As a result, the current optical industry at large has a highly "un-integrated” approach for designing, simulating and verifying the mostly discrete optical components and optical systems.
• the few existing design, simulation and verification tools for optical elements tend to be overly specific to a particular type of optical device, or a system of optical components. Indeed, these tools have generally been developed for III-V based optical devices, not the silicon components used in the inventive integrated arrangement.
• E-CAD tools used for the design and development of traditional electronic integrated circuits, utilize various types of parameters that essentially characterize and model the electronic integrated circuits. These parameters can be the signal inputs, outputs, clock signal, time delays, load, voltages, and so on. The characterization of the electronic circuit elements enables the designers to design, simulate and verify the circuits prior to mask and fabrication. These parameters can be in analog or digital format, and are readily available within various E-CAD software libraries.
• Optical modeling has heretofore been limited to use with traditional III-V-based optical devices.
• optical i.e., passive optical devices
• electronic and opto-electronic i.e., active optical devices
• E-CAD electronic computer-aided design
• OE-CAD opto-electronic CAD
• conventional simulation tools associated with the design and fabrication of digital electronic devices and "mixed'Vanalog electronic device are re-characterized for use with silicon-based optical devices and opto-electronic devices (both passive and active devices).
• the methodology allows for the separate types of elements (i.e., digital IC elements, analog/mixed IC elements and opto-electronic elements) to be individually defined and simulated. Thereafter, a "co-simulation" process is performed that uses as inputs the results from the three separate simulation processes to assess the "logic" results of the complete arrangement. The three separate simulation results are then used as inputs to three separate physical layout routines to be verified.
• the three separate layouts are used as inputs to a "co-verification” process to review the actual layout of the complete arrangement.
• the co-simulation results are checked against the co-verification results. If these results are in agreement, the circuit is ready for "tape out” (the process used to define the individual fabrication steps for the final circuit arrangement). Otherwise, problem(s) is/are identified with one or more of the steps in the process, adjustments are made and the co-simulation and co- verification processes are performed for a second time. Again, if the results are not satisfactory, the process is adjusted and re-run until a sufficient agreement in results is achieved.
• a recursive digital integrated circuit logic design is developed using "register transfer level” (RTL) circuits, which are recursively synthesized, simulated and verified until the final design meets the desired objectives.
• RTL register transfer level
• a conventional analog/mixed circuit design tool is used to specify in schematic form, simulate and verify the analog/mixed electronic integrated circuits.
• the opto-electronic components are simulated using, for example, hardware description language (HDL), particularly analog HDL (A-HDL). In this case, an optical simulation is performed to verify the performance of the optical components in the opto-electronic arrangement, with a conventional device simulation used to verify the performance of the associated electrical devices.
• HDL hardware description language
• A-HDL analog HDL
• FIG. 1 illustrates, in block diagram form, an exemplary design architecture that may be used to provide the desired co-simulation and co- verification of the three types of elements formed in the silicon-based monolithic circuit structure in accordance with the present invention
• FIG. 2 illustrates an exemplary optical element that can be developed using a layout tool commonly employed for the layout of electronic elements
• FIG. 3 contains a simplified block diagram of an exemplary opto-electronic transmitter channel that may be analyzed to form the integrated design process in accordance with the present invention
• FIG. 4 is a flowchart of the process that may be used in conjunction the transmitter channel of FIG. 3 to develop the integrated, monolithic circuit design.
• the present invention can be viewed as performing separate top-level behavioral logic designs for the three different types of elements included within the final, silicon-based monolithic structure.
• the three different types of elements can be defined as: (1) digital electronic integrated circuit elements; (2) analog/mixed signal electronic integrated circuit elements; and (3) opto ⁇ electronic elements (including passive and active optical elements).
• the annotated results (complete with definitions of parasitic capacitances and resistances, for example) is then re- simulated and compared with the prior simulation, with alterations made in the logic design and/or the physical layout until the desired operating parameters are obtained.
• desired results are generated, conventional wafer-level fabrication operations are then considered to provide a final product ("tape out").
• a significant aspect of the system of the present invention is the need to develop a library of "schematics" of exemplary silicon-based optical devices to use during the logic design and physical layout phase.
• Typical optical devices include various passive elements (waveguides, prisms, mirrors, gratings, etc.) as well as active elements (MZIs, optical detectors, ring resonators, etc.).
• MZIs active elements
• optical detectors optical detectors
• ring resonators etc.
• the use of silicon-based devices in today's SOI-based monolithic structures allows for existing schematic capture tools to be employed for this characterization.
• a particular concern for the optical layout is the connectivity between components, which takes the form of optical waveguides.
• FIG. 1 contains, in simplified block diagram form, an exemplary architecture 10 for implementing the integrated approach for forming a monolithic, silicon-based opto ⁇ electronic circuit in accordance with the present invention.
• a set of three separate modules are initially used to define and simulate the three types of elements to be included in the monolithic arrangement: (1) digital electronic elements, defined and simulated in a first module 12; (2) analog/mixed signal electronic circuit elements, defined and simulated in a second module 14; and (3) opto-electronic circuit elements, defined and simulated in a third module 16.
• first module 12 performs behavioral modeling of the digital integrated circuits using, for example, HDL languages (such as Verilog and/or VHDL).
• the output from first module 12 is a synthesized HDL netlist calling for pre- constructured and pre-characterized standard cells that are utilized to define the desired digital circuitry.
• Second module 14, associated with the design and simulation of the analog/mixed signal elements may use a schematic capture tool (such as, for example, Cadence Composer) to develop the desired model, since as is known in the art, the definition and design of analog/mixed circuit cannot always be performed by using standard cells. Subsequently, the results of the analog/mixed signal logic design is then converted to an HDL netlist, similar to the output from first module 12.
• a schematic capture tool such as, for example, Cadence Composer
• passive and active optical elements there are various parameters that are analog in nature, such as optical loss, optical gain, changes in effective refractive indices, etc.
• the passive and active optical elements can thus be modeled using their optical parameters, just as the electronic components are modeled.
• Optical "standard cells”, corresponding to a schematic optical library, can thus be formed and used within third module 16 to define the required active and passive optical elements. Again a netlist (in terms of either a schematic or a set of code) is generated as an output.
• the netlist outputs from modules 12, 14 and 16 are applied as inputs to a co-simulation arrangement 18.
• a co-simulation arrangement 18 it has been found that the mere combination of the netlist outputs will lead to an unsatisfactory result in terms of the circuit design and layout. Indeed, the various electrical and optical parameters of the digital, analog/mixed signal and opto-electronic elements interact within one another and modify the results of the simulation. Thus, a "co-simulation" is performed simultaneously, where the three separate types of elements are simulated in concert. The ability to perform a co-simulation process is considered to be a significant aspect of the present invention, in terms of assessing the operational abilities of the monolithic arrangement.
• the netlist outputs from modules 12, 14 and 16 are also provided as separate inputs to arrangements for performing the physical layouts of each of the different types of elements.
• the netlist output from digital simulation module 12 is applied as an input to a "place and route" layout element 20, layout element 20 being well-known in the art.
• a full custom layout element 22 is used to derive the physical layout of the analog/mixed signal arrangement, based on the netlist output from analog simulation module 14.
• An optical layout element 24 performs the optical layout process, and the three "layout" outputs are then supplied as inputs, in accordance with the present invention, to a co-verification element 26.
• FIG. 2 contains an example of the application of this process to a conventional Mach-Zehnder interferometer (MZI) structure.
• MZI Mach-Zehnder interferometer
• the light beam then follows path B and impinges a focusing mirror 32 that re-directs the light beam along path C and into an input port of an MZI 34.
• the output beam from MZI 34 follows along a path D, where it then impinges an output mirror 36 so as to be focused into an optical path E.
• the signal is then re-directed by a turning mirror 38 into an output signal path F.
• the connectivity of the various optical paths A-F can be likened to the metal connectivity associated with the layout of convention integrated circuits. By using this analogy, therefore, one is able to define an optical element that can be recognized by existing verification toolsets, as discussed above.
• a co-verification process is used that takes into account the various parameters associated with the layout of both optical and electronic elements.
• the results of these processes are compared. If the results are in reasonable agreement, it is presumed that the complete design will function as desired, and the set of data created from the process can then be used in a conventional "tape out" to define the specific fabrication steps.
• one or more feedback signals are directed back to specific modules/elements that need to be modified to bring closure to the process. For example, the "layout" of a specific optical element may need to be modified to bring the co- verification process into agreement with the co-simulation process. Indeed, various different elements may need some sort of adjustment.
• FIGs. 3 and 4 illustrate an exemplary application of the inventive co- simulation/co-verification design process for a transmitter channel including each type of element as described above.
• FIG. 3 illustrates a high-level block diagram of the exemplary transmitter channel elements
• FIG. 4 contains a flowchart for an exemplary process that may be used to implement the integrated design methodology of the present invention.
• an exemplary transmitter channel 100 is illustrated as comprising an encoder 110 that receives the input digital data signal that is desired to be transmitted.
• Encoder 110 functions to translate the digital input signal into a particular coded form (such as NRZ) suitable for use in the remainder of the transmitter channel.
• the output from encoder 110 is subsequently applied as an input to a serializer 120, followed by a driver 130.
• Serializer 120 and driver 130 are typically implemented as a combination of analog and digital ("mixed signal") circuitry.
• the output from driver circuit 120 - the analog encoded information signal - is subsequently applied as an input to an electro-optic modulator 140.
• a separate continuous wave (CW) optical signal is applied as a second input to modulator 140.
• the electrical input signal is used to modulate the CW optical signal, providing as an output an optical information signal.
• FIG. 4 contains a flowchart illustrating, at a high level, the methodology employed to generate the fabrication process for the integrated transmitter channel 100 as shown in FIG. 3.
• the process begins at step 200, as shown, by defining the separate "blocks" in the high-level circuit arrangement that may be categorized as "digital”, “analog/mixed signal” and "opto-electronic".
• encoder 110 is defined as a typical "digital" electronic integrated circuit that may synthesized using standard cells and subjected to a conventional "place and route” layout process.
• Serializer 120 and driver 130 are defined as typical analog circuitry, including a digital- to-analog converter (thus “mixed signal") which can be synthesized using the A-HDL and/or SPICE processes, as discussed above.
• Electro-optic modulator 140 is defined as a typical opto-electronic element, utilizing both electrical and optical inputs to fo ⁇ n an optical output signal.
• each type of element is separately subjected to a logic design process suited for the particular type of element (step 210). That is, an RTL and synthesis process may be used for digital encoder 110, a SPICE simulation for serializer 120 and driver 130, and a number of optical "standard cells” can be defined and used in conjunction with electronic "standard cells” and HDL definitions to synthesize the modulation functionality of electro-optic modulator 140.
• the logic design data typically in the form of a netlist - in the form of code or schematic
• a co-simulation process 220 is provided as input to a co-simulation process 220.
• the co-simulation process is utilized to ensure that the various types of elements will function together to provide the desired output. That is, the logic designs of each type of element are melded together in a single simulation process to assess the interworking of the digital element with the mixed signal elements, and further with the opto-electronic element.
• the netlist outputs from the separate logic design processes are also applied as inputs, as shown in step 230, to a physical layout process that functions to separately provide the physical layout of the digital element, the mixed signal elements and the opto-electronic element.
• the three layouts are submitted to internal verification processes to ensure that each separate layout is accurate before initiating the co-verification process.
• the (verified) data defining the three separate physical layout arrangements is then applied as an input to a co-verification routine, as shown in step 240.
• a co-verification process is used in accordance with the present invention to ensure that the layouts of the three types of elements will work together in a proper manner to allow for accurate operation of transmitter channel 100.
• a correction/feedback signal is applied as an input to allow for an adjustment to be made to the logic design, physical layout or both.
• the co-simulation and co-verification processes are then performed again and an updated comparison is performed. The process may continue in this manner until there is sufficient agreement between the co- simulation and co-verification results.

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• 2005
  • 2005-06-22 JP JP2007518269A patent/JP2008509452A/ja active Pending
  • 2005-06-22 CA CA2581451A patent/CA2581451C/en not_active Expired - Fee Related
  • 2005-06-22 WO PCT/US2005/022254 patent/WO2006007474A2/en not_active Ceased
  • 2005-06-22 CN CNB200580020911XA patent/CN100492372C/zh not_active Expired - Fee Related
  • 2005-06-22 KR KR1020077001314A patent/KR101145972B1/ko not_active Expired - Fee Related
  • 2005-06-22 US US11/159,283 patent/US7269809B2/en not_active Expired - Lifetime

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