CN101036145A - 用于单片、硅基光电电路的设计、仿真和验证的集成方法 - Google Patents
用于单片、硅基光电电路的设计、仿真和验证的集成方法 Download PDFInfo
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- CN101036145A CN101036145A CNA200580020911XA CN200580020911A CN101036145A CN 101036145 A CN101036145 A CN 101036145A CN A200580020911X A CNA200580020911X A CN A200580020911XA CN 200580020911 A CN200580020911 A CN 200580020911A CN 101036145 A CN101036145 A CN 101036145A
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- design
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- layout
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/36—Circuit design at the analogue level
- G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
Claims (11)
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US58223504P | 2004-06-23 | 2004-06-23 | |
US60/582,235 | 2004-06-23 | ||
US11/159,283 US7269809B2 (en) | 2004-06-23 | 2005-06-22 | Integrated approach for design, simulation and verification of monolithic, silicon-based opto-electronic circuits |
US11/159,283 | 2005-06-22 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101036145A true CN101036145A (zh) | 2007-09-12 |
CN100492372C CN100492372C (zh) | 2009-05-27 |
Family
ID=35507571
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB200580020911XA Expired - Fee Related CN100492372C (zh) | 2004-06-23 | 2005-06-22 | 用于单片、硅基光电电路的设计、仿真和验证的集成方法 |
Country Status (6)
Country | Link |
---|---|
US (1) | US7269809B2 (zh) |
JP (1) | JP2008509452A (zh) |
KR (1) | KR101145972B1 (zh) |
CN (1) | CN100492372C (zh) |
CA (1) | CA2581451C (zh) |
WO (1) | WO2006007474A2 (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101676920B (zh) * | 2008-09-15 | 2013-11-20 | 新思科技有限公司 | 用于合并覆盖数据的eda覆盖日志的方法和装置 |
CN105653744A (zh) * | 2014-11-13 | 2016-06-08 | 中芯国际集成电路制造(上海)有限公司 | 版图布局的设计方法及装置 |
Families Citing this family (28)
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US7944467B2 (en) * | 2003-12-01 | 2011-05-17 | Omnivision Technologies, Inc. | Task-based imaging systems |
WO2005054927A2 (en) | 2003-12-01 | 2005-06-16 | Cdm Optics, Inc. | System and method for optimizing optical and digital system designs |
US7248757B2 (en) * | 2003-12-15 | 2007-07-24 | Canon Kabushiki Kaisha | Method, device and computer program for designing a circuit having electric wires and optical connections |
US7672558B2 (en) | 2004-01-12 | 2010-03-02 | Honeywell International, Inc. | Silicon optical device |
US7217584B2 (en) * | 2004-03-18 | 2007-05-15 | Honeywell International Inc. | Bonded thin-film structures for optical modulators and methods of manufacture |
US7149388B2 (en) * | 2004-03-18 | 2006-12-12 | Honeywell International, Inc. | Low loss contact structures for silicon based optical modulators and methods of manufacture |
US7177489B2 (en) | 2004-03-18 | 2007-02-13 | Honeywell International, Inc. | Silicon-insulator-silicon thin-film structures for optical modulators and methods of manufacture |
US7448012B1 (en) | 2004-04-21 | 2008-11-04 | Qi-De Qian | Methods and system for improving integrated circuit layout |
US20060063679A1 (en) * | 2004-09-17 | 2006-03-23 | Honeywell International Inc. | Semiconductor-insulator-semiconductor structure for high speed applications |
WO2008008084A2 (en) * | 2005-09-19 | 2008-01-17 | Cdm Optics, Inc. | Task-based imaging systems |
US7362443B2 (en) * | 2005-11-17 | 2008-04-22 | Honeywell International Inc. | Optical gyro with free space resonator and method for sensing inertial rotation rate |
US7442589B2 (en) * | 2006-01-17 | 2008-10-28 | Honeywell International Inc. | System and method for uniform multi-plane silicon oxide layer formation for optical applications |
US7514285B2 (en) * | 2006-01-17 | 2009-04-07 | Honeywell International Inc. | Isolation scheme for reducing film stress in a MEMS device |
US7454102B2 (en) * | 2006-04-26 | 2008-11-18 | Honeywell International Inc. | Optical coupling structure |
CN100442298C (zh) * | 2006-05-15 | 2008-12-10 | 中芯国际集成电路制造(上海)有限公司 | 栅极根部缺陷与mosfet器件性能相关性的仿真方法 |
US8117576B2 (en) * | 2008-03-05 | 2012-02-14 | Rambus Inc. | Method for using an equivalence checker to reduce verification effort in a system having analog blocks |
US8316342B1 (en) * | 2010-06-02 | 2012-11-20 | Cadence Design Systems, Inc. | Method and apparatus for concurrent design of modules across different design entry tools targeted to a single layout |
US8521483B1 (en) | 2010-06-02 | 2013-08-27 | Cadence Design Systems, Inc. | Method and apparatus for concurrent design of modules across different design entry tools targeted to single simulation |
US8527257B2 (en) | 2011-07-01 | 2013-09-03 | Fujitsu Limited | Transition-based macro-models for analog simulation |
US8903698B2 (en) | 2012-05-15 | 2014-12-02 | Fujitsu Limited | Generating behavioral models for analog circuits |
US20150067621A1 (en) * | 2012-09-05 | 2015-03-05 | Mentor Graphics Corporation | Logic-Driven Layout Pattern Analysis |
CN103164566A (zh) * | 2012-12-04 | 2013-06-19 | 天津蓝海微科技有限公司 | 版图验证规则的测试向量辅助层生成方法 |
US8856701B1 (en) * | 2013-03-12 | 2014-10-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of radio-frequency and microwave device generation |
US8726205B1 (en) | 2013-04-15 | 2014-05-13 | Nvidia Corporation | Optimized simulation technique for design verification of an electronic circuit |
US8813019B1 (en) | 2013-04-30 | 2014-08-19 | Nvidia Corporation | Optimized design verification of an electronic circuit |
CN107567622B (zh) | 2015-07-08 | 2021-06-25 | 慧与发展有限责任合伙企业 | 光子电路设计系统和计算机可读介质 |
US11023648B2 (en) | 2017-12-12 | 2021-06-01 | Siemens Industry Software Inc. | Puzzle-based pattern analysis and classification |
CN117332742B (zh) * | 2023-12-01 | 2024-02-23 | 芯动微电子科技(武汉)有限公司 | 一种芯片设计阶段的仿真验证方法和装置 |
Family Cites Families (31)
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US5544067A (en) * | 1990-04-06 | 1996-08-06 | Lsi Logic Corporation | Method and system for creating, deriving and validating structural description of electronic system from higher level, behavior-oriented description, including interactive schematic design and simulation |
US5222030A (en) * | 1990-04-06 | 1993-06-22 | Lsi Logic Corporation | Methodology for deriving executable low-level structural descriptions and valid physical implementations of circuits and systems from high-level semantic specifications and descriptions thereof |
US5930150A (en) * | 1996-09-06 | 1999-07-27 | Lucent Technologies Inc. | Method and system for designing and analyzing optical application specific integrated circuits |
US5914889A (en) * | 1996-09-13 | 1999-06-22 | Lucent Technologies Inc. | Method and system for generating a mask layout of an optical integrated circuit |
US6110217A (en) * | 1997-10-03 | 2000-08-29 | International Business Machines Corporation | System and method for synchronization of multiple analog servers on a simulation backplane |
US6845184B1 (en) * | 1998-10-09 | 2005-01-18 | Fujitsu Limited | Multi-layer opto-electronic substrates with electrical and optical interconnections and methods for making |
US7031889B1 (en) * | 1999-03-22 | 2006-04-18 | Hewlett-Packard Development Company, L.P. | Method and apparatus for evaluating the design quality of network nodes |
US6446243B1 (en) * | 1999-04-23 | 2002-09-03 | Novas Software, Inc. | Method for functional verification of VLSI circuit designs utilizing reusable functional blocks or intellectual property cores |
US6438735B1 (en) * | 1999-05-17 | 2002-08-20 | Synplicity, Inc. | Methods and apparatuses for designing integrated circuits |
US6480816B1 (en) * | 1999-06-14 | 2002-11-12 | Sanjay Dhar | Circuit simulation using dynamic partitioning and on-demand evaluation |
US6816825B1 (en) * | 1999-06-18 | 2004-11-09 | Nec Corporation | Simulation vector generation from HDL descriptions for observability-enhanced statement coverage |
US7065481B2 (en) * | 1999-11-30 | 2006-06-20 | Synplicity, Inc. | Method and system for debugging an electronic system using instrumentation circuitry and a logic analyzer |
JP2001230638A (ja) * | 2000-02-18 | 2001-08-24 | Nec Eng Ltd | 光送受信回路の設計方法 |
US6587995B1 (en) * | 2000-04-19 | 2003-07-01 | Koninklijke Philips Electronics N.V. | Enhanced programmable core model with integrated graphical debugging functionality |
US6718522B1 (en) * | 2000-08-15 | 2004-04-06 | Hewlett-Packard Development Company, L.P. | Electrical rules checker system and method using tri-state logic for electrical rule checks |
US6502223B1 (en) * | 2001-04-30 | 2002-12-31 | Hewlett-Packard Company | Method for simulating noise on the input of a static gate and determining noise on the output |
US6912330B2 (en) * | 2001-05-17 | 2005-06-28 | Sioptical Inc. | Integrated optical/electronic circuits and associated methods of simultaneous generation thereof |
US6980945B2 (en) * | 2001-12-04 | 2005-12-27 | Koninklijke Philips Electronics N.V. | Synchronized simulation of software and hardware in the analog domain |
US6745372B2 (en) * | 2002-04-05 | 2004-06-01 | Numerical Technologies, Inc. | Method and apparatus for facilitating process-compliant layout optimization |
US20030195736A1 (en) * | 2002-04-11 | 2003-10-16 | Sun Microsystems, Inc. | Method of storing cross-hierarchy coupling data in a hierarchical circuit model |
US6898767B2 (en) * | 2002-05-09 | 2005-05-24 | Lsi Logic Corporation | Method and apparatus for custom design in a standard cell design environment |
US6826739B2 (en) * | 2002-05-13 | 2004-11-30 | Agilent Technologies, Inc. | System and method for placing substrate contacts in a datapath stack in an integrated circuit design |
US6983443B2 (en) * | 2002-05-22 | 2006-01-03 | Agilent Technologies, Inc. | System and method for placing clock drivers in a standard cell block |
US6807658B2 (en) * | 2002-06-05 | 2004-10-19 | Agilent Technologies, Inc. | Systems and methods for performing clock gating checks |
US6815729B1 (en) * | 2002-10-09 | 2004-11-09 | Cypress Semiconductor Corp. | Electro-optical apparatus |
AU2002952700A0 (en) * | 2002-11-18 | 2002-11-28 | Vpisystems Pty Ltd | Simulation player |
US7055113B2 (en) * | 2002-12-31 | 2006-05-30 | Lsi Logic Corporation | Simplified process to design integrated circuits |
US7155689B2 (en) * | 2003-10-07 | 2006-12-26 | Magma Design Automation, Inc. | Design-manufacturing interface via a unified model |
JP4532893B2 (ja) * | 2003-12-15 | 2010-08-25 | キヤノン株式会社 | 電気配線と光接続を有する回路の設計装置 |
JP4208706B2 (ja) * | 2003-12-15 | 2009-01-14 | キヤノン株式会社 | 電気配線と光接続を有する回路の設計装置 |
US6969903B2 (en) * | 2004-01-19 | 2005-11-29 | International Business Machines Corporation | High tolerance TCR balanced high current resistor for RF CMOS and RF SiGe BiCMOS applications and cadenced based hierarchical parameterized cell design kit with tunable TCR and ESD resistor ballasting feature |
-
2005
- 2005-06-22 KR KR1020077001314A patent/KR101145972B1/ko active IP Right Grant
- 2005-06-22 US US11/159,283 patent/US7269809B2/en active Active
- 2005-06-22 WO PCT/US2005/022254 patent/WO2006007474A2/en active Application Filing
- 2005-06-22 CA CA2581451A patent/CA2581451C/en not_active Expired - Fee Related
- 2005-06-22 CN CNB200580020911XA patent/CN100492372C/zh not_active Expired - Fee Related
- 2005-06-22 JP JP2007518269A patent/JP2008509452A/ja active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101676920B (zh) * | 2008-09-15 | 2013-11-20 | 新思科技有限公司 | 用于合并覆盖数据的eda覆盖日志的方法和装置 |
CN105653744A (zh) * | 2014-11-13 | 2016-06-08 | 中芯国际集成电路制造(上海)有限公司 | 版图布局的设计方法及装置 |
Also Published As
Publication number | Publication date |
---|---|
WO2006007474A3 (en) | 2007-04-19 |
CA2581451A1 (en) | 2006-01-19 |
KR101145972B1 (ko) | 2012-05-22 |
US7269809B2 (en) | 2007-09-11 |
CA2581451C (en) | 2013-09-24 |
US20050289490A1 (en) | 2005-12-29 |
CN100492372C (zh) | 2009-05-27 |
KR20070040792A (ko) | 2007-04-17 |
JP2008509452A (ja) | 2008-03-27 |
WO2006007474A2 (en) | 2006-01-19 |
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Legal Events
Date | Code | Title | Description |
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C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
ASS | Succession or assignment of patent right |
Owner name: CISCO TECH IND. Free format text: FORMER OWNER: LIGHTWIRE INC. Effective date: 20130627 |
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C41 | Transfer of patent application or patent right or utility model | ||
C56 | Change in the name or address of the patentee |
Owner name: LIGHTWIRE INC. Free format text: FORMER NAME: SIOPTICAL INC. |
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CP01 | Change in the name or title of a patent holder |
Address after: American Pennsylvania Patentee after: LIGHTWIRE, Inc. Address before: American Pennsylvania Patentee before: SIOPTICAL, Inc. |
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CP03 | Change of name, title or address |
Address after: California, USA Patentee after: LIGHTWIRE, Inc. Address before: American Pennsylvania Patentee before: LIGHTWIRE, Inc. |
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TR01 | Transfer of patent right |
Effective date of registration: 20130627 Address after: California, USA Patentee after: Cisco Technology, Inc. Address before: California, USA Patentee before: Lightwire, Inc. |
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CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090527 Termination date: 20210622 |
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CF01 | Termination of patent right due to non-payment of annual fee |