CN100492372C - 用于单片、硅基光电电路的设计、仿真和验证的集成方法 - Google Patents

用于单片、硅基光电电路的设计、仿真和验证的集成方法 Download PDF

Info

Publication number
CN100492372C
CN100492372C CNB200580020911XA CN200580020911A CN100492372C CN 100492372 C CN100492372 C CN 100492372C CN B200580020911X A CNB200580020911X A CN B200580020911XA CN 200580020911 A CN200580020911 A CN 200580020911A CN 100492372 C CN100492372 C CN 100492372C
Authority
CN
China
Prior art keywords
design
simulation
verification
logic
physical layout
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB200580020911XA
Other languages
English (en)
Chinese (zh)
Other versions
CN101036145A (zh
Inventor
卡尔潘都·夏斯特里
索哈姆·帕塔克
普拉卡什·约托斯卡
鲍利尔斯·莫欣斯基斯
拜平·达玛
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cisco Technology Inc
Lightwire LLC
Original Assignee
SiOptical Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SiOptical Inc filed Critical SiOptical Inc
Publication of CN101036145A publication Critical patent/CN101036145A/zh
Application granted granted Critical
Publication of CN100492372C publication Critical patent/CN100492372C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
CNB200580020911XA 2004-06-23 2005-06-22 用于单片、硅基光电电路的设计、仿真和验证的集成方法 Expired - Fee Related CN100492372C (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US58223504P 2004-06-23 2004-06-23
US60/582,235 2004-06-23
US11/159,283 2005-06-22
US11/159,283 US7269809B2 (en) 2004-06-23 2005-06-22 Integrated approach for design, simulation and verification of monolithic, silicon-based opto-electronic circuits

Publications (2)

Publication Number Publication Date
CN101036145A CN101036145A (zh) 2007-09-12
CN100492372C true CN100492372C (zh) 2009-05-27

Family

ID=35507571

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB200580020911XA Expired - Fee Related CN100492372C (zh) 2004-06-23 2005-06-22 用于单片、硅基光电电路的设计、仿真和验证的集成方法

Country Status (6)

Country Link
US (1) US7269809B2 (OSRAM)
JP (1) JP2008509452A (OSRAM)
KR (1) KR101145972B1 (OSRAM)
CN (1) CN100492372C (OSRAM)
CA (1) CA2581451C (OSRAM)
WO (1) WO2006007474A2 (OSRAM)

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007513427A (ja) * 2003-12-01 2007-05-24 シーディーエム オプティックス， インコーポレイテッド 光学システムおよびデジタルシステムの設計を最適化するシステムおよび方法
US7944467B2 (en) * 2003-12-01 2011-05-17 Omnivision Technologies, Inc. Task-based imaging systems
US7248757B2 (en) * 2003-12-15 2007-07-24 Canon Kabushiki Kaisha Method, device and computer program for designing a circuit having electric wires and optical connections
US7672558B2 (en) 2004-01-12 2010-03-02 Honeywell International, Inc. Silicon optical device
US7217584B2 (en) * 2004-03-18 2007-05-15 Honeywell International Inc. Bonded thin-film structures for optical modulators and methods of manufacture
US7177489B2 (en) 2004-03-18 2007-02-13 Honeywell International, Inc. Silicon-insulator-silicon thin-film structures for optical modulators and methods of manufacture
US7149388B2 (en) * 2004-03-18 2006-12-12 Honeywell International, Inc. Low loss contact structures for silicon based optical modulators and methods of manufacture
US7448012B1 (en) 2004-04-21 2008-11-04 Qi-De Qian Methods and system for improving integrated circuit layout
US20060063679A1 (en) * 2004-09-17 2006-03-23 Honeywell International Inc. Semiconductor-insulator-semiconductor structure for high speed applications
WO2008008084A2 (en) * 2005-09-19 2008-01-17 Cdm Optics, Inc. Task-based imaging systems
US7362443B2 (en) * 2005-11-17 2008-04-22 Honeywell International Inc. Optical gyro with free space resonator and method for sensing inertial rotation rate
US7442589B2 (en) * 2006-01-17 2008-10-28 Honeywell International Inc. System and method for uniform multi-plane silicon oxide layer formation for optical applications
US7514285B2 (en) * 2006-01-17 2009-04-07 Honeywell International Inc. Isolation scheme for reducing film stress in a MEMS device
US7463360B2 (en) 2006-04-18 2008-12-09 Honeywell International Inc. Optical resonator gyro with integrated external cavity beam generator
US7454102B2 (en) * 2006-04-26 2008-11-18 Honeywell International Inc. Optical coupling structure
US7535576B2 (en) 2006-05-15 2009-05-19 Honeywell International, Inc. Integrated optical rotation sensor and method for sensing rotation rate
CN100442298C (zh) * 2006-05-15 2008-12-10 中芯国际集成电路制造(上海)有限公司 栅极根部缺陷与mosfet器件性能相关性的仿真方法
US8117576B2 (en) * 2008-03-05 2012-02-14 Rambus Inc. Method for using an equivalence checker to reduce verification effort in a system having analog blocks
US8219947B2 (en) * 2008-09-15 2012-07-10 Synopsys, Inc. Method and apparatus for merging EDA coverage logs of coverage data
US8316342B1 (en) * 2010-06-02 2012-11-20 Cadence Design Systems, Inc. Method and apparatus for concurrent design of modules across different design entry tools targeted to a single layout
US8521483B1 (en) 2010-06-02 2013-08-27 Cadence Design Systems, Inc. Method and apparatus for concurrent design of modules across different design entry tools targeted to single simulation
US8527257B2 (en) 2011-07-01 2013-09-03 Fujitsu Limited Transition-based macro-models for analog simulation
US8903698B2 (en) 2012-05-15 2014-12-02 Fujitsu Limited Generating behavioral models for analog circuits
US20150067621A1 (en) * 2012-09-05 2015-03-05 Mentor Graphics Corporation Logic-Driven Layout Pattern Analysis
CN103164566A (zh) * 2012-12-04 2013-06-19 天津蓝海微科技有限公司 版图验证规则的测试向量辅助层生成方法
US8856701B1 (en) * 2013-03-12 2014-10-07 Taiwan Semiconductor Manufacturing Co., Ltd. Method of radio-frequency and microwave device generation
US8726205B1 (en) 2013-04-15 2014-05-13 Nvidia Corporation Optimized simulation technique for design verification of an electronic circuit
US8813019B1 (en) 2013-04-30 2014-08-19 Nvidia Corporation Optimized design verification of an electronic circuit
CN105653744A (zh) * 2014-11-13 2016-06-08 中芯国际集成电路制造(上海)有限公司 版图布局的设计方法及装置
CN107567622B (zh) 2015-07-08 2021-06-25 慧与发展有限责任合伙企业 光子电路设计系统和计算机可读介质
US11023648B2 (en) 2017-12-12 2021-06-01 Siemens Industry Software Inc. Puzzle-based pattern analysis and classification
US12387022B2 (en) * 2022-03-02 2025-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method of optimizing an integrated circuit design
CN118194813A (zh) * 2023-12-01 2024-06-14 芯动微电子科技(武汉)有限公司 一种芯片设计阶段的仿真验证方法和装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6110217A (en) * 1997-10-03 2000-08-29 International Business Machines Corporation System and method for synchronization of multiple analog servers on a simulation backplane
US20030195736A1 (en) * 2002-04-11 2003-10-16 Sun Microsystems, Inc. Method of storing cross-hierarchy coupling data in a hierarchical circuit model
US20030221179A1 (en) * 2002-05-22 2003-11-27 Korzyniowski Ryan Matthew System and method for placing clock drivers in a standard cell block
US6718522B1 (en) * 2000-08-15 2004-04-06 Hewlett-Packard Development Company, L.P. Electrical rules checker system and method using tri-state logic for electrical rule checks
US20040107085A1 (en) * 2002-11-18 2004-06-03 Vpisystems Pte Simulation player

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5544067A (en) * 1990-04-06 1996-08-06 Lsi Logic Corporation Method and system for creating, deriving and validating structural description of electronic system from higher level, behavior-oriented description, including interactive schematic design and simulation
US5222030A (en) * 1990-04-06 1993-06-22 Lsi Logic Corporation Methodology for deriving executable low-level structural descriptions and valid physical implementations of circuits and systems from high-level semantic specifications and descriptions thereof
US5930150A (en) * 1996-09-06 1999-07-27 Lucent Technologies Inc. Method and system for designing and analyzing optical application specific integrated circuits
US5914889A (en) * 1996-09-13 1999-06-22 Lucent Technologies Inc. Method and system for generating a mask layout of an optical integrated circuit
US6845184B1 (en) * 1998-10-09 2005-01-18 Fujitsu Limited Multi-layer opto-electronic substrates with electrical and optical interconnections and methods for making
US7031889B1 (en) * 1999-03-22 2006-04-18 Hewlett-Packard Development Company, L.P. Method and apparatus for evaluating the design quality of network nodes
US6446243B1 (en) * 1999-04-23 2002-09-03 Novas Software, Inc. Method for functional verification of VLSI circuit designs utilizing reusable functional blocks or intellectual property cores
US6438735B1 (en) * 1999-05-17 2002-08-20 Synplicity, Inc. Methods and apparatuses for designing integrated circuits
US6480816B1 (en) * 1999-06-14 2002-11-12 Sanjay Dhar Circuit simulation using dynamic partitioning and on-demand evaluation
US6816825B1 (en) * 1999-06-18 2004-11-09 Nec Corporation Simulation vector generation from HDL descriptions for observability-enhanced statement coverage
US7065481B2 (en) * 1999-11-30 2006-06-20 Synplicity, Inc. Method and system for debugging an electronic system using instrumentation circuitry and a logic analyzer
JP2001230638A (ja) * 2000-02-18 2001-08-24 Nec Eng Ltd 光送受信回路の設計方法
US6587995B1 (en) * 2000-04-19 2003-07-01 Koninklijke Philips Electronics N.V. Enhanced programmable core model with integrated graphical debugging functionality
US6502223B1 (en) * 2001-04-30 2002-12-31 Hewlett-Packard Company Method for simulating noise on the input of a static gate and determining noise on the output
US6912330B2 (en) * 2001-05-17 2005-06-28 Sioptical Inc. Integrated optical/electronic circuits and associated methods of simultaneous generation thereof
US6980945B2 (en) * 2001-12-04 2005-12-27 Koninklijke Philips Electronics N.V. Synchronized simulation of software and hardware in the analog domain
US6745372B2 (en) * 2002-04-05 2004-06-01 Numerical Technologies, Inc. Method and apparatus for facilitating process-compliant layout optimization
US6898767B2 (en) * 2002-05-09 2005-05-24 Lsi Logic Corporation Method and apparatus for custom design in a standard cell design environment
US6826739B2 (en) * 2002-05-13 2004-11-30 Agilent Technologies, Inc. System and method for placing substrate contacts in a datapath stack in an integrated circuit design
US6807658B2 (en) * 2002-06-05 2004-10-19 Agilent Technologies, Inc. Systems and methods for performing clock gating checks
US6815729B1 (en) * 2002-10-09 2004-11-09 Cypress Semiconductor Corp. Electro-optical apparatus
US7055113B2 (en) * 2002-12-31 2006-05-30 Lsi Logic Corporation Simplified process to design integrated circuits
US7155689B2 (en) * 2003-10-07 2006-12-26 Magma Design Automation, Inc. Design-manufacturing interface via a unified model
JP4532893B2 (ja) * 2003-12-15 2010-08-25 キヤノン株式会社 電気配線と光接続を有する回路の設計装置
JP4208706B2 (ja) * 2003-12-15 2009-01-14 キヤノン株式会社 電気配線と光接続を有する回路の設計装置
US6969903B2 (en) * 2004-01-19 2005-11-29 International Business Machines Corporation High tolerance TCR balanced high current resistor for RF CMOS and RF SiGe BiCMOS applications and cadenced based hierarchical parameterized cell design kit with tunable TCR and ESD resistor ballasting feature

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6110217A (en) * 1997-10-03 2000-08-29 International Business Machines Corporation System and method for synchronization of multiple analog servers on a simulation backplane
US6718522B1 (en) * 2000-08-15 2004-04-06 Hewlett-Packard Development Company, L.P. Electrical rules checker system and method using tri-state logic for electrical rule checks
US20030195736A1 (en) * 2002-04-11 2003-10-16 Sun Microsystems, Inc. Method of storing cross-hierarchy coupling data in a hierarchical circuit model
US20030221179A1 (en) * 2002-05-22 2003-11-27 Korzyniowski Ryan Matthew System and method for placing clock drivers in a standard cell block
US20040107085A1 (en) * 2002-11-18 2004-06-03 Vpisystems Pte Simulation player

Also Published As

Publication number Publication date
JP2008509452A (ja) 2008-03-27
KR101145972B1 (ko) 2012-05-22
KR20070040792A (ko) 2007-04-17
CA2581451A1 (en) 2006-01-19
US7269809B2 (en) 2007-09-11
US20050289490A1 (en) 2005-12-29
WO2006007474A2 (en) 2006-01-19
WO2006007474A3 (en) 2007-04-19
CN101036145A (zh) 2007-09-12
CA2581451C (en) 2013-09-24

Similar Documents

Publication Publication Date Title
CN100492372C (zh) 用于单片、硅基光电电路的设计、仿真和验证的集成方法
Gielen et al. Computer-aided design of analog and mixed-signal integrated circuits
US6131182A (en) Method and apparatus for synthesizing and optimizing control logic based on SRCMOS logic array macros
CN104376138B (zh) 集成电路芯片的时序确定方法和装置
US20080120085A1 (en) Transaction co-validation across abstraction layers
JPH10207937A (ja) レイアウト・クリティカルなネット用のタイミング・エラー限界値をフィルタリングすることにより、マイクロエレクトロニクス回路のレイアウト後検証を実行する方法、装置およびコンピュータ・プログラム製品
WO2007020439A1 (en) Pattern matching and pattern replacement
US6601024B1 (en) Code translation between hardware design languages
US20080295057A1 (en) Method for determining a standard cell for ic design
WO1999009497A1 (fr) Procede d'extraction de caracteristiques de synchronisation de circuits a transistors, support de stockage stockant une bibliotheque de caracteristiques de synchronisation, procede de conception de lsi et procede d'extraction par grille
Scheible Optimized is not always optimal-the dilemma of analog design automation
Donnay et al. Using top-down CAD tools for mixed analog/digital ASICs: a practical design case
US7861198B2 (en) Distorted waveform propagation and crosstalk delay analysis using multiple cell models
Kommuru et al. ASIC design flow tutorial using synopsys tools
Heins et al. Design flow automation for silicon photonics: Challenges, collaboration, and standardization
Meiners et al. Schematic driven MEMS design
CN119808668A (zh) 芯片设计的方法、装置、设备、存储介质和程序产品
US6453448B1 (en) Functional level configuration of input-output test circuitry
Malavasi et al. A top-down, constraint-driven design methodology for analog integrated circuits
US7272542B1 (en) Method and system for re-targeting integrated circuits
Lienig et al. Methodologies for Physical Design: Models, Styles, Tasks, and Flows
Richard Building a System
US7131079B2 (en) Method of generating protected standard delay format file
Lamant et al. Schematic driven simulation and layout of complex photonic IC's
Kundert et al. Analog verification

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
ASS Succession or assignment of patent right

Owner name: CISCO TECH IND.

Free format text: FORMER OWNER: LIGHTWIRE INC.

Effective date: 20130627

C41 Transfer of patent application or patent right or utility model
C56 Change in the name or address of the patentee

Owner name: LIGHTWIRE INC.

Free format text: FORMER NAME: SIOPTICAL INC.

CP01 Change in the name or title of a patent holder

Address after: American Pennsylvania

Patentee after: LIGHTWIRE, Inc.

Address before: American Pennsylvania

Patentee before: SIOPTICAL, Inc.

CP03 Change of name, title or address

Address after: California, USA

Patentee after: LIGHTWIRE, Inc.

Address before: American Pennsylvania

Patentee before: LIGHTWIRE, Inc.

TR01 Transfer of patent right

Effective date of registration: 20130627

Address after: California, USA

Patentee after: Cisco Technology, Inc.

Address before: California, USA

Patentee before: Lightwire, Inc.

CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20090527

Termination date: 20210622

CF01 Termination of patent right due to non-payment of annual fee