Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
  • H10D84/611—Combinations of BJTs and one or more of diodes, resistors or capacitors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/101—Integrated devices comprising main components and built-in components, e.g. IGBT having built-in freewheel diode
  • H10D84/121—BJTs having built-in components
  • H10D84/125—BJTs having built-in components the built-in components being resistive elements, e.g. BJT having a built-in ballasting resistor
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
  • H10D84/611—Combinations of BJTs and one or more of diodes, resistors or capacitors
  • H10D84/613—Combinations of vertical BJTs and one or more of diodes, resistors or capacitors
  • H10D84/617—Combinations of vertical BJTs and only diodes

Definitions

• the present invention relates to a bipolar transistor with a built-in resistor.
• a bipolar transistor with a built-in resistor is mainly used for switching applications, and generally has a structure in which a resistor is connected in series with the base and in parallel between the base-emitter as shown in Fig. 1. Since bipolar transistors with built-in resistors are often used in large quantities in electronic circuits, as shown in Fig. 2, two transistors in the same package are also produced. It is manufactured by mounting the above transistor chips in the same package.
• resistors are connected to the collector and the base of the transistor.
• this circuit is configured by forming the transistor and the two resistors by separate components, Alternatively, it is formed using a single resistor and a transistor with a built-in resistor in the base.
• FIG. 4 shows the structure of a conventional general bipolar transistor with a built-in resistor.
• the figure shows the case of an NPN bipolar transistor.
• An N-type epitaxial layer 2 is formed on an N-type high impurity concentration semiconductor substrate 1, and a P-type region 3 is formed on a part of the N-type epitaxial layer 2.
• N-type region 4 is formed on the portion.
• a resistor 6 made of polycrystalline silicon is formed on a part of the N-type epitaxial layer 2 via an insulating film 5, and is wired by wiring electrodes 7, 8 and 9.
• NPN transistor When an NPN transistor is configured with this structure, (A) N-type epitaxial layer 2; collector, P-type region 3; base, N-type region 4; emitter, and (B) N-type epitaxial layer 2 ; Emitter, P-type region 3; Base, N-type region 4; Collector may be used, but due to the concentration of each region described above, the DC current amplification factor hFE is about 10 in the configuration of (B). Generally used in configuration (A) Is done.
• FIG. 1 it is possible to configure a bipolar transistor with a built-in resistor in which a resistor is connected to the base and the emitter. As shown in the muting circuit shown in FIG. It is very difficult to configure the circuits connected to the same chip on the same chip.
• the present invention has been made in view of the above-mentioned problems of the related art, and easily forms a bipolar transistor with a built-in resistor having a collector connected to a resistor and a plurality of bipolar transistors with a built-in resistor on the same chip. It provides a possible bipolar transistor structure.
• an N-type semiconductor substrate an N-type semiconductor substrate; a P-type impurity region formed on the N-type semiconductor substrate and formed so as to surround the periphery with the N-type semiconductor region; An N-type impurity region formed on the N-type semiconductor substrate, and a semiconductor layer formed on a part of the N-type semiconductor substrate via an insulating layer.
• the impurity concentration of each region can be such that N-type semiconductor substrate> P-type impurity region ⁇ N-type impurity region. Therefore, (A) N-type semiconductor substrate; collector, P-type (B) N-type semiconductor substrate; emitter, P-type impurity region; base and N-type impurity region; DC current gain in both cases of using as collector hFE can be set to 100 or more. [0010] Therefore, when the configuration of (B) is adopted, it is possible to easily form a bipolar transistor with a built-in resistor having a collector connected to a resistor and a plurality of bipolar transistors with a built-in resistor on the same chip. .
• the resistor and the bipolar transistor are the same even when a resistor is connected to the collector as in the muting circuit shown in FIG. Can be formed on a chip. Also, since multiple bipolar transistors with built-in resistors can be formed on the same chip, it is possible to increase the production efficiency of two transistors in the same package as shown in Fig. 2. .
• FIG. 1 is an equivalent circuit of a bipolar transistor with a built-in resistor.
• Figure 2 shows the case where two bipolar transistors with built-in resistors are mounted in the same package.
• FIG. 3 shows a muting circuit
• FIG. 4 shows the structure of a conventional bipolar transistor with a built-in resistor.
• FIG. 5 shows a case where two conventional bipolar transistors with built-in resistors are formed on the same chip.
• FIG. 6 is an equivalent circuit when two conventional bipolar transistors with built-in resistors are formed on the same chip.
• FIG. 7 shows a structure of a resistor built-in neural transistor according to the present invention.
• FIG. 8 is an equivalent circuit of the bipolar transistor with a built-in resistor in FIG.
• FIG. 9 shows a manufacturing process of the bipolar transistor with a built-in resistor according to the present invention.
• FIG. 10 shows a manufacturing process of the resistor built-in neural transistor according to the present invention.
• FIG. 11 shows a manufacturing process of the resistor built-in bipolar transistor according to the present invention.
• FIG. 12 shows a manufacturing process of the built-in resistor bipolar transistor according to the present invention.
• FIG. 13 shows a manufacturing process of the resistor built-in neural transistor according to the present invention.
• FIG. 14 shows a manufacturing process of the resistor built-in neural transistor according to the present invention.
• FIG. 15 shows another embodiment 2 of the present invention.
• FIG. 16 shows another embodiment 3 of the present invention.
• FIG. 17 is an equivalent circuit of the structure of FIG.
• FIG. 18 shows another embodiment 4 of the present invention.
• FIG. 19 is an equivalent circuit of the structure of FIG.
• FIG. 20 shows another embodiment 5 of the present invention.
• a low-concentration P-type semiconductor layer 12 is formed on an N-type (hereinafter referred to as N +) semiconductor substrate 11 having a high impurity concentration, and a low-concentration P-type semiconductor layer 12 is formed on the semiconductor substrate 1. It is formed so as to surround the periphery of the layer 12.
• An N + -type impurity region 15 is formed on a part of the P-type semiconductor layer 12.
• a semiconductor layer 17 serving as a resistor is formed on a part of the N + type semiconductor substrate 11 via an insulating layer 16, and wiring electrodes 18, 19, and 20 are formed.
• a transistor is formed. Note that a P + type impurity region 14 can be formed on a part of the P type semiconductor layer 12 as needed.
• an N + -type silicon substrate 11 is prepared, and a P-type semiconductor layer 12 is formed by epitaxy.
• the specific impurity concentration of each of these regions is, for example, N + type semiconductor substrate 11; 1 ⁇ 10 18 cm— 3 —IX 10 20 cm ′′ 3 , P-type semiconductor layer 12; 2 ⁇ 10 14 cm— 3— 4 x 10 16 cm— 3 mag.
• an N-type impurity such as phosphorus is selectively injected and diffused to form an N + -type diffusion region 13 so as to surround the P-type semiconductor layer 12.
• the N + type diffusion region 13 is formed so as to reach near the N + type semiconductor substrate 1, and is preferably formed with a sheet resistance of several tens ⁇ / slot or less.
• a P-type region 14 is formed by selectively implanting and diffusing a P-type impurity such as boron.
• the P + type region 14 is provided to reduce the contact resistance between the P-type semiconductor layer 12 and the wiring electrode, and is not necessary when the impurity concentration of the P-type semiconductor layer 12 is sufficiently high.
• the concentration of the P + type impurity may be about 1 ⁇ 10 17 cm ′′ -3 ⁇ 1 ⁇ 10 20 cm ⁇ 3 in surface concentration.
• an N-type region 15 is formed by selectively implanting and diffusing an N-type impurity such as phosphorus.
• concentration of the N + -type region, the surface concentration of 1 X 10 19 cm “3 one 1 X 10 2Q C m- 3 may be the extent.
• the DC current amplification factor hFE of the bipolar transistor of the present structure, N Since it is determined by the diffusion depth of the + -type region 15, it is necessary to control as necessary.
• silicon oxide films are formed by thermal oxidation or CVD (irradiative vapor phase epitaxy) or the like, and this silicon oxide film 16 is formed. Approximately 5000 openings of polycrystalline silicon are deposited on a part of the film 16, and a resistor 17 is formed by forming a pattern having an appropriate shape and implanting impurities.
• a contact hole is formed at an appropriate portion of the silicon oxide film 16, and wiring electrodes 18, 19, and 20 are formed by using a film or the like.
• a resistor built-in Neupolar transistor according to the present invention is completed.
• Example 1 according to the present invention is shown in FIG. This is the case where a resistor is connected to the collector.
• Fig. 8 shows an equivalent circuit.
• FIG. 15 shows a second embodiment according to the present invention. This is because resistors are formed in series with the collector and the base, respectively, and the equivalent circuit is as shown in Fig. 3.
• FIG. 16 shows a third embodiment according to the present invention. This is the case where a resistor is formed in parallel between the emitter bases, and the equivalent circuit is as shown in FIG.
• Example 4 according to the present invention is shown in FIG. This is the case where a resistor is further formed in series with the base in the case of FIG. 16, and the equivalent circuit is as shown in FIG.
• FIG. 20 shows a fifth embodiment according to the present invention. This is the case where two bipolar transistors with built-in resistors shown in FIG. 18 are formed on the same chip.

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• Bipolar Transistors (AREA)
• Bipolar Integrated Circuits (AREA)
• Semiconductor Integrated Circuits (AREA)

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• 2004
  • 2004-04-02 JP JP2004109640A patent/JP2005294659A/ja active Pending
  • 2004-09-22 CN CNB2004800424732A patent/CN100444401C/zh not_active Expired - Fee Related
  • 2004-09-22 WO PCT/JP2004/013783 patent/WO2005101517A1/ja not_active Ceased
  • 2004-09-22 KR KR1020067018390A patent/KR20060129050A/ko not_active Ceased

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