CN100444401C - 电阻内置型双极晶体管 - Google Patents

电阻内置型双极晶体管 Download PDF

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CN100444401C
CN100444401C CNB2004800424732A CN200480042473A CN100444401C CN 100444401 C CN100444401 C CN 100444401C CN B2004800424732 A CNB2004800424732 A CN B2004800424732A CN 200480042473 A CN200480042473 A CN 200480042473A CN 100444401 C CN100444401 C CN 100444401C
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松永平
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Isahaya Electronics Corp
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Abstract

在本发明的结构包括：N型半导体衬底；P型杂质区，形成在上述N型半导体衬底上、且形成为N型半导体区围绕在其周围；N型杂质区，形成在上述P型杂质区的一部分上；以及半导体层；隔着绝缘层形成在上述N型半导体衬底的一部分之上。在采用该结构的情况下，由于可使各区域的杂质浓度为N型半导体衬底＞P型杂质区＜N型杂质区，因此在(A)以N型半导体衬底为集电极、以P型杂质区为基极、以N型杂质区为发射极；(B)以N型半导体衬底为发射极、以P型杂质区为基极、以N型杂质区为集电极这两种情况下，都可使直流电流放大系数hFE大于或等于100。因此，在采用上述(B)结构的情况下，可以实现电阻与集电极连接的电阻内置型双极晶体管、以及容易地在同一芯片上形成多个电阻内置型双极晶体管。

Description

电阻内置型双极晶体管
技术领域
本发明涉及一种电阻内置型双极晶体管。电阻内置型双极晶体管主要是用作开关，如图1所示，一般结构是电阻与基极串联连接，且在基极-发射极之间并联连接电阻。在电子电路中，由于经常大量使用该电阻内置型双极晶体管，因此如图2所示，还生产把2个晶体管置入同一封装体的封装体，在该情况下，把2个晶体管芯片搭载于同一封装体来制造。
另外，在图3所示的噪声抑制电路中，晶体管的集电极以及基极连接有电阻，目前，该电路由分立部件形成晶体管和2个电阻，或是使用1个电阻和在基极内置了电阻的晶体管来形成。
背景技术
图4表示以往的普通电阻内置型双极晶体管的结构。该图表示NPN型双极晶体管的情况。在N型高杂质浓度半导体衬底1上形成有N型的外延层2，在该N型的外延层2的一部分上形成有P区3，在该P区3的一部分上形成有N区4。并且，在N型外延层2的一部分之上，隔着绝缘膜5形成有多晶硅电阻6，利用布线电极7、8、9来形成布线。
在该结构中，各区域的杂质浓度的关系因制造工序的顺序而成为：N型外延层2＜P区3＜N区4。由该结构来构成NPN型晶体管的情况包括：(A)以N型外延层2为集电极、以P区3为基极、以N区4为发射极；(B)以N型外延层2为发射极、以P区3为基极、以N区4为集电极。由于上述各区域的浓度关系，在(B)结构的情况下，直流电流放大系数hFE较低，在10左右，所以，一般使用(A)结构。
因此，如图1所示，可以形成电阻与基极、发射极连接的电阻内置型双极晶体管，但如图3所示的噪声抑制电路所示，很难在同一芯片上形成电阻与集电极连接的电路。
另外，如图2所示，在同一封装体内置入了2个晶体管的产品中，如果可以在同一芯片上形成该2个晶体管，则从组装角度来看非常有利。但在上述以往的结构的情况下，如图5所示，由于共用集电极，因此难以实现。图6表示等效电路。
发明内容
本发明就是鉴于上述以往技术的问题而做出的，提供一种电阻与集电极连接的电阻内置型双极晶体管、以及可以容易地在同一芯片上形成多个电阻内置型双极晶体管的双极晶体管结构。
对把本发明的结构应用在NPN式电阻内置型双极晶体管中的情况进行说明。本发明的结构包括：N型半导体衬底；P型杂质区，形成在上述N型半导体衬底上、且形成为N型半导体区围绕在其周围；N型杂质区，形成在上述P型杂质区的一部分上；以及半导体层，隔着绝缘层形成在上述N型半导体衬底的一部分之上。图7示出了一个例子。
在采用该结构的情况下，由于可使各区域的杂质浓度为N型半导体衬底＞P型杂质区＜N型杂质区，因此在(A)以N型半导体衬底为集电极、以P型杂质区为基极、以N型杂质区为发射极，(B)以N型半导体衬底为发射极、以P型杂质区为基极、以N型杂质区为集电极这两种情况下，都可以使直流电流放大系数hFE大于或等于100。
因此，在采用上述(B)结构的情况下，可以实现电阻与集电极连接的电阻内置型双极晶体管、以及容易地在同一芯片上形成多个电阻内置型双极晶体管。
这样，在采用本发明涉及的电阻内置型双极晶体管的情况下，即便是在如图3所示的噪声抑制电路所示，电阻与集电极连接的情况下，也可以在同一芯片上形成电阻和双极晶体管。并且，由于可以在同一芯片上形成多个电阻内置型双极晶体管，因此可以提高图2所示的同一封装体内置入了2个晶体管的封装体的生产效率。
附图说明
图1是电阻内置型双极晶体管的等效电路的图。
图2是在同一封装体内搭载了2个电阻内置型双极晶体管的情况的图。
图3是噪声抑制电路的图。
图4是以往的电阻内置型双极晶体管的结构的图。
图5是在同一封装体内形成了2个以往的电阻内置型双极晶体管的情况的图。
图6是在同一封装体内形成了2个以往的电阻内置型双极晶体管的情况下的等效电路图。
图7是本发明的电阻内置型双极晶体管的结构的图。
图8是图7的电阻内置型双极晶体管的等效电路的图。
图9是本发明的电阻内置型双极晶体管的制造工序的图。
图10是本发明的电阻内置型双极晶体管的制造工序的图。
图11是本发明的电阻内置型双极晶体管的制造工序的图。
图12是本发明的电阻内置型双极晶体管的制造工序的图。
图13是本发明的电阻内置型双极晶体管的制造工序的图。
图14是本发明的电阻内置型双极晶体管的制造工序的图。
图15是本发明的实施例2的图。
图16是本发明的实施例3的图。
图17是图16的结构的等效电路的图。
图18是本发明的实施例4的图。
图19是图18的结构的等效电路的图。
图20是本发明的实施例5的图。
符号说明：
1、11 N型高杂质浓度半导体衬底
2 N型外延层
3、3A、3B P区
4、4A、4B N区
5绝缘膜
6、6A、6B多晶硅(电阻)
7、7A、7B发射极布线电极
8、8A、8B基极布线电极1
9、9A、9B基极布线电极2
12 P型半导体层
13 N+型杂质区
14 P+型杂质区
15 N+型杂质区
16绝缘膜
17、21、23A、23B多晶硅(电阻)
18、18A、18B基极布线电极1
19、19A、19B集电极布线电极1
20集电极布线电极2
22、22A、22B发射极布线电极
24基极布线电极2
具体实施方式
利用图7以NPN型的情况为例来说明本发明的电阻内置型双极晶体管的实施方式。在高杂质浓度的N型(以下，称为N型)半导体衬底11上形成浓度低于上述半导体衬底11的P型半导体层12，N+型杂质区13形成为围绕在上述低浓度的P型半导体层12的周围。在上述P型半导体层12的一部分上形成N+型杂质区15。并且，在上述N+型半导体衬底11的一部分之上，隔着绝缘层16形成成为电阻的半导体层17，并形成布线电极18、19、20，由此形成本发明的电阻内置型双极晶体管。另外，根据需要还可以在上述P型半导体层12的一部分上形成P+型杂质区14。
在采用本结构的情况下，可以采用以半导体衬底11为发射极、以P型半导体层12为基极、以N+型杂质区15为集电极的结构，如图8所示的等效电路所示，可以形成电阻与集电极连接的电阻内置型双极晶体管。
接着，说明本发明的电阻内置型双极晶体管的制造方法。首先，如图9所示，准备N+型硅衬底11，利用外延生长法来形成P型半导体层12。作为这些区域的具体的杂质浓度，例如，N+型半导体衬底11为1×1018cm-3～1×1020cm-3、P型半导体层12为2×1014cm-3～4×1016cm-3等。
接着，如图10所示，选择性地注入扩散磷等N型杂质，形成N+型扩散区13，使得围绕在P型半导体层12的周围。并且，优选将N+型扩散区13形成得到达N+型半导体衬底11，作为薄层电阻形成为数十Ω/□以下。
接着，如图11所示，选择性地注入扩散硼等P型杂质，形成P+型区14。该P+型区14是为了降低P型半导体层12和布线电极的接触电阻而设置的，且P型半导体层12的杂质浓度不必过高。另外，作为P+型杂质的浓度，可以使表面浓度为1×1017cm-3～1×1020cm-3左右。
接着，如图12所示，选择性地注入扩散磷等N型杂质，形成N+型区15。作为该N+型区的浓度，可以使表面浓度为1×1019cm-3～1×1020cm-3左右。并且，由于本结构的双极晶体管的直流电流放大系数hFE是由N+型区15的扩散深度决定的，因此需要根据需要进行控制。
接着，如图13所示，利用热氧化或CVD(化学汽相淀积法)等，把硅氧化膜16形成为
Figure C20048004247300081
左右，在该硅氧化膜16的一部分上淀积
Figure C20048004247300082
左右的多晶硅，并形成适当形状的图形以及注入杂质，由此形成电阻17。
接着，如图14所示，在硅氧化膜16的适当的位置形成接触孔，并用铝等来形成布线电极18、19、20，由此完成本发明的电阻内置型双极晶体管。
实施例1
图7表示本发明的实施例1。其为在集电极连接了电阻的情况，图8表示等效电路。
实施例2
图15表示本发明的实施例2。其为在集电极和基极分别串联地形成了电阻，等效电路如图3所示。
实施例3
图16表示本发明的实施例3。其为在发射极-基极之间并联地形成了电阻的情况，等效电路如图17所示。
实施例4
图18表示本发明的实施例4。其为在图16所示的情况下，进一步在基极串联地形成了电阻的情况，等效电路如图19所示。
实施例5
图20表示本发明的实施例5。其为在同一芯片上形成了2个图18所示的电阻内置型双极晶体管的情况。

Claims (5)

1.一种电阻内置型双极晶体管，以第一导电型半导体衬底为发射极，以形成在上述第一导电型半导体衬底上、且形成为第一导电型半导体区围绕在其周围的第二导电型杂质区为基极，以形成在上述第二导电型基极区域的一部分上的第一导电型杂质区为集电极，以隔着绝缘层形成在上述第一导电型半导体衬底的一部分之上的半导体层为电阻，其中，上述第一导电型半导体衬底、上述第二导电型杂质区和上述第一导电型杂质区的杂质浓度，具有上述第一导电型半导体衬底＞上述第二导电型杂质区＜上述第一导电型杂质区的关系，在上述第二导电型杂质区上形成有选择性注入并扩散P型杂质而形成的P+型区域，上述第一导电型半导体衬底的杂质浓度为1×1018cm-3～1×1020cm-3，上述第二导电型杂质区的杂质浓度为2×1014cm-3～4×1016cm-3，上述P+型区域的杂质的表面浓度为1×1017cm-3～1×1020cm-3，上述电阻与上述第一导电型集电极区域连接。
2.一种电阻内置型双极晶体管，以第一导电型半导体衬底为发射极，以形成在上述第一导电型半导体衬底上、且形成为第一导电型半导体区围绕在其周围的第二导电型杂质区为基极，以形成在上述第二导电型基极区域的一部分上的第一导电型杂质区为集电极，以隔着绝缘层形成在上述第一导电型半导体衬底的一部分之上的半导体层为电阻，其中，上述第一导电型半导体衬底、上述第二导电型杂质区和上述第一导电型杂质区的杂质浓度，具有上述第一导电型半导体衬底＞上述第二导电型杂质区＜上述第一导电型杂质区的关系，在上述第二导电型杂质区上形成有选择性注入并扩散P型杂质而形成的P+型区域，上述第一导电型半导体衬底的杂质浓度为1×1018cm-3～1×1020cm-3，上述第二导电型杂质区的杂质浓度为2×1014cm-3～4×1016cm-3，上述P+型区域的杂质的表面浓度为1×1017cm-3～1×1020cm-3，上述电阻与上述第二导电型基极区域连接。
3.一种电阻内置型双极晶体管，以第一导电型半导体衬底为发射极，以形成在上述第一导电型半导体衬底上、且形成为第一导电型半导体区围绕在其周围的第二导电型杂质区为基极，以形成在上述第二导电型基极区域的一部分上的第一导电型杂质区为集电极，以隔着绝缘层形成在上述第一导电型半导体衬底的一部分之上的半导体层为电阻，其中，上述第一导电型半导体衬底、上述第二导电型杂质区和上述第一导电型杂质区的杂质浓度，具有上述第一导电型半导体衬底＞上述第二导电型杂质区＜上述第一导电型杂质区的关系，在上述第二导电型杂质区上形成有选择性注入并扩散P型杂质而形成的P+型区域，上述第一导电型半导体衬底的杂质浓度为1×1018cm-3～1×1020cm-3，上述第二导电型杂质区的杂质浓度为2×1014cm-3～4×1016cm-3，上述P+型区域的杂质的表面浓度为1×1017cm-3～1×1020cm-3，上述电阻并联连接在上述第一导电型半导体衬底和上述第二导电型基极区域之间。
4.根据权利要求3所述的电阻内置型双极晶体管，其特征在于，上述第二导电型基极区域还串联连接有电阻。
5.一种电阻内置型双极晶体管，其特征在于，在同一第一导电型半导体衬底上，配置有多个以上述半导体衬底为发射极的上述权利要求1、2、3或4所述的电阻内置型双极晶体管。
CNB2004800424732A 2004-04-02 2004-09-22 电阻内置型双极晶体管 Expired - Fee Related CN100444401C (zh)

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