WO2005099304A1 - 音量制御回路、半導体集積回路および音源機器 - Google Patents
音量制御回路、半導体集積回路および音源機器 Download PDFInfo
- Publication number
- WO2005099304A1 WO2005099304A1 PCT/JP2005/006620 JP2005006620W WO2005099304A1 WO 2005099304 A1 WO2005099304 A1 WO 2005099304A1 JP 2005006620 W JP2005006620 W JP 2005006620W WO 2005099304 A1 WO2005099304 A1 WO 2005099304A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- signal
- volume
- control circuit
- circuit
- output
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims description 4
- 238000005070 sampling Methods 0.000 claims abstract description 17
- 230000009467 reduction Effects 0.000 claims description 13
- 238000011946 reduction process Methods 0.000 claims description 12
- 230000005236 sound signal Effects 0.000 claims description 9
- 238000000034 method Methods 0.000 abstract description 6
- 230000008569 process Effects 0.000 abstract description 3
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 8
- 230000000694 effects Effects 0.000 description 5
- 230000008859 change Effects 0.000 description 4
- 230000002238 attenuated effect Effects 0.000 description 2
- 238000013016 damping Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 241000406668 Loxodonta cyclotis Species 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004590 computer program Methods 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
- H04R29/00—Monitoring arrangements; Testing arrangements
- H04R29/001—Monitoring arrangements; Testing arrangements for loudspeakers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/002—Control of digital or coded signals
Definitions
- volume control circuit semiconductor integrated circuit and sound source device
- the present invention relates to a volume control technique, and more particularly to a volume control circuit that reduces the volume of a signal to be processed as an input signal and outputs the reduced signal, a semiconductor integrated circuit, and a sound source device.
- Patent Document 1 discloses an automatic volume control device provided with gain control means for avoiding this phenomenon, which is caused by a sudden change in the gain of an amplifier when an analog switch is turned on and off, which causes a decrease in sound quality.
- Patent Document 1 JP-A-8-139395
- Patent Document 1 the gain is gradually increased when the level of the received audio signal falls below the standard value, so that the volume can be adjusted without a sense of discomfort in hearing.
- a similar problem occurs when such a steady volume adjustment alone causes the sound to be completely dropped. In other words, if the sound is interrupted at the same time as the switch-off, a great discomfort may be heard.
- the present invention has been made in view of such a situation, and an object of the present invention is to provide a sound volume control technique for obtaining a natural audible effect when sound is turned off.
- a volume control circuit includes: a volume circuit that reduces the volume of a signal to be processed and generates an output signal after an output stop command is issued; A setting circuit for setting the amount of reduction in a single reduction process when reducing the volume of the elephant signal, and a control circuit for increasing the number of reduction processes while reducing the volume of the signal to be processed in the volume circuit. including. According to this configuration, since the number of times of reduction processing gradually increases, the amount of reduction in volume gradually increases, and a mute effect that is natural in terms of audibility can be obtained.
- the control circuit may include a timer. In this case, the number of times of the reduction process may be increased at a predetermined time interval measured by the timer. Further, a forcible off circuit may be provided for setting the volume to zero when a predetermined end time is reached by a timer.
- the above-described volume circuit captures a signal to be processed at a predetermined capture sampling frequency, and executes a reduction process by the number of times increased by the control circuit in a shorter time than the cycle of the capture sampling frequency. Then, an output signal may be generated.
- the processing target signal is fetched at each sampling timing, and the reduction processing is performed on the processing target signal, so that sound skipping can be prevented and the volume can be smoothly reduced.
- the sound volume control circuit of the present invention the sound volume can be naturally reduced in terms of audibility.
- FIG. 1 is a diagram showing a configuration of a sound source device according to an embodiment.
- FIG. 2 is a diagram showing a configuration of a volume control circuit according to an embodiment.
- FIG. 3 is a flowchart showing an operation of a volume control circuit.
- FIG. 1 shows an overall configuration of a sound source device 1000 including a volume control circuit 100 according to an embodiment.
- the sound source device 1000 includes a volume control circuit 100 for controlling the volume of an audio signal, and an output stop instruction generating circuit 200 for generating an audio output stop instruction.
- the volume control circuit 100 includes a signal generation circuit 12 that outputs an audio signal, a volume circuit 40 that generates an output signal by reducing the volume of a signal to be processed after an output stop command is issued, and a volume circuit 4 that outputs a signal.
- a setting circuit 50 for setting the amount of reduction in one reduction process and a volume circuit 40 for reducing the volume of the signal to be processed in the volume circuit 40.
- a control circuit 60 for increasing the number of times.
- FIG. 2 shows a configuration of a volume control circuit 100 according to the embodiment.
- the volume circuit 40 mainly includes a multiplier 16 and a first multiplexer 14, a second multiplexer 18, a first flip-flop 20, and an input capture signal generation circuit 30 placed before and after the multiplier 16.
- the setting circuit 50 mainly includes the attenuation coefficient setting register 28.
- the control circuit 60 mainly includes a multiplication number master counter 38 and a multiplication number temporary counter 32. However, any circuit may be considered to further include those peripheral circuits.
- the control circuit 60 may include the timer setting register 34 and the timer 36.
- the signal generation circuit 12 is an arbitrary circuit that outputs an audio signal, and is, for example, a sound source circuit, a codec, a DTMF circuit, or the like.
- the output signal of the signal generation circuit 12 is the processing target signal in.
- the first multiplexer 14 selects and outputs a signal to be input to either the first input terminal 0 or the second input terminal 1 according to the capture timing signal L input to the selection signal input terminal s.
- An output signal of a later-described first flip-flop 20 is provided to a first input terminal 0, and a signal to be processed in is provided to a second input terminal 1.
- the multiplier 16 multiplies the processing target signal in, which is the output signal a of the first multiplexer 14, by the output signal b of the attenuation coefficient setting register 28, and outputs a signal c as a result of the multiplication (hereinafter referred to as these).
- the three values are sometimes abbreviated as a, b, and c).
- the second multiplexer 18 selects and outputs a signal input to either the first input terminal 0 or the second input terminal 1 in accordance with the count-over signal co input to the selection signal input terminal s.
- the output signal of the first flip-flop 20 is given to the first input terminal 0, and c is given to the second input terminal 1.
- the output signal of the second multiplexer 18 is supplied to the input terminal D of the first flip-flop 20, and the clock input terminal of the first flip-flop 20 is supplied with the oversampling clock OSCK, which is the fastest clock in this system.
- the third multiplexer 22 selects and outputs a signal to be input to either the first input terminal 0 or the second input terminal 1 according to a stop command STOP input to the selection signal input terminal s.
- the stop command STOP is a command STOP for stopping the input sound.
- the first input terminal 0 is supplied with the signal to be processed in, and the second input terminal 1 is supplied with the output signal of the first flip-flop 20.
- the output signal of the third multiplexer 22 is input to the input terminal D of the second flip-flop 24.
- the third multiplexer 22 outputs the input signal of the second input terminal 1 when the stop command STOP input to the selection signal input terminal s is activated.
- the stop instruction STOP is not input to the third multiplexer 22, the output signal of the signal generation circuit 12, that is, the signal to be processed in is output to the second flip-flop 24 as it is.
- the stop command STOP is a level signal.
- the clock input terminal of the second flip-flop 24 is supplied with a sampling clock SCK of the audio processing system, and the output signal of the second flip-flop 24 is supplied to one input terminal of a mask circuit 26 which is an AND gate.
- the stop command STOP is generated by an operation such as turning off the power of a device on which the volume control circuit 100 is mounted or turning off the volume. It doesn't matter here.
- the attenuation coefficient setting register 28 holds an amount (hereinafter, “attenuation coefficient” t b) b to be reduced in one reduction process.
- the attenuation coefficient setting register 28 can be set by software. For example, if 0.8 is set as the attenuation coefficient b, this value is multiplied by the processing target signal in output from the first multiplexer 14 in the multiplier 16, and the volume is increased 0.8 times in one reduction processing. Become. The value of the damping coefficient b in the damping coefficient setting register 28 does not change until the software force is reset.
- the input capture signal generation circuit 30 generates a capture timing signal L for capturing the signal to be processed in.
- the capture timing signal L is synchronized with a clock edge slightly delayed in phase of the sampling clock SCK as described later.
- This fetch timing signal L is applied to the first multiplexer 14 and the multiplication number temporary counter 32.
- the first multiplexer 14 When the capture timing signal L is asserted, the input signal of the second input terminal 1 is selected, and the processing target signal in is input to the multiplier 16. At other timings, the first multiplexer 14 selects the input signal of the first input terminal 0, and the signal to be processed “in” already input is repeatedly input to the multiplier 16. Such an operation realizes a plurality of reduction processes by a plurality of multiplications.
- the multiplication number temporary counter 32 loads the output signal of the multiplication number master counter 38 when the capture timing signal L is asserted.
- the multiplication count temporary counter 32 is a down counter.Each time the rising edge of the oversampling clock OSCK is input, the internal value is decremented, and after the value becomes zero, the count is over until the next count operation is started. Actively assert signal co.
- This count-over signal co is input to the selection signal input terminal s of the second multiplexer 18.
- the second multiplexer 18 selects the signal input to the first input terminal 0 while the count-over signal co is active, and as a result, the signal is looped by the first flip-flop 20 and the second multiplexer 18, and the volume is reduced. The reduction process is skipped, and the volume becomes constant.
- the multiplication count master counter 38 sets how many times the reduction processing is repeated for the fetched processing target signal in.
- the multiplication count master counter 38 is an up counter, and the internal value is incremented every time a predetermined time elapses in the timer 36.
- the software time is also set in the timer setting register 34 for the predetermined time, and the timer 36 is controlled by the output signal of the timer setting register 34.
- the multiplication count master counter 38 also receives a stop command STOP. During this stop command STOP force inactive, that is, during normal operation, the multiplication count master counter 38 is in a fixed state. At this time, in the present embodiment, it is assumed that the value inside the multiplication number master counter 38 is fixed at “1”. When the stop command STOP becomes active, the multiplication count master counter 38 counts up every time a predetermined time elapses with the timer 36, and the value of the multiplication count master counter 38 at that time is incremented by the fetch timing signal L. Loaded into Here, it is assumed that the cycle of the output signal of the timer 36 is sufficiently longer than the cycle of the fetch timing signal L.
- the value output to the multiplication count temporary counter 32 is “1” when the acquisition timing signal L is asserted as a reference. "1" ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ . .
- the count over signal co of the multiplication number temporary counter 32 is based on the oversampling clock OSCK.
- the processing target signal “in” passes through the multiplier 16 three times as described later, and the sound volume becomes three times the original b.
- the multiplication count master counter 38 determines that the volume has been sufficiently reduced, and thereafter sets a low mask signal for reducing the volume to zero. Output with. This signal is input to the mask circuit 26.
- the mask circuit 26 is a forced off circuit for setting the volume to zero.
- Stop command STOP power During normal operation in which the signal is inactive, the third multiplexer 22 selects the signal to be processed in from the signal generation circuit 12 and the second flip-flop 24 selects the sampling clock which is the basic clock of the audio processing system. It is sampled by the clock SCK and is output as an output signal out through the mask circuit 26. During this time, the signal to be processed in is input from the first multiplexer 14 to the multiplier 16 every time the fetch timing signal L is asserted, and the multiplication process continues.
- the third multiplexer 22 switches, and the output signal of the first flip-flop 20 is transmitted to the second flip-flop 24.
- the oversampling clock OSCK should be a signal sufficiently faster than the sampling clock SCK.
- these clocks and the basic clock of the timer 36 have a predetermined synchronization relationship and a phase correlation, and the clock tracing is performed at the time of circuit switching and signal latching. And hazards should be considered.
- FIG. 3 is a timing chart showing the above operation.
- one cycle of the oversampling clock OSCK is defined as t.
- the capture timing signal L is obtained by slightly delaying the sampling clock SCK.
- the stop command STOP has already been activated, and the timer 36 has once counted a predetermined time and the state of the multiplication master counter 38 has reached "2".
- the value of the multiplication number master counter 38 at that time, “2”, is loaded into the multiplication number temporary counter 32.
- the output signal is gradually narrowed down, and after a certain period of time, is finally cut off completely by the mask circuit 26.
- sound output is stopped. After the command to stop is issued, the volume can be gradually lowered, which is natural for the sense of hearing.
- the volume is reduced logarithmically, but the manner of lowering the volume is not limited thereto.
- the value of the attenuation coefficient set in the attenuation coefficient setting register 28 can be changed.
- a number X less than 1 and a number Y greater than 1 are alternately set in the attenuation coefficient setting register 28, such as “0.7” and “1.1”.
- the volume can be gradually reduced while making the sound undulate, and a special effect can be realized.
- various effects can be realized by controlling the attenuation coefficient to be set.
- the volume control circuit 100 is considered to be mounted on the mobile device, but the present invention is not limited to this. Any device may be used as long as it has a mechanism for outputting sound.
- the present invention can be used for a wireless mono device, mainly a portable phone, and other audio output devices.
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- Health & Medical Sciences (AREA)
- General Health & Medical Sciences (AREA)
- Otolaryngology (AREA)
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Acoustics & Sound (AREA)
- Signal Processing (AREA)
- Control Of Amplification And Gain Control (AREA)
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006512071A JP4751321B2 (ja) | 2004-04-06 | 2005-04-04 | 音量制御回路、半導体集積回路および音源機器 |
CN2005800107347A CN1939089B (zh) | 2004-04-06 | 2005-04-04 | 音量控制电路、半导体集成电路及声源设备 |
EP05728868A EP1744588A1 (en) | 2004-04-06 | 2005-04-04 | Sound volume control circuit, semiconductor integrated circuit, and sound source device |
US11/547,601 US20070211910A1 (en) | 2004-04-06 | 2005-04-04 | Sound Volume Control Circuit, Semiconductor Integrated Circuit And Sound Source Device |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004-111959 | 2004-04-06 | ||
JP2004111959 | 2004-04-06 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2005099304A1 true WO2005099304A1 (ja) | 2005-10-20 |
Family
ID=35125472
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2005/006620 WO2005099304A1 (ja) | 2004-04-06 | 2005-04-04 | 音量制御回路、半導体集積回路および音源機器 |
Country Status (6)
Country | Link |
---|---|
US (1) | US20070211910A1 (ja) |
EP (1) | EP1744588A1 (ja) |
JP (1) | JP4751321B2 (ja) |
CN (1) | CN1939089B (ja) |
TW (1) | TW200618462A (ja) |
WO (1) | WO2005099304A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2008032209A3 (en) * | 2006-09-14 | 2008-07-24 | Lg Electronics Inc | Controller and user interface for dialogue enhancement techniques |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0742101U (ja) * | 1993-12-27 | 1995-07-21 | アイワ株式会社 | 電子式ボリュームの制御回路 |
JP2000013157A (ja) * | 1998-06-18 | 2000-01-14 | Fujitsu Ten Ltd | 音響機器の音量制御装置 |
JP2000102088A (ja) * | 1998-09-25 | 2000-04-07 | Pioneer Electronic Corp | オーディオシステム |
JP2000315925A (ja) * | 1999-04-28 | 2000-11-14 | Clarion Co Ltd | 音響機器の音量制御装置 |
JP2001257548A (ja) * | 2000-03-10 | 2001-09-21 | Matsushita Electric Ind Co Ltd | 音量制御方法 |
JP2002353757A (ja) * | 2001-05-30 | 2002-12-06 | Victor Co Of Japan Ltd | 自動音量制御装置 |
JP2003173612A (ja) * | 2001-11-30 | 2003-06-20 | Sharp Corp | 音量制御装置 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6095721U (ja) * | 1983-12-07 | 1985-06-29 | パイオニア株式会社 | 電子ボリユ−ム回路 |
US5150415A (en) * | 1989-05-01 | 1992-09-22 | Motorola, Inc. | Volume control circuit using pulse modulation |
DE19630395C1 (de) * | 1996-07-26 | 1997-10-02 | Sgs Thomson Microelectronics | Elektrische Stummsteuerschaltung |
JPH0923123A (ja) * | 1996-08-02 | 1997-01-21 | Sony Corp | デジタルオーディオ信号の減衰装置 |
US6216052B1 (en) * | 1996-10-23 | 2001-04-10 | Advanced Micro Devices, Inc. | Noise elimination in a USB codec |
JP2002006070A (ja) * | 2000-06-20 | 2002-01-09 | Funai Electric Co Ltd | 電子装置 |
GB2409389B (en) * | 2003-12-09 | 2005-10-05 | Wolfson Ltd | Signal processors and associated methods |
JP4241443B2 (ja) * | 2004-03-10 | 2009-03-18 | ソニー株式会社 | 音声信号処理装置、音声信号処理方法 |
-
2005
- 2005-04-04 EP EP05728868A patent/EP1744588A1/en not_active Withdrawn
- 2005-04-04 WO PCT/JP2005/006620 patent/WO2005099304A1/ja active Application Filing
- 2005-04-04 JP JP2006512071A patent/JP4751321B2/ja not_active Expired - Fee Related
- 2005-04-04 US US11/547,601 patent/US20070211910A1/en not_active Abandoned
- 2005-04-04 CN CN2005800107347A patent/CN1939089B/zh not_active Expired - Fee Related
- 2005-04-06 TW TW094110875A patent/TW200618462A/zh unknown
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0742101U (ja) * | 1993-12-27 | 1995-07-21 | アイワ株式会社 | 電子式ボリュームの制御回路 |
JP2000013157A (ja) * | 1998-06-18 | 2000-01-14 | Fujitsu Ten Ltd | 音響機器の音量制御装置 |
JP2000102088A (ja) * | 1998-09-25 | 2000-04-07 | Pioneer Electronic Corp | オーディオシステム |
JP2000315925A (ja) * | 1999-04-28 | 2000-11-14 | Clarion Co Ltd | 音響機器の音量制御装置 |
JP2001257548A (ja) * | 2000-03-10 | 2001-09-21 | Matsushita Electric Ind Co Ltd | 音量制御方法 |
JP2002353757A (ja) * | 2001-05-30 | 2002-12-06 | Victor Co Of Japan Ltd | 自動音量制御装置 |
JP2003173612A (ja) * | 2001-11-30 | 2003-06-20 | Sharp Corp | 音量制御装置 |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2008032209A3 (en) * | 2006-09-14 | 2008-07-24 | Lg Electronics Inc | Controller and user interface for dialogue enhancement techniques |
KR101061415B1 (ko) | 2006-09-14 | 2011-09-01 | 엘지전자 주식회사 | 다이알로그 증폭 기술을 위한 컨트롤러 및 사용자 인터페이스 |
US8184834B2 (en) | 2006-09-14 | 2012-05-22 | Lg Electronics Inc. | Controller and user interface for dialogue enhancement techniques |
US8238560B2 (en) | 2006-09-14 | 2012-08-07 | Lg Electronics Inc. | Dialogue enhancements techniques |
US8275610B2 (en) | 2006-09-14 | 2012-09-25 | Lg Electronics Inc. | Dialogue enhancement techniques |
Also Published As
Publication number | Publication date |
---|---|
EP1744588A1 (en) | 2007-01-17 |
JP4751321B2 (ja) | 2011-08-17 |
JPWO2005099304A1 (ja) | 2008-03-06 |
US20070211910A1 (en) | 2007-09-13 |
TW200618462A (en) | 2006-06-01 |
CN1939089B (zh) | 2011-01-12 |
CN1939089A (zh) | 2007-03-28 |
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