Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
  • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
  • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/67—Thin-film transistors [TFT]
  • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
  • H10D30/6708—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device for preventing the kink effect or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
  • H10D30/6711—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device for preventing the kink effect or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect by using electrodes contacting the supplementary regions or layers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/67—Thin-film transistors [TFT]
  • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
  • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/67—Thin-film transistors [TFT]
  • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
  • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
  • H10D30/6743—Silicon

Definitions

• the present disclosure relates generally to semiconductor devices, and more particularly, to a method and apparatus for forming an SOI body-contacted transistor.
• Body-contacted SOI transistors are typically built with a polysilicon gate separating the source/drain regions from the body contact region.
• the additional circuit loading capacitance due to this body-tie gate is substantial, especially for high-performance technologies that use reticle enhancement techniques such as complementary phase-shift masks to reduce the main transistor gate length. Such techniques are unable to reduce the size of the body-tie region or capacitance.
• FIG. 1 is a layout view of a typical SOI body-contacted transistor 10.
• SOI body- contacted transistor 10 includes an active transistor region 12, wherein active transistor region 12 includes a portion thereof for use as a body tie contact region, as indicated by reference numeral 14.
• An intrinsic body region, proximate a center of the active transistor region 12, includes a width dimension 16, designated as "Wi,” and a length dimension 18, designated as "Li.”
• SOI body-contacted transistor 10 further includes a gate polysilicon 24 overlying the active transistor region 12.
• the gate polysilicon 24 further includes a portion 26 thereof that overlies a portion of the body tie contact region 14 corresponding to the extrinsic body region.
• SOI body-contacted transistor 10 still further includes a source suicide 28, drain suicide 30, and body tie contact region suicide 32.
• the structure of transistor 10 includes implant regions, designated by reference numerals 34 and 36. In one embodiment, the implant regions 34 and 36 correspond to N++ and P++ implant regions, respectively. Contacts 38, 40, 42, and 44 provide electrical connection to the gate, source, drain, and body tie regions, respectively.
• FIG. 2 is a cross-sectional view 50 of the typical SOI body-contacted transistor 10 of Figure 1, taken along line 2-2.
• Transistor 10 includes an insulator 52, trench isolation 54, intrinsic body of the active region 56, extrinsic body tie access region 58, and body tie diffusion 60.
• intrinsic body of the active region 56 includes a P type region
• extrinsic body tie access region 58 includes a P- type region
• body tie diffusion 60 includes a P++ region.
• a depleted portion of the extrinsic body tie access region designated by reference numeral 62, is formed within the extrinsic body tie access region 58.
• the depleted portion of the extrinsic body tie access region causes a higher body tie resistance condition, resulting in a degraded body tie efficiency.
• a thin gate oxide 64 overlies the active transistor region 12 in an area underlying gate polysilicon 66.
• Gate polysilicon 66 includes an N++ portion 68 and a P++ portion 70, resulting from N++ and P++ implantations in regions 34 and 36, repectively, after sidewall spacer formation.
• Sidewall spacers 72 are formed at end regions of the gate polysilicon 66.
• Silicidation forms suicides 24 and 32.
• an interlevel dielectric ILDo indicated by reference numeral 74, is formed overlying the transistor structure, followed by formation of contacts 38 and 44.
• a method for forming a silicon-on-insulator transistor includes forming an active region overlying an insulating layer, wherein a portion of the active region provides an intrinsic body region.
• a body tie access region is also formed within the active region, overlying the insulating layer and laterally disposed adjacent the intrinsic body region, making electrical contact to the intrinsic body region.
• a gate electrode is formed overlying the intrinsic body region for providing electrical control of the intrinsic body region, the gate electrode extending over a portion of the body tie access region.
• the gate electrode is formed having a substantially constant gate length along its entire width overlying the active region, with a portion overlying the body tie access region having a gate length substantially smaller than L , to minimize parasitic capacitance and gate electrode leakage.
• First and second current electrodes are formed adjacent opposite sides of the intrinsic body region.
• a body tie diffusion is formed within the active region and laterally offset from the body tie access region and electrically coupled to the body tie access region.
• Figure 1 is a layout view of a typical SOI body-contacted transistor (PRIOR ART);
• Figure 2 is a cross-sectional view of the typical SOI body-contacted transistor of Figure 1, taken along line 2-2 (PRIOR ART);
• Figure 3 is a layout view of a novel SOI body-contacted transistor according to an embodiment of the present disclosure.
• Figure 4 is a cross-sectional view of the SOI body-contacted transistor of Figure 3, taken along line 4-4;
• Figure 5 is a cross-sectional view of the SOI body-contacted transistor of Figure 3, taken along line 5-5;
• Figure 6 is a cross-sectional view of the SOI body-contacted transistor of Figure 3, taken along line 6-6;
• Figure 7 is a cross-sectional view of the SOI body-contacted transistor of Figure 3, taken along line 7-7;
• Figure 8 is a cross-sectional view of the SOI body-contacted transistor of Figure 3, taken along line 8-8;
• Figure 9 is a cross-sectional view of the SOI body-contacted transistor of Figure 3, taken along line 9-9;
• Figure 10 is a flow diagram view of a method for fabricating the SOI body- contacted transistor according to an embodiment of the present disclosure.
• FIG 3 is a layout view of a novel SOI body-contacted transistor 80 according to an embodiment of the present disclosure.
• SOI body-contacted transistor 80 includes an active transistor region 82, wherein active transistor region 82 includes a portion thereof for use as a body tie contact region, as indicated by reference numeral 84.
• This region corresponds to a body tie access region and is designated by reference numeral 128 in Figures 3 and 4.
• SOI body-contacted transistor 80 further includes a gate polysilicon 94 overlying the active transistor region 82.
• the gate polysilicon 94 further includes a portion 96 thereof that overlies a portion of the body tie contact region 84 corresponding to the extrinsic body tie access region 128 ( Figure 4). Note that the portion 96 of the gate polysilicon that overlies the portion of the body tie contact region 84, and more particularly, the body tie access region 128 of the body tie contact region 84, has a length dimension that is substantially smaller than the length dimension of the body tie contact region 84 (in one embodiment, Li « L 2 ).
• SOI body-contacted transistor 80 still further includes a source silicide 98, drain silicide 100, and body tie contact region silicide 102.
• the structure of transistor 80 includes implant regions, designated by reference numerals 104 and 106.
• the implant regions 104 and 106 correspond to N++ and P++ implant regions, respectively.
• Contacts 108, 110, 112, and 114 provide electrical connection to the gate, source, drain, and body tie regions, respectively.
• FIG. 4 is a cross-sectional view 120 of the SOI body-contacted transistor 80 of Figure 3, taken along line 4-4.
• Transistor 80 includes an insulator 122, trench isolation 124, an intrinsic body 126 of the active region 82, a body tie access region 128 of the active region 82, and a body tie diffusion 130 of the active region 82.
• the intrinsic body 126 of the active region 82 includes a P type region
• body tie access region 128 includes a P+ type region
• body tie diffusion 130 includes a P++ region.
• a depleted portion of an extrinsic body tie access region designated by reference numeral 131, is formed within the body tie access region 128.
• the depleted portion 131 of the body tie access region 128 is minimized, thereby substantially reducing body tie access resistance and resulting in substantially improved body tie efficiency.
• a thin gate oxide 132 overlies the active transistor region 82 in an area underlying gate polysilicon 134.
• Gate polysilicon 134 includes an N++ suicided portion 136 and an unsilicided portion 137, resulting from N++ implantation in region 104, after sidewall spacer formation.
• Sidewall spacers (138,140) are formed at end regions of the gate polysilicon 134.
• sidewall spacers (138,140) include a dielectric.
• the dielectric can include a silicon oxide, nitride, or other suitable dielectric. Subsequent silicidation forms suicides 94 and 102.
• sidewall spacer 140 prevents a silicidation of a portion of the gate polysilicon 134 underlying a portion of the spacer 140.
• an interlevel dielectric ILDo is formed overlying the transistor structure, followed by formation of contacts 108 and 114.
• sidewall spacer 140 extends across the active region 82, in particular, the body tie access region 128, that corresponds to width W 2 designated by reference numeral 90 in Figure 3. Furthermore, sidewall spacer 140 forms a hard mask having dimensions as outlined by dashed line designated by reference numeral 144 ( Figure 3), wherein a first dimension is on the order of W 2 , designated by reference numeral 90 and a second dimension is on the order of greater than L 2 , designated by reference numeral 92. In the second dimension, the hard mask overlies trench isolation 124 and the body tie access region 128.
• FIG. 5 is a cross-sectional view 150 of the SOI body-contacted transistor 80 of Figure 3, taken along line 5-5.
• transistor 80 includes an insulator 122, trench isolation 124, and an active region 82.
• Transistor 80 further includes a drain region 152 of active region 82, a body tie access region 128 of the active region 82, and a body tie diffusion 130 of the active region 82.
• the drain region 152 includes an N++ type region
• body tie access region 128 includes a P+ type region
• body tie diffusion 130 includes a P++ region.
• a portion of sidewall spacer 140 overlies the body tie access region 128 along line 5-5 of Figure 3.
• silicidation also forms silicide 100. Note that sidewall spacer 140 inhibits a silicidation of the active region 82 underlying the spacer 140.
• FIG. 6 is a cross-sectional view 160 of the SOI body-contacted transistor 80 of Figure 3, taken along line 6-6.
• transistor 80 includes an insulator 122, trench isolation 124, and an active region 82.
• Transistor 80 further includes an intrinsic body region 126, a drain region 152 of active region 82, and a source region 154 of active region 82.
• the drain and source regions 152 and 154 respectively, include N++ type regions.
• the gate polysilicon 136 includes an N++ type gate polysilicon and sidewall spacers 138 overlying gate oxide 132. In addition to silicide 100, silicidation also forms suicides 94 and 98.
• FIG. 7 is a cross-sectional view 170 of the SOI body-contacted transistor 80 of Figure 3, taken along line 7-7.
• transistor 80 includes an insulator 122, trench isolation 124, an active region 82, and a body tie access region 128 of active region 82.
• the body tie access region 128 includes a P+ type region.
• the unsilicided portion of gate polysilicon 137 and sidewall spacer 140 overlie gate oxide 132, wherein sidewall spacer 140 also overlies a portion of trench isolation 124. Note that sidewall spacer 140 inhibits a silicidation of the active region 82 underlying the spacer 140.
• Figure 8 is a cross-sectional view 180 of the SOI body-contacted transistor 80 of Figure 3, taken along line 8-8.
• transistor 80 includes an insulator 122, trench isolation 124, an active region 82, and a body tie access region 128 of active region 82.
• the body tie access region 128 includes a P+ type region.
• sidewall spacer 140 overlies gate oxide 132 and a portion of trench isolation 124. Note that sidewall spacer 140 inhibits a silicidation of the active region 82 underlying the spacer 140.
• Figure 9 is a cross-sectional view 190 of the SOI body-contacted transistor 80 of Figure 3, taken along line 9-9.
• transistor 80 includes an insulator 122, trench isolation 124, an active region 82, and body tie diffusion 130 of active region 82.
• body tie diffusion 130 includes a P++ region. Silicidation forms silicide 102 on the body tie diffusion 130.
• FIG 10 is a flow diagram view 200 of a method for fabricating the SOI body- contacted transistor according to an embodiment of the present disclosure.
• the method begins by providing an SOI substrate.
• an active region is defined (or active regions defined).
• step 206 perform an intrinsic body implant or implants.
• step 208 form an open mask over an intrinsic body tie region through mask Boolean and perform additional body access region implant(s).
• step 210 form gate oxide(s), deposit and pattern gate electrode(s).
• step 211 mask the body tie access region and perform halo/extension implant(s) (also referred to as pocket implant(s)).
• step 213 mask body tie access region(s) and perform sidewall spacer etch(es).
• step 214 perform source/drain implant(s).
• step 216 deposit and form silicide region(s).
• step 218, continue with interlevel dielectric ILDo deposition and further processing according to the semiconductor IC flow.
• a silicon-on-insulator transistor 80 includes an insulating layer 122 and an active region 82 overlying the insulating layer.
• the active region 82 includes an intrinsic body region 126 and a body tie access region 128, the body tie access region also overlying the insulating layer 122 and being laterally adjacent the intrinsic body region 126.
• the body tie access region 128 provides for making electrical contact to the intrinsic body region 126.
• the SOI transistor 80 further includes a body tie diffusion 130 laterally offset from the body tie access region 128 and electrically coupled to the body tie access region 128.
• Transistor 80 further includes a gate electrode 134.
• the gate electrode 134 overlies the intrinsic body region 126 for providing electrical control of the intrinsic body region 126 of the silicon-on-insulator transistor 80 and extends over a portion 137 of the body tie access region 128.
• the gate electrode 134 has a substantially constant gate length 88 along its entire width, wherein different portions of the gate electrode overlie the body tie access region 128 and the intrinsic body region 126.
• first and second current electrodes (98,100) are provided adjacent opposite sides of the intrinsic body region 126.
• the gate electrode 134 extends over only a fraction of the body tie access region 128 to minimize parasitic gate capacitance and current leakage.
• the silicon-on-insulator transistor 80 further includes a dielectric layer 140.
• the dielectric layer 140 overlies substantially all of the body tie access region 128 including the portion 137 of the gate electrode 134 that overlies the body tie access region 128.
• the dielectric layer 140 functions as a sidewall spacer (138,140) of the gate electrode 134.
• a portion of the body tie access region 128 that underlies the dielectric layer 140 comprises doped material.
• the doped material increases a doping concentration of the body tie access region 128 so as to substantially minimize formation of a depletion region 131 in the body tie access region 128.
• Doping of the portion of the body tie access region can be provided by using a pattern feature 144 in a first mask and reusing the pattern feature in a second mask to provide the dielectric layer 140.
• a method for forming a silicon-on-insulator transistor 80 includes providing an insulating layer 122 and forming an active region 82, a body tie access region 128, a gate electrode 134, first and second current electrodes (98,100), and a body tie diffusion 130 overlying the insulating layer 122.
• Forming an active region 82 includes forming the active region to overlie the insulating layer 122, wherein a portion of the active region 82 provides an intrinsic body region 126.
• Forming the body tie access region 128 includes forming a body tie access region 128 within the active region 82 and also overlying the insulating layer 122.
• Forming the gate electrode 134 includes forming a gate electrode overlying the intrinsic body region 126 for providing electrical control of the intrinsic body region 126 of the silicon-on-insulator transistor 80.
• the gate electrode 134 extends over a portion of the body tie access region 128, as indicated by reference numeral 137 in Figure 4.
• the gate electrode 134 is formed to have a substantially constant gate length Li as indicated by reference numeral 88, along its entire width overlying the intrinsic body region 126 and the body tie access region 128.
• the gate electrode 134 maximizes transistor drive current capability and minimizes parasitic capacitance and gate electrode leakage.
• the method includes minimizing parasitic gate capacitance and current leakage by not extending the gate electrode 134 over the entire body tie access region 128.
• first and second current electrodes are formed adjacent opposite sides of the intrinsic body region 126.
• a body tie diffusion 130 is formed within the active region 82 and laterally offset from the body tie access region 128. Furthermore, the body tie diffusion 130 electrically couples to the body tie access region 128.
• the method also includes forming a dielectric layer 140 overlying substantially all of the body tie access region 128, including the portion 137 of the gate electrode that overlies the body tie access region 128.
• a portion of the body tie access region 128 that underlies the dielectric layer 140 is doped to increase a doping concentration of the body tie access region 128 to substantially minimize formation of a depletion region 131 in the body tie access region.
• the doping comprises using a pattern feature 144 in a first mask as a first selective block for the doping, and reusing the pattern feature 144 in a second mask as a second selective block, wherein the pattern feature is used to define the portion of the dielectric layer denoted by reference numeral 140.
• a method of forming a silicon- on-insulator transistor includes forming an insulating substrate (202) and defining an active region 82 which defines a location of the silicon-on-insulator transistor 80.
• the active region 82 is implanted with a predetermined diffusion material to form an intrinsic body region 126 of desired doping concentration (206).
• the method further includes defining a body tie access region 128 by forming an opening in a mask overlying the active region 82, implanting the active region to form the body tie access region 128, the body tie access region having a predetermined doping concentration to minimize body tie access resistance.
• a gate oxide (132,133) is then formed overlying both the intrinsic body region 126 and the body tie access region 128.
• the method continues with the depositing and patterning of gate electrode material 134 overlying the intrinsic body region 126 and a portion of the body tie access region 128.
• a region is defined by forming an opening in a mask overlying the active region 82, performing halo/extension implants of dopants into the intrinsic body region 126, while substantially blocking the dopants from the body tie access region 128.
• Sidewall spacer dielectric material (138,140) is then formed overlying the substantially constant length gate electrode material and body tie access region 128.
• a region substantially overlying the body tie access region 128 is masked, for example, using a suitable mask having an outline as indicated by dashed lines and reference numeral 144 ( Figure 3).
• the sidewall spacer dielectric material is then removed substantially everywhere except overlying the body tie access region 128 and adjacent the substantially constant length gate electrode material.
• a source diffusion region 98, a drain diffusion region 100, and a body tie diffusion region 130 are formed.
• the method further includes forming electrical contacts to the source diffusion region (110), the drain diffusion region (112), the body tie diffusion (114) and to the substantially constant length gate electrode material (108).
• forming electrical contacts includes forming a silicide layer overlying the source diffusion region (98), the drain diffusion region (100), the body tie diffusion (102) and over the substantially constant length gate electrode material (94).
• the method still further includes defining a dimension (144) of the mask (used for masking the body tie access region) to have a minimum distance necessary to prevent dopants implanted into the source diffusion region and the drain diffusion region from also being implanted into the body tie diffusion and vice versa.
• the method includes depositing and forming a conductive material selectively overlying each of the source diffusion region, the drain diffusion region, the substantially constant length gate electrode material and the body tie diffusion region for making electrical contact thereto.
• the method includes defining a dimension of the mask to have a value substantially large enough to prevent electrical short circuiting by the silicide contacting each of the source diffusion region, the drain diffusion region, the body tie diffusion region and the substantially constant length gate electrode material.
• the gate oxide overlying the body tie access region 128 is formed to have a first thickness (132,133) that is greater than a second thickness (132) of the gate oxide overlying the intrinsic body region 126 by using the mask.
• the method further includes extending the substantially constant length gate electrode material 134 to overlie only a fraction of the body tie access region, for example, on the order of less than one-half.
• the dielectric layer 140 separates the source and drain regions from the body contact region 130, by effectively providing a silicide-block layer, and thereby minimizes the extrinsic gate capacitance and gate leakage current in the body-contact access region 128, as well as the body contact region 130.
• the shape of the dielectric layer 140 can be combined (for example, via mask Boolean operations) into a high threshold voltage (Vt) PMOS channel implant mask; thereby minimizing an extrinsic body resistance.
• the embodiments of the present disclosure advantageously provide an extension to existing high performance MOS SOI processes.
• the embodiments of the present disclosure also provide additional advantages, in particular, for the use of body-tied transistors in critical circuits that require precise control of the body terminal. With the embodiments of the present disclosure, no additional masking steps are required. Accordingly, implementation of the method of the present disclosure can be as simple as a change to a design layout.
• the present embodiments also offer various benefits that can include one or more of: 1) reduced gate capacitance and current for such transistors, driven by reduction in gate area, 2) reduced gate to body overlap capacitance and leakage current, 3) ability to couple the embodiments of the method of the present disclosure with a dual gate oxide (DGO) mask in a body-contact region to further reduce capacitance and leakage current, and 4) an ability to minimize gate length in the body-tie region will relax poly-active misalignment requirements, and/or improve mismatch between the source and drain of two transistors with the same layout, 5) provide a reduced external body resistance under the blocked gate, wherein the silicide-block process also blocks out n/p extensions and halo implants.
• DGO dual gate oxide

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