CN1890799A - 用于形成soi体接触晶体管的方法和设备 - Google Patents

用于形成soi体接触晶体管的方法和设备 Download PDF

Info

Publication number
CN1890799A
CN1890799A CNA200480036861XA CN200480036861A CN1890799A CN 1890799 A CN1890799 A CN 1890799A CN A200480036861X A CNA200480036861X A CN A200480036861XA CN 200480036861 A CN200480036861 A CN 200480036861A CN 1890799 A CN1890799 A CN 1890799A
Authority
CN
China
Prior art keywords
region
district
intrinsic
diffusion region
drawn
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CNA200480036861XA
Other languages
English (en)
Chinese (zh)
Inventor
苏里亚·维拉拉加万
杜洋
格伦·O·沃克曼
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Freescale Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Publication of CN1890799A publication Critical patent/CN1890799A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6708—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device for preventing the kink effect or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
    • H10D30/6711—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device for preventing the kink effect or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect by using electrodes contacting the supplementary regions or layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
CNA200480036861XA 2003-12-12 2004-11-12 用于形成soi体接触晶体管的方法和设备 Pending CN1890799A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/734,435 US6953738B2 (en) 2003-12-12 2003-12-12 Method and apparatus for forming an SOI body-contacted transistor
US10/734,435 2003-12-12

Publications (1)

Publication Number Publication Date
CN1890799A true CN1890799A (zh) 2007-01-03

Family

ID=34653364

Family Applications (1)

Application Number Title Priority Date Filing Date
CNA200480036861XA Pending CN1890799A (zh) 2003-12-12 2004-11-12 用于形成soi体接触晶体管的方法和设备

Country Status (7)

Country Link
US (1) US6953738B2 (enExample)
EP (1) EP1694615A4 (enExample)
JP (1) JP2007514316A (enExample)
KR (1) KR101113009B1 (enExample)
CN (1) CN1890799A (enExample)
TW (1) TWI358080B (enExample)
WO (1) WO2005060464A2 (enExample)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104103579A (zh) * 2013-04-04 2014-10-15 意法半导体公司 集成电路器件和制作技术
CN110168387A (zh) * 2016-12-14 2019-08-23 日立汽车系统株式会社 负载驱动装置
CN110998862A (zh) * 2017-08-07 2020-04-10 Towerjazz松下半导体有限公司 半导体装置

Families Citing this family (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6804502B2 (en) 2001-10-10 2004-10-12 Peregrine Semiconductor Corporation Switch circuit and method of switching radio frequency signals
WO2006002347A1 (en) 2004-06-23 2006-01-05 Peregrine Semiconductor Corporation Integrated rf front end
US7244640B2 (en) * 2004-10-19 2007-07-17 Taiwan Semiconductor Manufacturing Company, Ltd. Method for fabricating a body contact in a Finfet structure and a device including the same
USRE48965E1 (en) 2005-07-11 2022-03-08 Psemi Corporation Method and apparatus improving gate oxide reliability by controlling accumulated charge
US9653601B2 (en) 2005-07-11 2017-05-16 Peregrine Semiconductor Corporation Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink-harmonic wrinkle reduction
US7890891B2 (en) 2005-07-11 2011-02-15 Peregrine Semiconductor Corporation Method and apparatus improving gate oxide reliability by controlling accumulated charge
US8742502B2 (en) 2005-07-11 2014-06-03 Peregrine Semiconductor Corporation Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink-harmonic wrinkle reduction
US7910993B2 (en) 2005-07-11 2011-03-22 Peregrine Semiconductor Corporation Method and apparatus for use in improving linearity of MOSFET's using an accumulated charge sink
US20080076371A1 (en) 2005-07-11 2008-03-27 Alexander Dribinsky Circuit and method for controlling charge injection in radio frequency switches
US7446001B2 (en) * 2006-02-08 2008-11-04 Freescale Semiconductors, Inc. Method for forming a semiconductor-on-insulator (SOI) body-contacted device with a portion of drain region removed
US7855414B2 (en) * 2006-07-28 2010-12-21 Broadcom Corporation Semiconductor device with increased breakdown voltage
US8587062B2 (en) * 2007-03-26 2013-11-19 International Business Machines Corporation Silicon on insulator (SOI) field effect transistors (FETs) with adjacent body contacts
US7679139B2 (en) * 2007-09-11 2010-03-16 Honeywell International Inc. Non-planar silicon-on-insulator device that includes an “area-efficient” body tie
JP5417346B2 (ja) 2008-02-28 2014-02-12 ペレグリン セミコンダクター コーポレーション 集積回路素子内でキャパシタをデジタル処理で同調するときに用いられる方法及び装置
US20090236632A1 (en) * 2008-03-19 2009-09-24 Anderson Brent A Fet having high-k, vt modifying channel and gate extension devoid of high-k and/or vt modifying material, and design structure
US8410554B2 (en) * 2008-03-26 2013-04-02 International Business Machines Corporation Method, structure and design structure for customizing history effects of SOI circuits
US8420460B2 (en) 2008-03-26 2013-04-16 International Business Machines Corporation Method, structure and design structure for customizing history effects of SOI circuits
US7964467B2 (en) * 2008-03-26 2011-06-21 International Business Machines Corporation Method, structure and design structure for customizing history effects of soi circuits
US7893494B2 (en) * 2008-06-18 2011-02-22 International Business Machines Corporation Method and structure for SOI body contact FET with reduced parasitic capacitance
US7820530B2 (en) 2008-10-01 2010-10-26 Freescale Semiconductor, Inc. Efficient body contact field effect transistor with reduced body resistance
US8723260B1 (en) 2009-03-12 2014-05-13 Rf Micro Devices, Inc. Semiconductor radio frequency switch with body contact
US8680617B2 (en) * 2009-10-06 2014-03-25 International Business Machines Corporation Split level shallow trench isolation for area efficient body contacts in SOI MOSFETS
US8441071B2 (en) 2010-01-05 2013-05-14 International Business Machines Corporation Body contacted transistor with reduced parasitic capacitance
US8643107B2 (en) * 2010-01-07 2014-02-04 International Business Machines Corporation Body-tied asymmetric N-type field effect transistor
US8426917B2 (en) * 2010-01-07 2013-04-23 International Business Machines Corporation Body-tied asymmetric P-type field effect transistor
US8299519B2 (en) * 2010-01-11 2012-10-30 International Business Machines Corporation Read transistor for single poly non-volatile memory using body contacted SOI device
US8283722B2 (en) 2010-06-14 2012-10-09 Broadcom Corporation Semiconductor device having an enhanced well region
JP6006219B2 (ja) * 2010-10-20 2016-10-12 ペレグリン セミコンダクター コーポレイション 蓄積電荷シンクを用いてｍｏｓｆｅｔの線形性を改善することに使用される方法及び装置−高調波リンクルの抑制
JP5521993B2 (ja) * 2010-11-17 2014-06-18 富士通セミコンダクター株式会社 半導体装置の製造方法及び半導体装置
US9123807B2 (en) * 2010-12-28 2015-09-01 Broadcom Corporation Reduction of parasitic capacitance in a semiconductor device
US8217456B1 (en) 2011-03-11 2012-07-10 International Business Machines Corporation Low capacitance hi-K dual work function metal gate body-contacted field effect transistor
US9590674B2 (en) 2012-12-14 2017-03-07 Peregrine Semiconductor Corporation Semiconductor devices with switchable ground-body connection
US20150236748A1 (en) 2013-03-14 2015-08-20 Peregrine Semiconductor Corporation Devices and Methods for Duplexer Loss Reduction
US9406695B2 (en) 2013-11-20 2016-08-02 Peregrine Semiconductor Corporation Circuit and method for improving ESD tolerance and switching speed
US9831857B2 (en) 2015-03-11 2017-11-28 Peregrine Semiconductor Corporation Power splitter with programmable output phase shift
US9948281B2 (en) 2016-09-02 2018-04-17 Peregrine Semiconductor Corporation Positive logic digitally tunable capacitor
US10505530B2 (en) 2018-03-28 2019-12-10 Psemi Corporation Positive logic switch with selectable DC blocking circuit
US10236872B1 (en) 2018-03-28 2019-03-19 Psemi Corporation AC coupling modules for bias ladders
US10886911B2 (en) 2018-03-28 2021-01-05 Psemi Corporation Stacked FET switch bias ladders
US11476849B2 (en) 2020-01-06 2022-10-18 Psemi Corporation High power positive logic switch

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6353245B1 (en) * 1998-04-09 2002-03-05 Texas Instruments Incorporated Body-tied-to-source partially depleted SOI MOSFET
JP4614522B2 (ja) * 2000-10-25 2011-01-19 富士通セミコンダクター株式会社 半導体装置及びその製造方法
JP2002261292A (ja) * 2000-12-26 2002-09-13 Toshiba Corp 半導体装置及びその製造方法
JP4792638B2 (ja) * 2001-02-01 2011-10-12 パナソニック株式会社 半導体装置及びその製造方法
US6620656B2 (en) 2001-12-19 2003-09-16 Motorola, Inc. Method of forming body-tied silicon on insulator semiconductor device

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104103579A (zh) * 2013-04-04 2014-10-15 意法半导体公司 集成电路器件和制作技术
US9825055B2 (en) 2013-04-04 2017-11-21 Stmicroelectronics, Inc. FinFETs suitable for use in a high density SRAM cell
CN104103579B (zh) * 2013-04-04 2018-02-02 意法半导体公司 集成电路器件和制作技术
US10325927B2 (en) 2013-04-04 2019-06-18 Stmicroelectronics, Inc. Integrated circuit devices and fabrication techniques
US10937811B2 (en) 2013-04-04 2021-03-02 Stmicroelectronics, Inc. Integrated circuit devices and fabrication techniques
US11705458B2 (en) 2013-04-04 2023-07-18 Stmicroelectronics, Inc. Integrated circuit devices and fabrication techniques
US12211853B2 (en) 2013-04-04 2025-01-28 Stmicroelectronics, Inc. Integrated circuit devices and fabrication techniques
CN110168387A (zh) * 2016-12-14 2019-08-23 日立汽车系统株式会社 负载驱动装置
CN110168387B (zh) * 2016-12-14 2021-06-18 日立汽车系统株式会社 负载驱动装置
CN110998862A (zh) * 2017-08-07 2020-04-10 Towerjazz松下半导体有限公司 半导体装置

Also Published As

Publication number Publication date
EP1694615A2 (en) 2006-08-30
KR101113009B1 (ko) 2012-02-24
US20050127442A1 (en) 2005-06-16
TW200534340A (en) 2005-10-16
WO2005060464A3 (en) 2005-11-17
EP1694615A4 (en) 2009-09-23
KR20070003787A (ko) 2007-01-05
TWI358080B (en) 2012-02-11
US6953738B2 (en) 2005-10-11
WO2005060464A2 (en) 2005-07-07
JP2007514316A (ja) 2007-05-31

Similar Documents

Publication Publication Date Title
CN1890799A (zh) 用于形成soi体接触晶体管的方法和设备
US9245975B2 (en) Recessed channel insulated-gate field effect transistor with self-aligned gate and increased channel length
US7396713B2 (en) Structure and method for forming asymmetrical overlap capacitance in field effect transistors
US5583067A (en) Inverse T-gate semiconductor device with self-aligned punchthrough stops and method of fabrication
US8963227B2 (en) Semiconductor devices having a diffusion barrier layer and methods of manufacturing the same
US9368573B2 (en) Methods for manufacturing a semiconductor device
CN1641846A (zh) 一种mosfet半导体及其制造方法
CN101292340A (zh) 使用自对准沟槽隔离的减小电场dmos
US20090173998A1 (en) Semiconductor device and manufacturing method thereof
CN1523649A (zh) 双栅极场效应晶体管及其制造方法
CN119050141A (zh) 利用埋置绝缘层作为栅极介电质的高压晶体管
CN1101059C (zh) 制作半导体器件的方法
US6117739A (en) Semiconductor device with layered doped regions and methods of manufacture
CN1784774A (zh) 多厚度硅化物器件的cmos集成
CN1809920A (zh) Soi形状的结构
KR20040071742A (ko) 전기적으로 프로그램된 ｍｏｓ 트랜지스터 소스/드레인직렬 저항
KR20010060529A (ko) 반도체 소자의 트랜지스터 제조방법
US20050153498A1 (en) Method of manufacturing p-channel MOS transistor and CMOS transistor
CN1913172A (zh) 使用反向体偏压操作晶体管的方法和设备
CN118231414B (zh) Pdsoi晶体管及其制造方法
KR100311177B1 (ko) 반도체장치의 제조방법
KR101065352B1 (ko) 모스 트랜지스터 및 이의 제조 방법
JP2006120801A (ja) 半導体装置及びその製造方法
KR20010059530A (ko) 반도체소자의 트랜지스터 형성방법
US8729635B2 (en) Semiconductor device having a high stress material layer

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication