JP2007514316A - Soiボディコンタクトトランジスタを製造する方法及び装置 - Google Patents

Soiボディコンタクトトランジスタを製造する方法及び装置 Download PDF

Info

Publication number
JP2007514316A
JP2007514316A JP2006543827A JP2006543827A JP2007514316A JP 2007514316 A JP2007514316 A JP 2007514316A JP 2006543827 A JP2006543827 A JP 2006543827A JP 2006543827 A JP2006543827 A JP 2006543827A JP 2007514316 A JP2007514316 A JP 2007514316A
Authority
JP
Japan
Prior art keywords
region
coupled
gate electrode
forming
access region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2006543827A
Other languages
English (en)
Japanese (ja)
Other versions
JP2007514316A5 (enExample
Inventor
バーララガーバン、スーリヤ
ドゥ、ヤン
オー. ワークマン、グレン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
NXP USA Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP USA Inc filed Critical NXP USA Inc
Publication of JP2007514316A publication Critical patent/JP2007514316A/ja
Publication of JP2007514316A5 publication Critical patent/JP2007514316A5/ja
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/6704Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6708Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device for preventing the kink effect or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
    • H10D30/6711Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device for preventing the kink effect or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect by using electrodes contacting the supplementary regions or layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/6729Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/674Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743Silicon

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
JP2006543827A 2003-12-12 2004-11-12 Soiボディコンタクトトランジスタを製造する方法及び装置 Pending JP2007514316A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/734,435 US6953738B2 (en) 2003-12-12 2003-12-12 Method and apparatus for forming an SOI body-contacted transistor
PCT/US2004/037760 WO2005060464A2 (en) 2003-12-12 2004-11-12 Method and apparatus for forming an soi body-contacted transistor

Publications (2)

Publication Number Publication Date
JP2007514316A true JP2007514316A (ja) 2007-05-31
JP2007514316A5 JP2007514316A5 (enExample) 2007-12-27

Family

ID=34653364

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006543827A Pending JP2007514316A (ja) 2003-12-12 2004-11-12 Soiボディコンタクトトランジスタを製造する方法及び装置

Country Status (7)

Country Link
US (1) US6953738B2 (enExample)
EP (1) EP1694615A4 (enExample)
JP (1) JP2007514316A (enExample)
KR (1) KR101113009B1 (enExample)
CN (1) CN1890799A (enExample)
TW (1) TWI358080B (enExample)
WO (1) WO2005060464A2 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010004006A (ja) * 2008-06-18 2010-01-07 Internatl Business Mach Corp <Ibm> 寄生容量が低減されたsoiボディ・コンタクト型fetのための方法及び構造体

Families Citing this family (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6804502B2 (en) 2001-10-10 2004-10-12 Peregrine Semiconductor Corporation Switch circuit and method of switching radio frequency signals
WO2006002347A1 (en) 2004-06-23 2006-01-05 Peregrine Semiconductor Corporation Integrated rf front end
US7244640B2 (en) * 2004-10-19 2007-07-17 Taiwan Semiconductor Manufacturing Company, Ltd. Method for fabricating a body contact in a Finfet structure and a device including the same
USRE48965E1 (en) 2005-07-11 2022-03-08 Psemi Corporation Method and apparatus improving gate oxide reliability by controlling accumulated charge
US9653601B2 (en) 2005-07-11 2017-05-16 Peregrine Semiconductor Corporation Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink-harmonic wrinkle reduction
US7890891B2 (en) 2005-07-11 2011-02-15 Peregrine Semiconductor Corporation Method and apparatus improving gate oxide reliability by controlling accumulated charge
US8742502B2 (en) 2005-07-11 2014-06-03 Peregrine Semiconductor Corporation Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink-harmonic wrinkle reduction
US7910993B2 (en) 2005-07-11 2011-03-22 Peregrine Semiconductor Corporation Method and apparatus for use in improving linearity of MOSFET's using an accumulated charge sink
US20080076371A1 (en) 2005-07-11 2008-03-27 Alexander Dribinsky Circuit and method for controlling charge injection in radio frequency switches
US7446001B2 (en) * 2006-02-08 2008-11-04 Freescale Semiconductors, Inc. Method for forming a semiconductor-on-insulator (SOI) body-contacted device with a portion of drain region removed
US7855414B2 (en) * 2006-07-28 2010-12-21 Broadcom Corporation Semiconductor device with increased breakdown voltage
US8587062B2 (en) * 2007-03-26 2013-11-19 International Business Machines Corporation Silicon on insulator (SOI) field effect transistors (FETs) with adjacent body contacts
US7679139B2 (en) * 2007-09-11 2010-03-16 Honeywell International Inc. Non-planar silicon-on-insulator device that includes an “area-efficient” body tie
JP5417346B2 (ja) 2008-02-28 2014-02-12 ペレグリン セミコンダクター コーポレーション 集積回路素子内でキャパシタをデジタル処理で同調するときに用いられる方法及び装置
US20090236632A1 (en) * 2008-03-19 2009-09-24 Anderson Brent A Fet having high-k, vt modifying channel and gate extension devoid of high-k and/or vt modifying material, and design structure
US8410554B2 (en) * 2008-03-26 2013-04-02 International Business Machines Corporation Method, structure and design structure for customizing history effects of SOI circuits
US8420460B2 (en) 2008-03-26 2013-04-16 International Business Machines Corporation Method, structure and design structure for customizing history effects of SOI circuits
US7964467B2 (en) * 2008-03-26 2011-06-21 International Business Machines Corporation Method, structure and design structure for customizing history effects of soi circuits
US7820530B2 (en) 2008-10-01 2010-10-26 Freescale Semiconductor, Inc. Efficient body contact field effect transistor with reduced body resistance
US8723260B1 (en) 2009-03-12 2014-05-13 Rf Micro Devices, Inc. Semiconductor radio frequency switch with body contact
US8680617B2 (en) * 2009-10-06 2014-03-25 International Business Machines Corporation Split level shallow trench isolation for area efficient body contacts in SOI MOSFETS
US8441071B2 (en) 2010-01-05 2013-05-14 International Business Machines Corporation Body contacted transistor with reduced parasitic capacitance
US8643107B2 (en) * 2010-01-07 2014-02-04 International Business Machines Corporation Body-tied asymmetric N-type field effect transistor
US8426917B2 (en) * 2010-01-07 2013-04-23 International Business Machines Corporation Body-tied asymmetric P-type field effect transistor
US8299519B2 (en) * 2010-01-11 2012-10-30 International Business Machines Corporation Read transistor for single poly non-volatile memory using body contacted SOI device
US8283722B2 (en) 2010-06-14 2012-10-09 Broadcom Corporation Semiconductor device having an enhanced well region
JP6006219B2 (ja) * 2010-10-20 2016-10-12 ペレグリン セミコンダクター コーポレイション 蓄積電荷シンクを用いてmosfetの線形性を改善することに使用される方法及び装置−高調波リンクルの抑制
JP5521993B2 (ja) * 2010-11-17 2014-06-18 富士通セミコンダクター株式会社 半導体装置の製造方法及び半導体装置
US9123807B2 (en) * 2010-12-28 2015-09-01 Broadcom Corporation Reduction of parasitic capacitance in a semiconductor device
US8217456B1 (en) 2011-03-11 2012-07-10 International Business Machines Corporation Low capacitance hi-K dual work function metal gate body-contacted field effect transistor
US9590674B2 (en) 2012-12-14 2017-03-07 Peregrine Semiconductor Corporation Semiconductor devices with switchable ground-body connection
US20150236748A1 (en) 2013-03-14 2015-08-20 Peregrine Semiconductor Corporation Devices and Methods for Duplexer Loss Reduction
US9111801B2 (en) * 2013-04-04 2015-08-18 Stmicroelectronics, Inc. Integrated circuit devices and fabrication techniques
US9406695B2 (en) 2013-11-20 2016-08-02 Peregrine Semiconductor Corporation Circuit and method for improving ESD tolerance and switching speed
US9831857B2 (en) 2015-03-11 2017-11-28 Peregrine Semiconductor Corporation Power splitter with programmable output phase shift
US9948281B2 (en) 2016-09-02 2018-04-17 Peregrine Semiconductor Corporation Positive logic digitally tunable capacitor
US10587263B2 (en) * 2016-12-14 2020-03-10 Hitachi Automotive Systems, Ltd. Load drive apparatus
KR20200035420A (ko) * 2017-08-07 2020-04-03 타워재즈 파나소닉 세미컨덕터 컴퍼니 리미티드 반도체 장치
US10505530B2 (en) 2018-03-28 2019-12-10 Psemi Corporation Positive logic switch with selectable DC blocking circuit
US10236872B1 (en) 2018-03-28 2019-03-19 Psemi Corporation AC coupling modules for bias ladders
US10886911B2 (en) 2018-03-28 2021-01-05 Psemi Corporation Stacked FET switch bias ladders
US11476849B2 (en) 2020-01-06 2022-10-18 Psemi Corporation High power positive logic switch

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002231956A (ja) * 2001-02-01 2002-08-16 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
JP2002261292A (ja) * 2000-12-26 2002-09-13 Toshiba Corp 半導体装置及びその製造方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6353245B1 (en) * 1998-04-09 2002-03-05 Texas Instruments Incorporated Body-tied-to-source partially depleted SOI MOSFET
JP4614522B2 (ja) * 2000-10-25 2011-01-19 富士通セミコンダクター株式会社 半導体装置及びその製造方法
US6620656B2 (en) 2001-12-19 2003-09-16 Motorola, Inc. Method of forming body-tied silicon on insulator semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002261292A (ja) * 2000-12-26 2002-09-13 Toshiba Corp 半導体装置及びその製造方法
JP2002231956A (ja) * 2001-02-01 2002-08-16 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010004006A (ja) * 2008-06-18 2010-01-07 Internatl Business Mach Corp <Ibm> 寄生容量が低減されたsoiボディ・コンタクト型fetのための方法及び構造体
JP2010258471A (ja) * 2008-06-18 2010-11-11 Internatl Business Mach Corp <Ibm> 寄生容量が低減されたsoiボディ・コンタクト型fetのための方法
US7893494B2 (en) 2008-06-18 2011-02-22 International Business Machines Corporation Method and structure for SOI body contact FET with reduced parasitic capacitance

Also Published As

Publication number Publication date
EP1694615A2 (en) 2006-08-30
KR101113009B1 (ko) 2012-02-24
US20050127442A1 (en) 2005-06-16
TW200534340A (en) 2005-10-16
WO2005060464A3 (en) 2005-11-17
EP1694615A4 (en) 2009-09-23
KR20070003787A (ko) 2007-01-05
TWI358080B (en) 2012-02-11
CN1890799A (zh) 2007-01-03
US6953738B2 (en) 2005-10-11
WO2005060464A2 (en) 2005-07-07

Similar Documents

Publication Publication Date Title
JP2007514316A (ja) Soiボディコンタクトトランジスタを製造する方法及び装置
KR100189966B1 (ko) 소이 구조의 모스 트랜지스터 및 그 제조방법
US6392271B1 (en) Structure and process flow for fabrication of dual gate floating body integrated MOS transistors
TWI287867B (en) Independently accessed double-gate and tri-gate transistors in same process flow
KR20040065297A (ko) 본체결합식 실리콘-온-인슐레이터 반도체 디바이스 및 그제조방법
KR20000022709A (ko) 전계 효과 트랜지스터와 반도체 구조물 및 그의 제조 방법
JP3455452B2 (ja) 半導体デバイス及びその製造方法
EP1335425A1 (en) Semiconductor device and its production method
CN101304031A (zh) 电路结构及其制造方法
CN101772839B (zh) 具有金属栅极和高k电介质的电路结构
CN119050141A (zh) 利用埋置绝缘层作为栅极介电质的高压晶体管
US6555446B1 (en) Body contact silicon-on-insulator transistor and method
US20020175380A1 (en) Cmos with a fixed charge in the gate dielectric
JP2004072063A (ja) 半導体装置及びその製造方法
US9425189B1 (en) Compact FDSOI device with Bulex contact extending through buried insulating layer adjacent gate structure for back-bias
KR100457222B1 (ko) 고전압 소자의 제조방법
US7307320B2 (en) Differential mechanical stress-producing regions for integrated circuit field effect transistors
KR100424414B1 (ko) 고전압 트랜지스터 형성방법
KR100629267B1 (ko) 듀얼-게이트 구조를 갖는 집적회로 소자 및 그 제조 방법
KR20000066568A (ko) 반도체 소자의 제조방법
JP4265890B2 (ja) 絶縁ゲート型電界効果トランジスタの製造方法
JP2004103637A (ja) 半導体装置およびその製造方法
JPH08250726A (ja) 絶縁ゲート型電界効果トランジスタおよびその製造方法
TW202450117A (zh) 互補金氧半電路
JP2005175011A (ja) 電界効果型トランジスタ及びその製造方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20071109

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20071109

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110824

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20110825

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20111124

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20111201

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20111222

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20120515

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20120810

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20120817

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20120914

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20120924

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20121012

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20130409