Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
  • H03D3/00—Demodulation of angle-, frequency- or phase- modulated oscillations
  • H03D3/007—Demodulation of angle-, frequency- or phase- modulated oscillations by converting the oscillations into two quadrature related signals
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L27/00—Modulated-carrier systems
  • H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04B—TRANSMISSION
  • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
  • H04B1/06—Receivers
  • H04B1/16—Circuits
  • H04B1/22—Circuits for receivers in which no local oscillation is generated
  • H04B1/24—Circuits for receivers in which no local oscillation is generated the receiver comprising at least one semiconductor device having three or more electrodes
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04B—TRANSMISSION
  • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
  • H04B1/06—Receivers
  • H04B1/16—Circuits
  • H04B1/26—Circuits for superheterodyne receivers

Definitions

• the present invention relates generally to a radio signal receiver for use in wireless communications, and more particularly, to a radio signal receiver employing bandpass samplin g.
• the user signal to be transmitted is usually baseband signal with relatively low frequency and limited bandwidth, and in general can be expressed by two orthogonal components as l( ⁇ +jQ( ⁇ ⁇ The spectrum can be illustrated as in Fig.1, where l(t) is the in -phase component and Q(t) is the quadrature component.
• the transmitter modulates a carrier signal s, whose frequency is in RF (Radio Frequen cy) domain, with the user signal and then transmits the RF signal to radio space through the transmitting antenna.
• the receiver receives the RF signal from radio space through the antenna, and converts it into baseband digital signal centred at zero frequency so that the wanted user signal meeting the BER (Bit -Error-Rate) requirement can be recovered through further baseband processing.
• BER Bit -Error-Rate
• receiver 200 receives the RF signal via the antenna.
• the RF signal is first filtered by bandpass filter 220, and then amplified by LNA (Low Noise
• Down -converter 230 down-converts the received RF signal into IF (intermediate frequency) analog signal by exploiting a LO (local oscillator) signal, and the out -of-band interference in IF domain is rejected through IF filter 233. Afterwards, quadrature demodulation is performed on the IF signal in l/Q separating unit 240, to get two orthogonal baseband analog signals 1(f) and Q(t).
• IF filter 233 is indispensable, and the effect of IF filtering is directly related wi th the quality of the output signal. But in conventional super heterodyne receiver, IF filter 233 is implemented by bulky and expensive SAW (Surface Acoustic Wave) devices, making it very hard to be integrated with other circuits.
• SAW Surface Acoustic Wave
• the super heterodyne receiver needs a standalone IF SAW filter for every channel bandwidth in every mode, which increases the cost of receivers, and furthermore, the hardware constraints pose an obstacle to the upgrade of equ ipments.
• analog mixers are used many times in the receiver, thereby problems like nonlinear effects and image frequency interference, is unavoidable.
• a solutio n is proposed to adopt ZIF (Zero -IF) receiver or direct conversion receiver architectures, to convert the RF signal directly into baseband signal by taking advantage of the LO signal having the same frequency as the RF carrier.
• the received signal at the receiver is actually a bandpass signal in which a band-limited signal (shown in Fig.1) is modulated onto a HF carrier, and the lower sideband of the bandpass signal is much h igher than the bandwidth of the passband, so sampling can be done by choosing a clock signal whose frequency is lower than the carrier frequency of the received signal, and thus some portion of high -order spectrum components of the sampled signal is placed between the lower sideband of the bandpass signal and zero frequency.
• the sampling frequency in bandpass sampling is significantly lower than the carrier frequency of the signal, and thus is also called as sub-sampling. Two kinds of sub -sampling receiver architectures are proposed in the patent document, which is incorporated herein as reference.
• Fig.3 Architecture of the first sub -sampling receiver is shown in Fig.3.
• Fig.3 after being processed at RF bandpass filter 220 and LNA 221, the received RF signal is sent to sampler and holder 310, to be bandpass sampled at sampling frequency of _ f > 1B , wherein f c is the carrier frequency, " M + 1/4
• ADC 4 320 is used for converting the sampled signal into digital signal.
• the converted digital signal will be quadrature modulated in digital domain independently at digital mixers 3301 and 330Q.
• Digital mixers 3301 and 330Q f are used for moving the signal spectrum at ⁇ - to zero frequency, so that 4 orthogonal user digital signals can be recovered after being filtere d by the digital lowpass filters.
• the analog mixers and the IF filters are omitted, but two digital mixers are needed to implement the second frequency conversion to move the spectrum of the signal to be demodula ted into baseband.
• a very high sampling frequency (higher than twice the bandwidth of the bandpass signal) is normally required in order to avoid aliases in the receiver.
• the input signal of the sampling circuit often contains wideband interference. Therefore, the clock signal selected in practical applications often has a frequency much higher than the theoretical value, which often leads to low efficiency.
• AD Analog -to-Digital
• a two -path sub-sampling receiver architecture is disclosed in patent document US20020181614A1, as shown in Fig.4.
• the carrier frequency is multiple times the sampling frequency, so the nth -order spectrum component of the user signal will exist at zero frequency after sampling.
• the baseband analog signal at zero frequency can be filtered out through lowpass filters. And then baseband digital signal can be gotten after AD converting the baseband analog signal.
• processing of the digital mixer in the first sub -sampling receiver is omitted and the baseband signal can be AD converted directly.
• the sampling frequency is chosen, if N is even, the two paths will get the same result after the signal is sampled, and thus we can't obtain the separated orthogonal user signal s 1(f) and Q(t).
• wideband ADC is required to approach the receiving antenna as near as it can, and AD convert the RF signal direc tly, then various processing on the received signal should be implemented by programmable DSP (digital signal processing) devices as much as possible.
• DSP digital signal processing
• DSP is flexible, costs less and is easy for integration, so this method can realize compatibility of multiple communication protocols and easy for technical upgrade.
• this invention focuses on proposing a receiver architecture for AD converting the RF signal directly, and a specific method for recovering the wanted user signal as well.
• a bandpass -sampling receiver is proposed for receiving RF signals, comprising: the first ADC, for converting the RF signal into the first path of digital signal under the control of the first sampling clock signal; the second
• ADC for converting the RF signal into the second path of digital signal under the control of the second sampling clock signal
• a signal separating unit for separating the in -phase signal and the quadrature signal in the first path of digital signal and the second path of digital signal; wherein t he frequency of said first sampling clock signal and said second sampling clock signal is 1/N of the carrier frequency of said RF signal, and N is a natural number.
• Fig.1 displays the frequency spectrum of the baseband user signal
• Fig.2 is a block diagram illustrating the architecture of conventional super heterodyne receiver
• Fig.3 is a block diagram illustrating the architecture of a normal sub-sampling receiver
• Fig.4 is a block diagram illustrating the architecture of a normal two-path sub -sampling receiver
• Fig.5 displays the frequency spectrum of the RF signal after the user signal is modulated
• Fig.7 is a block diagram illustrating the architecture of the bandpass sampling receiver in an embodiment of the presen t invention
• Fig.8 illustrates structure of the proposed equipment for generating quadrature sampling clock signal in an embodiment of the present invention.
• S(t) can be further expressed as two bandpass components S'(f) and S"(t) with central frequencies as f c and -f c respectively:
• S ' (t) ⁇ [I(t)cos( ⁇ )-Q(t)s ( ⁇ )] + J[I(t)sin( ⁇ ) + Q(t) C os( ⁇ )] ⁇ e ⁇ (2)
• S t) ⁇ [I(t)cos( ⁇ )- Q(t)sm( ⁇ )] -j[I(t)s ( ⁇ ) + Q(t)c s( ⁇ )] ⁇ e- ⁇ ' (3) Its spectrum characteristic is shown in Fig.5.
• Fig.7 the architecture of the proposed bandpass sampling receiver is shown in Fig.7.
• the RF signal received at the antenna is filtered by bandpass filter 220 and amplified by LNA 221, divided into two paths, and then AD converted by ADC 710 and 711 respectively.
• the sampling clock frequencies of the two ADCs are both 1/N of the carrier frequency of the RF signal, but there is a fixed relative delay ⁇ between the sampling clocks CLK-i and CLK 2 of the two ADCs.
• the purpose of introducing the relative delay ⁇ lies in that the sampling instants in the two paths correspond to two different carrier phases, and accordingly two different digital sequences can be obtained after AD convers ion.
• the relative delay ⁇ is required to be much smaller than the reciprocal of B (i.e., ⁇ «-) in order that the in -phase component /(/) and the quadrature component ⁇ ( keep almost constant during the period ⁇ .
• the zero frequency component (or namely the baseband digital signal) of the sampled digital sequences can be obtained.
• the two paths of baseband digital signals are sent to l/Q separator 730 for necessary digital signal processing, thus the two orthogonal components are separated and sent to subsequent DSP modu le 740, and the wanted user signal can be recovered through further processing, such as demodulation, decoding and etc.
• l(t) and Q(t) can respectively be represented as the linear combination of the output signals S ⁇ (t) and S 2 (t) of digital lowpass filters 720 and 721: /(f ) _ s ⁇ ( sin t ⁇ -2 ) - ⁇ 2 (0 sinQP. ) (6) sin( ⁇ 2 - ⁇ Q ( - i , S l (t)c s( ⁇ 2 )-S 2 (t)cos( ⁇ l ) , y . sin ⁇ - ,) From equations (6) and (7), it can be known that l(t) and Q(t) are only related with the initial pha ses ⁇ ! and ⁇ 2 of the carrier relative to CLK 1 and
• l/Q separator 730 can process the received Si ( t) and S 2 (t) according to equations (6) and (7), to get 1(f) and Q(t) of the wanted user signal.
• l/Q separator 730 is placed behind the ADC, so the processed signal is digital sequence.
• the relative delay ⁇ between the two paths of clock signals CLK 1 and CLK 2 can be further constrained to satisfy c ⁇ 2n ⁇ - 2
• T c is the carrier cycle
• two sampling clock 2 4f c 4 signals can be generated readily with the method as shown in Fig.8.
• LO 801 generates a s ignal with frequency twice the carrier frequency of the received signal.
• the signal is split into two paths of orthogonal clock signals having the same frequency as the carrier frequency of the signal by the 1/2 splitter 802, thus it can be guaranteed that the phase shift is — under carrier frequency 0 ⁇ .
• two 1/N splitters 803 and 804 decrease the frequency of the two paths of orthogonal signals to 1/N of the former, i.e. the sampling clock frequency, thus the wanted sampling c locks CLK ⁇ and CLK 2 can be obtained, wherein 1/2 splitter 802 is required to ensure that the relative delay ⁇ between CLKi and CLK 2 can keep unchanged.
• equations (6) and (7) can be further 2 simplified.
• Q(t) -S l (t)sm( ⁇ i )-S 2 (t)cos( ⁇ ⁇ ) (13)
• the initial phase computing unit in l/Q separator 730 can compute the relative initial phase ⁇ ! of the carrier by taking advantage of the known midamble signal or pilot signal, with equation (10).
• ⁇ i (18)
• l/Q separator 730 can process the received Si (t) and S 2 (f) with equations (12) and (13) or
• l/Q separator 730 can recover the user signal with equations (19-26) under different cond itions: using two paths of baseband digital signals as the real part and imaginary part of the complex signal; rotating the phase of the complex signal with n times 90 degree, and then taking the real part and imaginary part of the complex signal as the corresponding separated in -phase signal and the quadrature signal respectively, to simplify the l/Q separation procedure at most.
• the aforementioned l/Q separator and the initial phase computing unit therein can be implemented in software, or in specific har dware to implement the algorithms in the equations, or in combination of both.
• the baseband signal can be obtained b y AD converting the RF signal with bandpass sampling method, and thus this leads to omission of analog mixers and IF filters that are usually bulky, power consuming and difficult to be integrated, which greatly simplifies the receiver architecture, and avo ids problems like nonlinear effects, image frequency interference, DC offset and mixer noise in conventional receivers.
• the sampling frequency can be significantly lower than the carrier frequency, thus the requirement fo r ADC's performance can be lowered.
• the present invention also overcomes the deficiency of two -path sampling methods in prior art, and the proposed receiver architecture can be applied in various situations through setting the delay ⁇ between two sampling clock signals to meet the condition ⁇ c ⁇ ⁇ n ⁇ .
• the details of l/Q separation are also offered in the presen t invention, which is of great help for the proposed receiver to be applied practically. It is to be understood by those skilled in the art that the bandpass sampling receiver as disclosed in this invention can be modified considerably without departing from the spirit and scope of the invention as defined by the appended claims.

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• Engineering & Computer Science (AREA)
• Computer Networks & Wireless Communication (AREA)
• Signal Processing (AREA)
• Power Engineering (AREA)
• Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

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• 2003
  • 2003-12-05 CN CNA2003101225023A patent/CN1625064A/zh active Pending
• 2004
  • 2004-12-01 JP JP2006542095A patent/JP2007513562A/ja not_active Withdrawn
  • 2004-12-01 WO PCT/IB2004/052611 patent/WO2005055449A1/en active Application Filing
  • 2004-12-01 KR KR1020067010845A patent/KR20060121126A/ko not_active Application Discontinuation
  • 2004-12-01 CN CNA2004800359042A patent/CN1890889A/zh active Pending

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