GB2461280A - A receiver for an analogue signal - Google Patents

Abstract

A receiver for an analogue signal having a carrier frequency fRFis disclosed. The receiver comprises a delta sigma modulator taking the analogue signal as input and providing a delta sigma modulated signal. A clock generator CLK provides a sampling clock signal for the DSM, having a sampling clock frequency fCLKof three times fRF. A demultiplexer takes the delta sigma modulated signal as input and provides a plurality of demulitplexed signals DEMUX SIGS. A digital I-Q converter takes the demultiplexed signals as input and provides a digital base band signal BBSIG having an in-phase component I and a quadtrature component Q. The receiver operates in a 3:1 mode which features better signal-to-noise ratio and better dynamic stability of the receiver.

Description

Description

The invention relates to a receiver for an analogue radio frequency (RF) signal and a method for processing a received analogue radio signal.

Background of the invention

A receiver for processing an analogue RF signal to yield a digital base band signal needs to perform two principal tasks: down-conversion and analogue-to-digital conversion. Many known receivers perform the down-conversion (or at least a significant part of the down-conversion) in the analogue domain using analogue circuitry. More recent receivers tend to shift the analogue-to-digital conversion towards the RF frontend, a development that was made possible by advances in the technology of analogue-to-digital converters. One of the types of analogue-to-digital converters that has been found to be suitable for the conversion of analogue RF signals is the delta-sigma modulator type. The article "Excess Loop Delay Effects in Continuous-Time Delta-Sigma Modulators and the Compensation Solution", Weinan Gao et. all, 1997 IEEE International Symposium on Circuits and Systems, June 9-12, 1997, Hong Kong, describes a receiver with a bandpass delta-sigma modulator (BPDSM).

The bandpass delta-sigma modulator is clocked at 3.6 GHz and is used to receive a 900 MHz RF signal, i.e. the clock frequency of the delta-sigma modulator is four times higher than the frequency of the received analogue signal. This so called 4:1 mode is often used for receivers, because samples from the analogue signal can be taken at RF carrier phases of 0°, 90°, 1800, and 270°. The conesponding sampling instances are +1, +Q, -I, -Q samples. Another common frequency ratio is 4:3, where the samples are taken at RF canier phases of 0°, 270°, 180°, and 900 (i.e. sampling instances are +1, -Q, -I, +Q).

While both the 4:1 mode and the 4:3 mode facilitate digital down conversion due to the choice of the sampling instances, they are not the optimum with respect to signal-to-noise ratio and stability regarding the dynamic range of the received analogue signal.

The European Patent Application EP 1 367 722 A2 describes an apparatus for generating at least one digital output signal representative of an analogue signal. This apparatus comprises a delta-sigma modulator that is clocked at the threefold frequency of the centre frequency of the analogue signal. The delta-sigma modulator in EP 1 367 722 A2 dual-path delta-sigma modulator that accepts sampled analogue signals that are phase offset by a phase difference.

At the input side of the delta-sigma modulator a demultiplexer is provided that produces said phase offset signals. At the output side of the delta-sigma modulator a multiplexer is provided that produces a multiplexed signal.

Summary of the invention

The teachings of this document improve the signal-to-noise ratio (SNR) and the dynamic range of a receiver for an analogue signal.

A receiver for an analogue signal having a canier frequency f is proposed, the receiver comprising a delta-sigma modulator taking the analogue signal as input, providing a delta- sigma modulated signal, a clock generator providing a sampling clock signal for the delta-signal modulator having a sampling clock frequency fCLK of three times fpy, a demultiplexer taking the delta-sigma modulated signal as input and providing a plurality of demultiplexed signals; a digital I-Q converter taking the demultiplexed signals as input and providing a digital base band signal having an in-phase component I and a quadrature component Q. Regarding the relation between the sampling clock frequency fCLK and the canier frequency RY it is submitted that the allowed deviation that still works is fCLK = (3 � 0.4) x that is for f ranging from fCLK = 2.6 x to fCLK = 3.4 x f. This deviation is within the scope of the claims. Also disclosed are ranges for the sampling clock frequency between 2.7 x f111 and 3.3 x between 2.8 x and 3.2 x as well as between 2.9 x and 3.1 x The proposed receiver offers an increased dynamic range and signal-to-noise ratio.

Furthermore, less switching noise and less jitter induced noise may be expected. The receiver supports a high input power and is stable in this respect. Possibly, the receiver also has a lower complexity than 4:1 mode delta-sigma modulators because the delta-sigma modulator only employs a "no return to zero" (NRZ) feedback, instead of employing both a "return to zero" (RZ) and a "half return to zero" (HRZ) feedback.

As illustrated in Fig. 8, for good quantization noise shaping, it is favourable to apply feedback current in the delta-sigma modulator only between the time from iT to 2T after each sampling event in the form of rectangular pulse 82. The sampling event is referenced by TSMPL. For a stable design, it is always required to have the centre of gravity 81, 83, 85 of the feedback pulse at a delay of 180° (with positive feedback coefficient) or 360° (with negative feedback coefficient) after each sampling event.

In 3:1 mode (Fig. 8, first diagram), a non-return to zero feedback is feasible, since the centre of gravity 81 of the interval from 1.0T to 2.0T is exactly at 180°. This relaxes speed requirements of the feedback digital-to-analogue converter (DAC) significantly. In particular, the non-return to zero feedback pulse is twice as long as the return-to-zero feedback pulse required in the 4:1 mode. Therefore the feedback DAC can be slower by another factor 2.

Furthermore, for the 3:1 mode the ratio of signal power contained in the feedback pulse 82 at the RF frequency over switching noise (including jitter induced noise) is quite good, since the pulse length is close to half the RF period (33% missing).

In contrast, the 4:1 mode (Fig. 8, second diagram) requires two pulses. A first pulse 84A extends from iT to 1.5T and a second pulse 84B extends from 1.5T to 2T, resulting in a centre of gravity 83. The two pulses have opposite polarity which is disadvantageous in terms of ratio of contained signal power at the radio frequency to switching noise power.

Tn 4:3 mode (Fig. 8, third diagram), the centre of gravity 85 is later, at 360° instead of 180°.

This is a disadvantage in terms of stability. Furthermore, the 4:3 mode tends to have poor bandwidth due to the low clock frequency / oversampling ratio.

In one aspect of the receiver, the demultiplexer is a 1:3 demultiplexer providing a base band triphase signal having triphase components at 0°, 120°, and 240° phases, respectively. Each of the triphase components resulting from the demultiplexing has a sample rate that is approximately equal to the frequency of the analogue RF signal so that each of the triphase components maintains a substantially constant phase relation to the RF signal.

Tn a further aspect of the receiver, the digital I-Q converter comprises a linear combiner taking the triphase components as input and providing the in-phase component I and the quadtrature component Q. The substantially constant phase relation between each of the triphase components and the analogue RE signal facilitates the conversion of the triphase components to a complex digital signal having an in-phase component I and a quadrature component Q. Tn another aspect of the receiver, the I-Q converter comprises delay elements for at least a part of the plurality of demultiplexed signals. The delay elements allow for aligning the various demultiplexed signals on the time line.

In one aspect of the receiver, the demultiplexer is a 1:2 demultiplexer providing two demultiplexed signals, and the I-Q converter comprises a digital mixer and a bandpass decimator, for mixing each one of the plurality of demultiplexed signals with a first local oscillator.

Tn a further aspect of the receiver, the first local oscillator has a frequency of a quarter of the sampling clock frequency.

a further aspect of the receiver, the bandpass decimator provides a plurality of intermediate frequency signals and the receiver further comprises a second digital mixer for mixing each one of the plurality of intermediate frequency signals with a second local oscillator.

In a further aspect of the receiver, the second local oscillator has a frequency fLo2 of 1/12 (one twelfth) of the sampling clock frequency fCLK.

The teachings of this document also improve a method for processing a received analogue radio signal.

The teachings of this document provide a method for processing a received analogue signal having a carrier frequency, the method comprising: generating a sampling clock signal having a clock frequency of three times the canier frequency, delta-sigma modulating the received analogue radio signal to a delta-sigma modulated signal at a sample rate equal to the frequency of the sampling clock signal, demultiplexing the delta-sigma modulated signal into a plurality of demultiplexed signals, and converting the demultiplexed signals to a digital base band signal having an in-phase component I and a quadrature component Q. In a further aspect of the method the demultiplexing of the delta-sigma modulated signal produces a triphase signal having triphase components at 00, 120°, and 240° phases, respectively, and wherein the method further comprises delaying at least two of the triphase components of the triphase signal to provide delayed triphase components; and linearly combining the delayed triphase components to produce the in-phase component I and the quadrature component Q. In another aspect of the method, the demultiplexing of the delta-sigma modulated signal produces two demultiplexed signals and the converting the demultiplexed signals comprises mixing each one of the plurality of the demultiplexed signals with a local oscillator, the local oscillator having a frequency of a quarter of the sampling clock frequency.

The teachings of this document also cover a computer program product comprising instructions that enable a processor to carry out the method as described above.

These and other aspects of the invention will be apparent from and elucidated with reference to the embodiment(s) described hereinafter.

Brief description of the figures

Fig. 1 shows a schematic block diagram of a receiver.

Fig. 2 shows a demultiplexer according to one aspect of the teachings of this document.

Fig. 3 shows an I-Q converter according to one aspect of the teachings of this document.

Fig. 4 shows a vector diagram illustrating the conversion of a triphase signal to an I-Q representation.

Fig. 5 is a detailed view of a part of the receiver according to one aspect of the teachings of this document.

Fig. 6 shows several time diagrams of various signals within the receiver.

Fig. 7 shows a diagram of the frequency domain for various signals within the receiver.

Fig. 8 shows time diagrams illustrating the relation between the analogue RF signal ARF and the feedback pulses for the 3:1 mode, the 4:1 mode, and the 4:3 mode.

Fig. 1 shows a block diagram illustrating the basic structure of a receiver RX for an analogue radio frequency signal ARF. The spectrum of the analogue radio frequency signal ARF is substantially centred on a frequency fRF. The receiver RX receives the signal ARF via an antenna or antenna array and typically a low noise amplifier (not shown). Signal ARF is then passed to a delta-sigma modulator DSM. A clock generator provides a sampling clock signal CLK to the delta-sigma modulator, the sampling clock signal CLK having a frequency fCLK 3 x fRF, i.e. approximately three times the frequency fRF of the analogue radio frequency signal ARF. The possible range of the frequency ratio could extend from a factor of 2.6 up to 3.4. It is expected that a frequency ratio within this range yields substantially equally good results than the frequency ratio of 3.0.

The delta-sigma modulator is preferably a bandpass delta-sigma modulator and produces a delta-sigma modulated signal DSM SIG (possibly a digital delta-sigma modulated signal) which is passed to a demultiplexer DEMUX. The demultiplexer DEMUX divides the delta-sigma modulated signal DSM SIG into several demultiplexed signals DEMUX SIGS. The demultiplexed signals DEMUX SIGS enter an I-Q converter I-Q CONY which produces base band signal BBSIG having an in-phase component I and a quadrature component Q. Fig. 2 shows the demultiplexer as a 1-to-3 demultiplexer 1:3 DEMUX that receives the delta-sigma modulated signal DSM SIG and produces a triphase signal 3-PHS SIG having three components, namely a triphase component at 0° CU, a triphase component at 120° C120, and a triphase component at 240° C240. Using a 1-to-3 demultiplexer delivers three baseband signals. Each of them can be decimated using a separate low-pass decimation filter (not shown).

Fig. 3 shows the I-Q converter I-Q CONY in the case where the demultiplexer produces a triphase signal 3-PHS SIG (cf Fig. 2). The I-Q converter I-Q CONY converts the triphase signal 3-PHS SIG to a complex signal having an in-phase component I and a quadrature component Q. A complex signal is needed for example on the so called CPRI link (Common Public Radio Interface). The I-Q converter I-Q CONY shown in Fig. 3 illustrates how the orthogonal signals I and Q can be generated by linearly combining the three triphase components CO. C120, and C240. Some phase or delay compensation is probably needed in order to combine the signals in phase. This is indicated by the blocks DEL FIL. These blocks DEL FIL could be digital allpass filters or lowpass filters of the FIR type (finite impulse response filter) which compensate for the differences of 11(3 x fp) and 2/(3 x fpy) within the delay, that inevitably occur in the demultiplexer DEMUX. This filtering could be done upstream of the decimation. In that case the decimation could be performed after the adders for the in-phase signal and the quadrature signal.

Fig. 4 shows a vector diagram illustrating the conversion of a triphase signal to a complex I-Q signal. The 0° component CO is represented in dashed lines, the 120° component C12O is represented in dotted lines, and the 240° component C240 is represented in dashed-dotted lines. The in-phase component I can be expressed by vector-wise adding the three components. In particular, the component having a phase of 00 is multiplied with a factor 1.0 (i.e. it is left unchanged), while the components having phases of 120° and 240°, respectively, are each multiplied by a factor -0.5. Dividing a digital number by a multiple of two is a relatively easy task, because it suffices to shift the bits by one or more positions. Adding the scaled components in the complex I-Q plane yields a vector having phase 0° and a length of 1 + 0.Scos(60°) + 0.Scos(60°) = 1.5, that is the in-phase component I scaled by a factor 1.5.

The scaling factor 1.5 is, however, not important in digital signal processing and can therefore be neglected. In a similar manner, the quadrature component Q is created by adding the two components having phases of 1200 and 240°, respectively. Each component is multiplied by cos(11/6)=0.866 (this multiplication could be performed after adding the two components or even omitted, because scaling factors are not as important for digital representations). The resulting vector sum has a phase of 90° and a length of 1.5. It can thus represent the quadrature component.

Fig. 5 shows a part of the receiver according to another aspect of the teachings of this document and can be regarded as an alternative to the structure shown in Figs. 2 and 3. The receiver uses a topology that is similar to the topology used for 4:1 mode receivers or 4:3 mode receivers. The receiver shown in Fig. 4 comprises a 1-to-2 demultiplexer 1:2 DEMUX that performs digital down-conversion and produces two demultiplexed signals.

The demultiplexer is followed by a circuit that alternatingly multiplies the data with a first local oscillator LOl formed by an alternating series of +1 (non-invert) and -1 (invert). First local oscillator LOl has a frequency fLol = 1/4 fCLK. Thus, the down-converted signal is at an intermediate frequency = f11 -fLo = 1/3 fCLK -/4 fCLK = /17 fCLK.

The two data streams resulting from the multiplication with the local oscillator are fed to a decimation filter that needs to be a bandpass decimation filter BP DEC due to the intermediate frequency of the signal output by the local oscillator circuit. Bandpass decimation filter BP DEC supports complex-valued input and output signals (I+jQ).

The low data rate decimated output signal(s) need to be down-converted from fif to base band which is a minor task at the reduced data rate. To this end, a second local oscillator L02 is used having a frequency fLo2 = fn = 1/ fCLK. The output(s) of the bandpass decimator BP DEC is/are mixed with the second local oscillator L02 to generate the base band signals I and Q. Fig. 6 shows time diagrams of the various signals generated within receiver RX. The first time diagram in Fig. 5 shows the sampling instants of the delta-sigma modulated signal DSM SIG in a schematic manner. The second time diagram in Fig. 5 shows one of the outputs of the 1 -to-2 demultiplexer 1:2 DEMUX SIG. The third time diagram in Fig. 6 shows the output MIX LOl of the mixer with first local oscillator LOl. As can be seen, every other sample is inverted.

Fig. 7 shows a schematic representation of the frequency domain to illustrate the relation of the various signals in the frequency domain. The analogue signal ARF has a frequency spectrum that is centred to f = 1/3 fCLK. The spectrum of ARF is drawn in an asymmetric manner in order to illustrate mirror images, where appropriate. On the right hand side of Fig. 6 the position of the sampling clock signal CLK in the frequency domain can be seen, i.e. at frequency fCLK. The first local oscillator LOl can be found at the frequency 1/4 fCLK. The arrow referenced by MOD LOl illustrates the effect of modulating the analogue signal ARF with the first local oscillator: A down-converted spectrum is created at the frequency 1/12 fCLK.

The second local oscillator LO2 is also situated at the frequency 1/12 fCLK. A second modulation process MOD L02 using the second local oscillator L02 creates a down-converted spectrum in the base band that corresponds to the base band signal BB SIG.

Fig. 8 shows time diagrams illustrating the relation between the analogue RF signal ARF and the feedback pulses for the 3:1 mode, the 4:1 mode, and the 4:3 mode. Fig. 8 is discussed in detail above.

While various embodiments of the present teachings have been described above, it should be understood that they have been presented by way of example, and not limitation. It will be apparent to persons skilled in the relevant arts that various changes in form and detail can be made therein without departing from the scope of the invention. For example, in addition to using hardware (e.g., within or coupled to a Central Processing Unit ("CPU'), microprocessor, microcontroller, digital signal processor, processor core, System on Chip ("SOC"), or any other device), implementations may also be embodied in software (e.g., computer readable code, program code, and/or instructions disposed in any form, such as source, object or machine language) disposed, for example, in a computer usable (e.g., readable) medium configured to store the software. Such software can enable, for example, the function, fabrication, modelling, simulation, description and/or testing of the apparatus and methods described herein. For example, this can be accomplished through the use of general programming languages (e.g., C, C++), hardware description languages (HDL) including Verilog HDL, VHDL, and so on, or other available programs. Such software can be disposed in any known computer usable medium such as semiconductor, magnetic disk, or optical disc (e.g., CD-ROM, DVD-ROM, etc.). The software can also be disposed as a computer data signal embodied in a computer usable (e.g., readable) transmission medium (e.g., carrier wave or any other medium including digital, optical, or analog-based medium).

Embodiments of the teachings within this document may include methods of providing the apparatus described herein by providing software describing the apparatus and subsequently transmitting the software as a computer data signal over a communication network including the Internet and intranets.

It is understood that the apparatus and method described herein may be included in a semiconductor intellectual property core, such as a microprocessor core (e.g., embodied in HDL) and transformed to hardware in the production of integrated circuits. Additionally, the apparatus and methods described herein may be embodied as a combination of hardware and software. Thus, the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.