JP6761218B2 - Reception processing device and receiver - Google Patents

Description

The techniques described herein relate to receiving processors and receivers.

A receiver that uses a direct RF (Radio Frequency) undersampling reception method is known.

Here, undersampling refers to a high frequency RF signal (which may be referred to as a “received signal”) at a lower frequency (which may be referred to as a “clock frequency” or a “sampling frequency”) f _CLK . It is a sampling technique. In undersampling by aliasing, art high frequency signal from f _{CLK / 2} is interference is folded below f _{CLK / 2} is utilized.

The receiver using the direct RF undersampling reception method amplifies the signal received by the antenna with an LNA (low noise amplifier), and passes the amplified signal through a BPF (bandpass filter). Further, the receiver undersamples the signal passed through the BPF at a predetermined clock frequency f _CLK by the S / H (sample hold) circuit. Then, the receiver performs analog / digital conversion of the undersampled signal, and filters the converted digital signal by a DSP (Digital Signal Processor) (see, for example, Patent Document 1 below).

Japanese Unexamined Patent Publication No. 2015-170935

By Behzad Razavi, Translated by Tadahiro Kuroda, "RF Microelectronics", Maruzen Co., Ltd., March 2002 Mitsuhiro Shimozawa, Kensuke Nakayama, Hiroomi Ueda, Tomohiro Tadokoro, Noriharu Suematsu, "An Even Harmonic Image Rejection Mixer using an Eight-Phase Polyphase Filter", Microwave Symposium Digest, 2008, IEEE MTT-S International, June 2008

When undersampling is performed by the S / H circuit, the clock frequency f _CLK is set to twice the system bandwidth, for example, so that there is a problem that the clock frequency f _CLK increases as the system bandwidth increases.

In one aspect, the techniques described herein are aimed at reducing the frequency of clock signals used in undersampling received signals.

In one aspect, the reception processing device samples the received signal based on a clock signal having a frequency lower than 0.25 times the frequency of the received signal, and extracts the first sampling signal and the second sampling signal. A sampling unit for generating an analog-digitally converted first sampling signal and a calculation unit for generating a first generated signal obtained by removing an image signal from the first sampling signal based on the second sampling signal. The first generated signal is a signal in the upper wave band which is a frequency band higher than the center frequency of the received signal or the lower wave band which is a lower frequency band, and the sampling unit receives the input of the clock signal. The first sampling signal is extracted by receiving an input of a delay unit that delays a predetermined time, which is a quarter cycle of the carrier of the received signal, and the received signal and the signal delayed by the delay unit . It includes a sampling unit and a second sampling unit that receives inputs from the received signal and the clock signal and extracts the second sampling signal.

As one aspect, the frequency of the clock signal used in undersampling the received signal can be reduced.

It is a block diagram which shows the structural example of the receiver of the related technology. It is a block diagram which shows the structural example of the receiver of an embodiment. It is a figure which shows the 1st example of SNR (signal-to-noise ratio) and IRR (image removal ratio) in the receiver of embodiment. It is a block diagram which shows the structural example of the receiver of the modification of embodiment. It is a block diagram which shows the structural example of the receiver of the differential circuit configuration corresponding to the receiver illustrated in FIG. It is a block diagram which shows the structural example of the receiver of the differential circuit configuration corresponding to the receiver illustrated in FIG. It is a figure which shows the 2nd example of SNR and IRR in the receiver of an embodiment and a modification.

Hereinafter, embodiments will be described with reference to the drawings. However, the embodiments shown below are merely examples, and there is no intention of excluding the application of various modifications and techniques not specified in the embodiments. That is, the present embodiment can be variously modified and implemented without departing from the gist thereof.

Further, each figure does not mean that it includes only the components shown in the figure, but may include other components. Hereinafter, in the drawings, parts having the same reference numerals indicate the same or similar parts unless otherwise specified.

[A] Related Technology FIG. 1 is a block diagram showing a configuration example of a receiver 8 of the related technology.

The receiver 8 of the related technology of the embodiment utilizes the direct RF undersampling reception method as an example. Since the direct RF undersampling reception method directly samples the RF signal, it is possible to realize a small receiver 8 with low power consumption.

As illustrated in FIG. 1, the receiver 8 includes an antenna 81, an LNA 82, a BPF 83, an S / H circuit 84, an oscillator 85, and an A / D (analog digital) converter 86.

The antenna 81 typically receives a signal transmitted by wireless communication from a transmitter (not shown).

Illustratively, the LNA 82 amplifies the signal received by the antenna 81 (which may be referred to as a "received signal" or "RF signal").

The BPF 83, exemplary, passes a signal amplified by the LNA for a predetermined frequency band.

Illustratively, the S / H circuit 84 samples the received signal that has passed through the BPF 83 based on the input from the oscillator 85 that generates the clock signal having a predetermined clock frequency f _CLK , and extracts the sampled signal.

The A / D converter 86, by way of example, converts the sampling signal extracted by the S / H circuit 84 into analog-to-digital conversion.

The receiver 8 may perform a filtering process by DSP (not shown) on the digital signal converted by the A / D converter 86.

When undersampling is performed by the S / H circuit 84, the clock frequency f _CLK is set to, for example, twice the system bandwidth, so that the clock frequency f _CLK increases as the system bandwidth increases.

[B] Embodiment [B-1] System configuration example In the receiver 100 of the embodiment, the clock frequency f _CLK used in the undersampling of the received signal SRF is exemplarily higher than the clock frequency f _CLK used conventionally. It can be reduced.

FIG. 2 is a block diagram showing a configuration example of the receiver 100 of the embodiment.

The receiver 100 typically utilizes an image removal type direct RF undersampling reception method. As illustrated in FIG. 2, the receiver 100 includes an antenna 1, an LNA2, a BPF3, an I / Q undersampling unit 4, an oscillator 5, an A / D converter 61, 62, an image removal calculation unit 7, and a USB output terminal. It includes 101 and an LSB output terminal 102. In addition, "I / Q" is an abbreviation for In-phase / Quadrature. USB is an abbreviation for Upper Side Band, and LSB is an abbreviation for Lower Side Band.

The I / Q undersampling unit 4 and the image removal calculation unit 7 may function as an example of the reception processing device.

The antenna 1 typically receives a signal transmitted by wireless communication from a transmitter (not shown).

LNA2 is an example of an amplifier. The LNA 2 schematically amplifies the signal received by the antenna 1 (which may be referred to as a "received signal" or "RF signal").

BPF3 is an example of a filter. BPF3, exemplary, passes a signal amplified by LNA2 for a predetermined frequency band. Further, BPF3 may attenuate the components of the frequency band other than the predetermined frequency band with respect to the signal amplified by LNA2.

As an example, the oscillator 5 generates a clock signal CLK having a frequency f _CLK lower than the frequency f _RF of the received signal SRF, and inputs the generated clock signal CLK to the I / Q undersampling unit 4.

The I / Q undersampling unit 4 is an example of a sampling unit, and may function by, for example, a CMOS (Complementary Metal-Oxide-Semiconductor) integrated circuit (IC circuit). The I / Q undersampling unit 4 includes, for example, S / H circuits 41 and 42 and a TL (Transmission Line) 43.

The I / Q undersampling unit 4 may sample the received signal based on the clock signal CLK having a frequency f _CLK lower than the frequency f _RF of the received signal SRF, and extract two sampled signals.

The two sampling signals may be referred to as a first sampling signal and a second sampling signal.

Further, the I / Q undersampling unit 4 performs sampling by making the phase of the received signal SRF with respect to the phase of the clock signal CLK different between the first sampling signal and the second sampling signal.

TL43 is an example of a delay portion. The TL 43 is exemplarily provided between the oscillator 5 and the S / H circuit 41 (except between the oscillator 5 and the S / H circuit 42), and delays the input of the clock signal CLK for a predetermined time. .. The TL43 may delay the input of the clock signal CLK, for example, by a quarter cycle (T / 4) of the carrier wave of the received signal SRF. The TL43 may be referred to as a delay line.

The S / H circuit 41 is an example of the first sampling unit, and typically receives the input of the received signal SRF and the signal delayed by the TL 43 and extracts the first sampling signal.

The S / H circuit 42 is an example of the second sampling unit, and typically receives the input of the received signal SRF and the clock signal CLK and extracts the second sampling signal.

The S / H circuits 41 and 42 discretize (may be referred to as “sampling”) the received signal SRF, which is an input analog signal, and keep the voltage of the discretized signal constant for a predetermined period. As a result, the sampling signal is output. The details of the sampling signal output method are described in, for example, Patent Document 1.

As described above, by delaying the input of the clock signal CLK by a quarter cycle (T / 4) of the carrier wave of the received signal SRF, the hold timing of the received signal SRF in the S / H circuit 41 and the S / H circuit 42 It shifts. Then, a phase difference of 90 degrees can be generated between the first sampling signal and the second sampling signal.

The TL 43 may be provided between the oscillator 5 and the S / H circuit 42 to delay the input of the clock signal CLK to the S / H circuit 42. In this case, the S / H circuit 41 may receive the input of the received signal SRF and the clock signal CLK and extract the first sampling signal. Further, in this case, the S / H circuit 42 may extract the second sampling signal by receiving the input of the received signal SRF and the signal delayed by the TL 43.

Illustratively, the A / D converters 61 and 62 perform analog-to-digital conversion of the sampling signal extracted by the I / Q undersampling unit 4, and input the analog-digitally converted sampling signal to the image removal calculation unit 7. The A / D converter 61 converts the first sampling signal extracted by the S / H circuit 41 into analog-to-digital conversion. Further, the A / D converter 62 converts the second sampling signal extracted by the S / H circuit 42 into analog-to-digital conversion.

The image removal calculation unit 7 is an example of a calculation unit, and may function by, for example, a DSP. The image removal calculation unit 7 typically removed the image signal from the first sampling signal and the second sampling signal by digital signal processing based on the sampling signal analog-digitally converted by the A / D converters 61 and 62. Generate a signal.

The signal obtained by removing the image from the first sampling signal is an example of the first generated signal, and may be referred to as an upper band signal USB. Further, the signal obtained by removing the image from the second sampling signal is an example of the second generated signal, and may be referred to as a lower band signal LSB.

The upper band signal USB is a signal having a component in a frequency band higher than the center frequency of the received signal SRF. Further, the lower band signal LSB is a signal having a component in a frequency band lower than the center frequency of the received signal SRF.

As described above, the TL 43 may be provided between the oscillator 5 and the S / H circuit 42 to delay the input of the clock signal CLK to the S / H circuit 42. In this case, the signal obtained by removing the image from the first sampling signal may be referred to as a lower band signal LSB, and the signal obtained by removing the image from the second sampling signal may be referred to as an upper band signal USB.

The first generated signal is a signal in the upper band, which is a frequency band higher than the center frequency of the received signal SRF, or the lower band, which is a lower frequency band. Further, the second generated signal is a signal on the band side different from the signal corresponding to the first generated signal among the signal in the upper wave band and the signal in the lower wave band.

That is, when the first generated signal is the upper band signal USB, the second generated signal is the lower band signal LSB, and when the first generated signal is the lower band signal LSB, the second generated signal is the lower band signal LSB. The signal is the upper band signal USB.

In the receiver 100 of the embodiment, the upper band signal USB and the lower band signal LSB can be taken out separately.

The image removal calculation unit 7 may include phase shift units 71 and 72 and addition units 73 and 74.

The phase shift unit 71 is an example of the first phase shift unit, and schematically shifts the phase of the first sampling signal by +90 degrees.

The phase shift unit 72 is an example of the second phase shift unit, and schematically shifts the phase of the second sampling signal by +90 degrees.

The addition unit 73 is an example of the first addition unit. Illustratively, the addition unit 73 adds the first sampling signal before the phase shift by the phase shift unit 71 and the second sampling signal after the phase shift by the phase shift unit 72 to obtain the upper band signal USB. In addition to in-phase synthesis and output, the lower band signal LSB, which is the image, is reverse-phase-synthesized and removed. Therefore, only the upper band signal USB is output to the USB output terminal 101.

The addition unit 74 is an example of the second addition unit. The addition unit 74 exemplifies the lower band signal LSB by adding the second sampling signal before the phase shift by the phase shift unit 72 and the first sampling signal after the phase shift by the phase shift unit 71. Is in-phase synthesized and output, and the upper band signal USB, which is the image, is reverse-phase-synthesized and removed. Therefore, only the lower band signal LSB is output to the LSB output terminal 102.

According to the image removal calculation unit 7 shown in FIG. 2, the image signal is canceled by performing separate phase shift operations for the desired wave and the image signal and adding the code-inverted image signal to the image signal. can do.

The image removal calculation unit 7 may generate only one of the upper band signal USB and the lower band signal LSB. When only one of the upper band signal USB and the lower band signal LSB is generated, the image removal calculation unit 7 includes the phase shift unit 71, the addition unit 74, the LSB output terminal 102, and the phase shift unit. It is not necessary to provide one of 72, the addition unit 73, and the USB output terminal 101.

Further, the phase shift unit 71 may shift the phase of the first sampling signal by −90 degrees, and the phase shift unit 72 may shift the phase of the second sampling signal by −90 degrees. In this case, in the example shown in FIG. 2, the output of the addition unit 73 is the lower band signal LSB, and the output of the addition unit 74 is the upper band signal USB.

FIG. 3 is a diagram showing a first example of SNR and IRR in the receiver 100 of the embodiment.

The SNR shown in FIG. 3 indicates the signal-to-noise ratio, and the IRR indicates the image removal ratio. The image removal ratio indicates the ratio of the signal level of the image signal to the signal level of the desired wave.

The image removal ratio in the upper band indicates the ratio of the signal level of the lower band signal LSB, which is the image signal, to the signal level of the upper band signal USB, which is a desired wave output from the USB output terminal 101. In other words, the image removal ratio in the upper band is the signal level of the lower band signal LSB that was reverse-phase synthesized by the adder 73 but remained unremoved, and the upper band signal USB, which is the desired wave. Shows the ratio to the signal level of.

The image removal ratio in the lower band indicates the ratio of the signal level of the upper wave signal to be the image signal to the signal level of the lower band signal LSB which is the desired wave output from the LSB output terminal 102. In other words, the image removal ratio in the lower band is the signal level of the upper band signal USB, which is reverse-phase synthesized by the adder 74 but remains unremoved, and the lower band signal, which is the desired wave. The ratio with the signal level of LSB is shown.

The frequency band _{f RF} reception signal SRF is 12.25~12.80GHz called satellite communication band and Ku band, SNR and IRR when the clock frequency _{f CLK} is 626MHz, like that illustrated in FIG. 3 become.

The SNR illustrated in FIG. 3 is 31.54 dB or more, and the IRR is 10.9 dB or more.

According to the receiver 100 of the embodiment, as illustrated in FIG. 3, for example, in the Ku band (in other words, the “satellite communication band”), in both the upper wave band and the lower wave band. The image signal can be removed.

In the example shown in FIG. 3, the system bandwidth (which may also be referred to as the "communication bandwidth") is 550 MHz, whereas the clock frequency f _CLK is set to 626 MHz.

In the receiver 8 of the related technology of the embodiment illustrated in FIG. 1, the clock frequency f _CLK is set to, for example, twice the system bandwidth, whereas the clock frequency f set in the receiver 100 of the embodiment is set. _CLK is less than the clock frequency f _CLK set in the receiver 8 of the related technology. In other words, in the receiver 100 of the embodiment, the clock frequency f _CLK , which is half of the clock frequency f _CLK used in the receiver 8 of the related technology of the embodiment illustrated in FIG. 1, is in the system band. The upper band signal USB and the lower band signal LSB can be received at the same time.

Further, in the receiver 8 of the related technology of the embodiment illustrated in FIG. 1, the pass band of the BPF 83 is set to, for example, half of the clock frequency, whereas it is set in the receiver 100 of the embodiment. The pass band of BPF3 can be wider than half the clock frequency.

That is, according to the receiver 100 of the embodiment, even when the system bandwidth is widened, the clock frequency f _CLK can be reduced as compared with the conventional case, and the pass band of BPF3 can be widened as compared with the conventional case.

[B-2] Modified Example FIG. 4 is a block diagram showing a configuration example of the receiver 100a of the modified example of the embodiment.

As illustrated in FIG. 4, the receiver 100a in the modified example includes an I / Q undersampling unit 4a in place of the I / Q undersampling unit 4 included in the receiver 100 of the embodiment illustrated in FIG. ..

Like the I / Q undersampling unit 4 illustrated in FIG. 2, the I / Q undersampling unit 4a includes S / H circuits 41, 42 and TL43, for example.

The TL43 is exemplarily provided between the BPF3 and the S / H circuit 41 (except between the BPF3 and the S / H42), and specifies the input of the received signal SRF to the S / H circuit 41. Delay the time.

Illustratively, the S / H circuit 41 receives the input of the signal delayed by the TL 43 and the clock signal CLK, and extracts the first sampling signal.

Illustratively, the S / H circuit 42 receives the input of the received signal SRF and the clock signal CLK and extracts the second sampling signal.

The TL 43 may be provided between the BPF 3 and the S / H circuit 42 to delay the input of the received signal SRF to the S / H circuit 42. In this case, the S / H circuit 41 may receive the input of the received signal SRF and the clock signal CLK and extract the first sampling signal. Further, in this case, the S / H circuit 42 may extract the second sampling signal by receiving the input of the signal delayed by the TL 43 and the clock signal CLK.

The receiver 100a in the modified example can also have the same effect as the receiver 100 of the above-described embodiment.

The same effect can be obtained by replacing the TL43 with a 90-degree hybrid circuit, a 90-degree distributor that combines a low-pass filter (LPF) and a high-pass filter (HPF), or a polyphase filter.

[C] Other disclosed techniques are not limited to the above-described embodiments, and can be variously modified and implemented without departing from the spirit of each embodiment. Each configuration and each process of each embodiment can be selected as necessary, or may be combined as appropriate.

The circuit of the receiver 100 in the above-described embodiment and the receiver 100a in the modified example may be a differential circuit.

FIG. 5 is a block diagram showing a configuration example of the receiver 100b having a differential circuit configuration corresponding to the receiver 100 illustrated in FIG.

As illustrated in FIG. 5, the receiver 100b outputs the inverted upper band signal USB and the inverted lower band signal LSB in addition to the upper band signal USB and the lower band signal LSB. To do.

As illustrated in FIG. 5, the receiver 100b includes an antenna 1, an LNA2, a BPF3, an inverter 9, an I / Q undersampling unit 4b, an oscillator 5, an A / D converter 61, 62, an image removal calculation unit 7a, and the like. It includes a USB output terminal 101, an LSB output terminal 102, an inverting USB output terminal 103, and an inverting LSB output terminal 104.

By way of example, the inverter 9 inverts one of the two received signal RFs output by BPF3, and inputs the inverted received signal RF to the I / Q undersampling unit 4b.

The I / Q undersampling unit 4b may include S / H circuits 41, 42 and TL43 in the same manner as the I / Q undersampling unit 4 illustrated in FIG. The I / Q undersampling unit 4b may perform undersampling and extract inverted first and second sampling signals in addition to the first and second sampling signals.

The S / H circuit 41 receives the input of the received signal SRF and the signal delayed by the TL 43, extracts the first sampling signal, and inputs the inverted received signal SRF and the signal delayed by the TL 43. The first sampling signal inverted after receiving the signal may be extracted.

The S / H circuit 42 receives the input of the received signal SRF and the clock signal CLK and extracts the second sampling signal, and receives the input of the inverted received signal SRF and the clock signal CLK and is inverted. The sampling signal may be extracted.

The A / D converter 61 may perform analog-to-digital conversion of the inverted first sampling signal in addition to the first sampling signal extracted by the I / Q undersampling unit 4b.

The A / D converter 62 may perform analog-to-digital conversion of the inverted second sampling signal in addition to the second sampling signal extracted by the I / Q undersampling unit 4b.

The image removal calculation unit 7a includes phase shift units 71a, 72a and addition units 73a, 74a in addition to the phase shift units 71, 72 and addition units 73, 74 included in the image removal calculation unit 7 illustrated in FIG. Good.

The phase shift units 71a and 72a may have the same functions as the phase shift units 71 and 72 illustrated in FIG. Further, the addition units 73a and 74a may have the same functions as the addition units 73a and 74a illustrated in FIG.

The phase shift unit 71a may shift the phase of the inverted first sampling signal by +90 degrees.

The phase shift unit 72a may shift the phase of the inverted second sampling signal by +90 degrees.

The addition unit 73a is inverted by adding the inverted first sampling signal before the phase shift by the phase shift unit 71a and the inverted second sampling signal after the phase shift by the phase shift unit 72a. A wave band signal USB may be generated. Then, the inverted upper band signal USB may be output from the inverted USB output terminal 103.

The addition unit 74a is inverted by adding the inverted second sampling signal before the phase shift by the phase shift unit 72a and the inverted first sampling signal after the phase shift by the phase shift unit 71a. The sideband signal LSB may be generated. Then, the inverted lower band signal LSB may be output from the inverted LSB output terminal 104.

FIG. 6 is a block diagram showing a configuration example of a receiver 100c having a differential circuit configuration corresponding to the receiver 100a illustrated in FIG.

In the receiver 100c, similarly to the receiver 100b illustrated in FIG. 5, in addition to the upper band signal USB and the lower band signal LSB, the inverted upper band signal USB and the inverted lower band signal Output LSB.

As illustrated in FIG. 6, the receiver 100c includes an I / Q undersampling unit 4c instead of the I / Q undersampling unit 4b included in the receiver 100b illustrated in FIG.

The I / Q undersampling unit 4c may include S / H circuits 41, 42 and TL43 in the same manner as the I / Q undersampling unit 4b illustrated in FIG.

The TL43 may be provided between the BPF3 and the S / H circuit 41 (except between the BPF3 and the S / H42). Further, the TL 43 may delay the input of the received signal SRF to the S / H circuit 41 for a predetermined time, and may delay the input of the inverted received signal RF to the S / H circuit 41 for a predetermined time.

The S / H circuit 41 may receive the input of the signal delayed by the TL 43 and the clock signal CLK, and extract the inverted first sampling signal in addition to the first sampling signal.

The S / H circuit 42 receives the input of the received signal SRF and the clock signal CLK and extracts the second sampling signal, and receives the input of the inverted received signal SRF and the clock signal CLK and is inverted. The sampling signal may be extracted.

The receivers 100b and 100c having a differential circuit configuration can also have the same effects as those of the above-described embodiments and modifications.

In the receiver 100 in the above-described embodiment and the receiver 100a in the modified example, n × f _CLK is a frequency substantially at the center of the reception band, but it can be set outside the reception band.

FIG. 7 is a diagram showing a second example of SNR and IRR in the receivers 100 and 100a of the embodiment and the modified example.

For example, n and f _CLK are designed so that n × f _CLK is outside the low band side of the reception band and (n + 1) × f _CLK is outside the wide band side of the reception band. Specifically, when f _RF is 12.25 GHz to 12.80 GHz and f _CLK is 610 MHz, the SNR and IRR are illustrated in FIG. 7.

The signal on the lower frequency side than 12.525 GHz is received as 20th-order undersampling as USB of n (= 20) × f _CLK , while the signal on the higher frequency side than 12.525 GHz is n + 1 (= 21). ) The 21st-order undersampling is received as the LSB of × f _CLK .

When n × f _{CLK is set} to a frequency almost at the center of the reception band, it is difficult to receive a modulated signal with a frequency that is exactly the center frequency, but by shifting the frequency of n × f _CLK , everything in the band It becomes possible to receive the frequency component of.

100, 100a, 100b, 100c, 8 Receiver 101 USB output terminal 102 LSB output terminal 103 Inverted USB output terminal 104 Inverted LSB output terminal 1,81 Antenna 2,82 LNA
3,83 BPF
4,4a, 4b, 4c I / Q undersampling unit 41, 42, 84 S / H circuit 43 TL
5,85 Oscillator 61, 62, 86 A / D converter 7,7a Image removal calculation unit 71, 72, 71a, 72a Phase shift unit 73, 74, 73a, 74a Addition unit 9 Inverter

Claims (7)

A sampling unit that samples the received signal based on a clock signal having a frequency lower than 0.25 times the frequency of the received signal and extracts the first sampling signal and the second sampling signal.
An arithmetic unit that generates a first generated signal obtained by removing an image signal from the first sampling signal based on the first sampling signal and the second sampling signal that have been analog-digitally converted.
With
The first generated signal is a signal in the upper wave band which is a frequency band higher than the center frequency of the received signal or the lower wave band which is a lower frequency band.
The sampling unit
A delay unit that delays the input of the clock signal for a predetermined time, which is a quarter cycle of the carrier wave of the received signal .
A first sampling unit that extracts the first sampling signal by receiving the input of the received signal and the signal delayed by the delay unit, and
A second sampling unit that receives the input of the received signal and the clock signal and extracts the second sampling signal , and
A reception processing device . A sampling unit that samples the received signal based on a clock signal having a frequency lower than 0.25 times the frequency of the received signal and extracts the first sampling signal and the second sampling signal.
An arithmetic unit that generates a first generated signal obtained by removing an image signal from the first sampling signal based on the first sampling signal and the second sampling signal that have been analog-digitally converted.
With
The first generated signal is a signal in the upper wave band which is a frequency band higher than the center frequency of the received signal or the lower wave band which is a lower frequency band.
The sampling unit
A delay unit that delays the input of the received signal for a predetermined time, which is a quarter cycle of the carrier wave of the received signal .
A first sampling unit that extracts the first sampling signal by receiving the input of the signal delayed by the delay unit and the clock signal, and
A second sampling unit that receives the input of the received signal and the clock signal and extracts the second sampling signal, and
The provided, reception processing device. The calculation unit
A first phase shift unit that shifts the phase of the second sampling signal by 90 degrees,
A first addition unit that generates the first generation signal by adding the first sampling signal and the second sampling signal after the phase shift by the first phase shift unit.
The reception processing apparatus according to claim 1 or 2 . Based on the analog-to-digital converted first sampling signal and the second sampling signal, the arithmetic unit further generates a second generated signal obtained by removing the image signal from the second sampling signal.
The second generated signal is a signal on the band side of the signal in the upper band and the signal in the lower band, which is different from the signal corresponding to the first generated signal.
The reception processing device according to any one of claims 1 to 3 . The calculation unit
A second phase shift unit that shifts the phase of the first sampling signal by 90 degrees,
A second addition unit that generates the second generation signal by adding the first sampling signal after the phase shift by the second phase shift unit and the second sampling signal.
The reception processing apparatus according to claim 4 . An amplifier that amplifies the received signal and
A filter that passes the received signal amplified by the amplifier in a predetermined frequency band,
A sampling unit that samples the received signal based on a clock signal having a frequency lower than 0.25 times the frequency of the received signal that has passed through the filter, and extracts the first sampling signal and the second sampling signal. ,
An analog-to-digital converter that converts the first sampling signal and the second sampling signal extracted by the sampling unit into analog-to-digital conversion, respectively.
An arithmetic unit that generates a first generated signal obtained by removing an image signal from the first sampling signal based on the first sampling signal and the second sampling signal that have been analog-digitally converted by the analog-digital converter.
With
The first generated signal is a signal in the upper wave band which is a frequency band higher than the center frequency of the received signal or the lower wave band which is a lower frequency band.
The sampling unit
A delay unit that delays the input of the clock signal for a predetermined time, which is a quarter cycle of the carrier wave of the received signal .
A first sampling unit that extracts the first sampling signal by receiving the input of the received signal and the signal delayed by the delay unit, and
A second sampling unit that receives the input of the received signal and the clock signal and extracts the second sampling signal , and
A receiver. An amplifier that amplifies the received signal and
A filter that passes the received signal amplified by the amplifier in a predetermined frequency band,
A sampling unit that samples the received signal based on a clock signal having a frequency lower than 0.25 times the frequency of the received signal that has passed through the filter, and extracts the first sampling signal and the second sampling signal. ,
An analog-to-digital converter that converts the first sampling signal and the second sampling signal extracted by the sampling unit into analog-to-digital conversion, respectively.
An arithmetic unit that generates a first generated signal obtained by removing an image signal from the first sampling signal based on the first sampling signal and the second sampling signal that have been analog-digitally converted by the analog-digital converter.
With
The first generated signal is a signal in the upper wave band which is a frequency band higher than the center frequency of the received signal or the lower wave band which is a lower frequency band.
The sampling unit
A delay unit that delays the input of the received signal for a predetermined time, which is a quarter cycle of the carrier wave of the received signal.
A first sampling unit that extracts the first sampling signal by receiving the input of the signal delayed by the delay unit and the clock signal, and
A second sampling unit that receives the input of the received signal and the clock signal and extracts the second sampling signal, and
A receiver.

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