WO2005055327A1 - 半導体受光素子及びその製造方法 - Google Patents
半導体受光素子及びその製造方法 Download PDFInfo
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- WO2005055327A1 WO2005055327A1 PCT/JP2004/017798 JP2004017798W WO2005055327A1 WO 2005055327 A1 WO2005055327 A1 WO 2005055327A1 JP 2004017798 W JP2004017798 W JP 2004017798W WO 2005055327 A1 WO2005055327 A1 WO 2005055327A1
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- Prior art keywords
- light receiving
- layer
- pad electrode
- light
- semiconductor
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/036—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes
- H01L31/0392—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including thin films deposited on metallic or insulating substrates ; characterised by specific substrate materials or substrate features or by the presence of intermediate layers, e.g. barrier layers, on the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/24—Coupling light guides
- G02B6/42—Coupling light guides with opto-electronic elements
- G02B6/43—Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1464—Back illuminated imager structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0232—Optical elements or arrangements associated with the device
- H01L31/02327—Optical elements or arrangements associated with the device the optical elements being integrated or being directly associated to the device, e.g. back reflectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
Definitions
- the present invention relates to a semiconductor light receiving element, particularly a back illuminated semiconductor light receiving element, and a method for manufacturing the same.
- a back-illuminated type semiconductor light-receiving element in which a semiconductor substrate is provided and a plurality of compound semiconductor layers are formed on the back surface opposite to the light incident surface of the semiconductor substrate is known.
- Patent Documents 13 See, for example, Patent Documents 13).
- the substrate portion corresponding to the light receiving section is partially thinned for the following purpose, and a thick portion is formed so as to surround the substrate portion.
- a first object is to prevent optical signal deterioration or loss due to light absorption of a semiconductor substrate.
- the second purpose is to prevent the semiconductor light receiving element from being damaged or damaged when the semiconductor light receiving element is mounted on an external substrate or the like by wire bonding or bump bonding.
- Patent Document 1 JP-A-3-104287
- Patent Document 2 JP-A-6-296035
- Patent Document 3 Japanese Patent Application Laid-Open No. 2002-353564
- the inventors of the present invention have studied the conventional semiconductor light receiving element, and have found the following problems. That is, the semiconductor light-receiving element described in Patent Documents 13 to 13 described above has a small thickness because a thick part exists around the thinned substrate part. There is a limit to conversion. In particular, when an array of semiconductor light receiving elements is to be formed, it is difficult to reduce the pitch, so that the element size must be increased (it is difficult to make the semiconductor light receiving elements compact).
- the present invention has been made to solve the above-described problems, and has as its object to provide a semiconductor light receiving element that can be sufficiently miniaturized while maintaining mechanical strength, and a method of manufacturing the same.
- a semiconductor light receiving element is a semiconductor light receiving element in which a plurality of compound semiconductor layers are stacked.
- a glass substrate that is optically transparent to incident light is adhered to the light incident surface side of the layer structure including a plurality of compound semiconductor layers via an silicon oxide film. .
- the mechanical strength of the layer structure is maintained by the glass substrate even when the plurality of compound semiconductor layers included in the layer structure are thinned. Become. Further, it is not necessary to form a thick portion around the thinned substrate portion corresponding to the light receiving portion as in the semiconductor light receiving device described in Patent Documents 13 to 13 described above. The size of the element can be easily reduced.
- the layer structure is bonded to a glass substrate via an oxidized silicon film, and the layer structure and the glass substrate are bonded using an adhesive or the like. It becomes possible to adhere without using. Therefore, the light incident from the glass substrate side can reach the layer structure without being absorbed by the adhesive or the like.
- the layer structure includes a first conductivity type high-concentration carrier layer, which is stacked in order from the light incident surface side as a plurality of compound semiconductor layers. It includes a conductive type light absorbing layer and a first conductive type cap layer. At least a light receiving region of the second conductivity type is formed in at least the cap layer, and the silicon oxide film is preferably formed on the high-concentration carrier layer side of the layer structure.
- the layer structure preferably further includes an antireflection film provided between the silicon oxide film and the high-concentration carrier layer.
- an antireflection film provided between the silicon oxide film and the high-concentration carrier layer.
- the semiconductor light-receiving element according to the present invention may further include a cap layer side of the layer structure.
- a light reflection film provided so as to cover the light receiving region.
- light that has once passed through the light absorbing layer without being absorbed is reflected by the light reflecting film and reenters the light absorbing layer (the absorption probability in the light absorbing layer is improved), so that the light sensitivity is further improved.
- the plurality of compound semiconductor layers include a light receiving portion, a first pad electrode disposing portion adjacent to the light receiving portion, and a second pad provided so as to sandwich the light receiving portion together with the first pad electrode disposing portion. It is composed of an electrode arrangement part.
- the light receiving section includes a part of a cap layer including a periphery of a light receiving region, a part of a light absorbing layer adjacent to a part of the cap layer, and a high concentration carrier layer adjacent to a part of the light absorbing layer. It is a region formed in a mesa shape including the portion.
- the first pad electrode disposition portion is a mesa-shaped region including a part of the cap layer, a part of the light absorption layer, and a part of the high-concentration carrier layer.
- the second pad electrode arrangement portion is a mesa-shaped region including a part of the cap layer, a part of the light absorption layer, and a part of the high concentration carrier layer.
- the light receiving section has a depression reaching the high concentration carrier layer.
- the semiconductor light receiving element further includes a first pad electrode disposed on the first pad electrode disposition portion, and a first wiring electrode for electrically connecting the first pad electrode to the light receiving region.
- the first wiring electrode is formed so that a part thereof extends along the side surface of the light receiving portion and the first pad electrode disposing portion over a portion between the light receiving portion and the first pad electrode disposing portion.
- the second wiring electrode partially extends along the side surface of the concave portion, the light receiving portion, and the second pad electrode disposing portion over a portion between the concave portion of the light receiving portion and the second pad electrode disposing portion. Formed.
- the parasitic capacitance can be further reduced.
- the light receiving portion has a recessed portion reaching the high concentration carrier layer, and the high concentration carrier layer of the light receiving portion and the second pad electrode are electrically connected by the second wiring electrode through the recessed portion. .
- the high-concentration carrier layer electrode of the light receiving section is directly drawn out, the series resistance can be greatly reduced. The As a result, a semiconductor light receiving element having excellent high-speed response characteristics is realized.
- each of the first and second pad electrode arrangement portions includes a part of the high-concentration carrier layer, a part of the light absorption layer, and a part of the cap layer. It is also easy to arrange the first pad electrode and the second pad electrode at substantially the same height. Then, the semiconductor light receiving element can be mounted by bump bonding.
- the second pad electrode disposition portion which is only the first pad electrode disposition portion, is also separated from the light receiving portion, the interval between the light receiving portion and the first pad electrode and the light receiving portion and the second pad electrode The interval between and is relatively wide.
- the electrodes are directly drawn from the high-concentration carrier layer of the light receiving section as described above, the series resistance is greatly reduced even when the wiring length is long.
- the recess is formed in a groove shape so as to surround the light receiving region.
- the connection area between the high-concentration carrier layer of the light receiving section and the second wiring electrode increases, and the series resistance can be further reduced.
- a bump electrode may be arranged on the first pad electrode and the second pad electrode.
- the semiconductor light receiving element can be mounted without increasing the wiring resistance.
- the semiconductor light receiving element according to the present invention may include one or more light receiving units having the same structure as the light receiving unit. In this case, these light receiving units are arranged in an array.
- the glass substrate may be provided with a lens unit for condensing incident light.
- the lens portion is formed closer to the layer structure than the outermost surface opposite to the surface of the glass substrate facing the layer structure.
- the glass substrate on which the lens portion is formed can be easily bonded.
- the degree of freedom in designing a lens shape and the like increases, so that there is little restriction on the processing method and the like.
- a method for manufacturing a semiconductor light receiving element includes a first step of preparing a semiconductor substrate and a glass substrate that is optically transparent to incident light; A second step of forming a layer structure including a plurality of compound semiconductor layers, a third step of forming a silicon oxide film on the side opposite to the semiconductor substrate across the layer structure, A fourth step of adhering the glass substrate to the layer structure via the silicon oxide film so as to be in contact with one surface of the glass substrate, and a step performed after the fourth step. A fifth step of removing the semiconductor substrate in contact with the layer structure.
- the layer structure is formed such that the silicon oxide film formed on the outermost surface side of the layer structure including the plurality of compound semiconductor layers is in contact with one surface of the glass substrate. After the semiconductor substrate and the glass substrate are bonded, the semiconductor substrate is removed. Therefore, a semiconductor light receiving element in which the glass substrate is bonded to the light incident surface side of the layer structure via the silicon oxide film can be easily obtained.
- the layer structure Is maintained by the glass substrate.
- the semiconductor light-receiving element obtained by the manufacturing method does not need to form a thick part around the thinned substrate part, as in the semiconductor light-receiving element described in Patent Documents 13 to 13. It is easy to reduce the size of the element. Before the glass substrate is bonded, the mechanical strength of the layer structure is maintained by the semiconductor substrate.
- the layer structure is bonded to the glass substrate via the silicon oxide film
- the laminated plurality of compound semiconductor layers use an adhesive or the like for the glass substrate. Glued without.
- the light which also has a glass substrate side force, can reach a plurality of stacked compound semiconductor layers without being absorbed by the adhesive or the like.
- the fifth step of removing the semiconductor substrate it is preferable to remove the semiconductor substrate by wet etching.
- the manufacturing method according to the present invention is a step performed between the first step and the second step, wherein the wet etching method is provided between the semiconductor substrate and the layer structure.
- etching of the semiconductor substrate becomes possible, and an etching solution that cannot etch the etching stop layer and an etching solution that cannot etch the etching stop layer.
- an etchant that can etch but cannot etch the compound semiconductor layer only the etching stop layer can be removed after the semiconductor substrate is removed. Therefore, the semiconductor substrate can be reliably and easily removed while leaving the layer structure (a plurality of compound semiconductor layers).
- the manufacturing method according to the present invention further includes a step performed between the first sub-step and the second step, wherein the step is located between the etching stop layer and the layer structure. It is preferable to include a second sub-step of forming a protective layer for protecting a plurality of compound semiconductor layers with an etchant. In this case, the layer structure (a plurality of compound semiconductor layers) is reliably prevented from being contaminated by the etchant.
- the layer structure may include a first conductive type cap layer and a first conductive type cap layer, which are stacked in order of a side force facing the semiconductor substrate as a plurality of compound semiconductor layers. It is preferable to include a light absorption layer of one conductivity type and a high concentration carrier layer of the first conductivity type.
- the manufacturing method according to the present invention is a step performed between the second step and the third step, wherein the step is performed so as to be located between the layer structure and the silicon oxide film.
- a third sub-step of forming an antireflection film on the opposite side of the layer structure from the semiconductor substrate may be provided. In this case, the reflection of light entering the light absorbing layer is prevented, and the amount of light incident on the light absorbing layer increases, so that the light sensitivity is improved.
- the manufacturing method according to the present invention is a step performed after the fifth step, further comprising: a seventh step of forming a light-receiving region of the second conductivity type in at least the cap layer; An eighth step of forming a depression extending from the cap layer to the high-concentration carrier layer; and a step performed after the seventh step, wherein the light-receiving section and the first
- a twelfth step of forming along the side surface of the placement part, and The thirteenth wiring electrode is formed so that a part of the wiring electrode extends along the side surface of the concave portion, the light receiving portion, and the second pad electrode disposing portion over a portion between the concave portion of the light receiving portion and the second pad electrode disposing portion. Process You may get.
- the first pad electrode arrangement section, the light receiving section, and the second pad electrode arrangement section are separated, so that the parasitic capacitance can be further reduced.
- a depression reaching the high-concentration carrier layer is formed in the light-receiving portion, and the high-concentration carrier layer of the light-receiving portion is electrically connected to the second pad electrode via the depression through the second wiring electrode.
- the high-concentration carrier layer electrode of the light receiving section is directly drawn out, and the series resistance is greatly reduced. As a result, a semiconductor light receiving element having excellent high-speed response characteristics can be obtained.
- each of the first pad electrode arrangement section, the light receiving section, and the second pad electrode arrangement section has a part of the high concentration carrier layer, a part of the light absorption layer, and one part of the cap layer. Since the first pad electrode and the second pad electrode are included at the same height, it is easy to arrange them. Then, the semiconductor light receiving element can be mounted by bump bonding.
- the second pad electrode disposition portion which is formed only by the first pad electrode disposition portion, is formed separately from the light receiving portion. Therefore, the distance between the light receiving portion and the first pad electrode and the light receiving portion and the second pad The distance between the electrodes is relatively wide. However, since the electrodes are directly drawn from the high-concentration carrier layer of the light receiving section as described above, the series resistance is greatly reduced even when the wiring length is long.
- the manufacturing method according to the present invention may further include a fourteenth step of forming a light reflecting film so as to cover the light receiving region, which is a step performed after the seventh step.
- a fourteenth step of forming a light reflecting film so as to cover the light receiving region, which is a step performed after the seventh step.
- light that has once passed through the light absorbing layer without being absorbed is reflected by the light reflecting film and re-enters the light absorbing layer (the absorption probability in the light absorbing layer is improved), so that the light sensitivity is improved.
- the glass substrate is provided with a lens unit that collects incident light.
- the lens portion is formed closer to the layer structure than the outermost surface opposite to the surface of the glass substrate facing the layer structure.
- the glass substrate on which the lens portion is formed can be easily bonded to the layer structure.
- the degree of freedom in designing the lens shape and the like is increased without being limited by the processing method and the like.
- the present invention it is possible to provide a semiconductor light receiving element capable of sufficiently miniaturizing while maintaining mechanical strength, and a method for manufacturing the same.
- FIG. 1 is a plan view showing a schematic configuration of a first embodiment of a semiconductor light receiving element according to the present invention.
- FIG. 2 is a view for explaining a cross-sectional structure of the semiconductor light receiving element shown in FIG. 1 along the line II-II.
- FIG. 3 is a cross-sectional view for explaining a manufacturing process of the first embodiment of the semiconductor light receiving element according to the present invention (part 1).
- FIG. 4 is a cross-sectional view for explaining a manufacturing step of the first embodiment of the semiconductor light receiving element according to the present invention (part 2).
- FIG. 5 is a cross-sectional view for explaining the manufacturing process of the first embodiment of the semiconductor light receiving element according to the present invention (part 3).
- FIG. 6 is a cross-sectional view for explaining the manufacturing process of the first embodiment of the semiconductor light receiving element according to the present invention (part 4).
- FIG. 7 is a cross-sectional view for explaining the manufacturing process of the first embodiment of the semiconductor light receiving element according to the present invention (part 5).
- FIG. 8 is a cross-sectional view for explaining the manufacturing process of the first embodiment of the semiconductor light receiving element according to the present invention (part 6).
- FIG. 9 is a cross-sectional view for explaining the manufacturing process of the first embodiment of the semiconductor light receiving element according to the present invention (part 7).
- FIG. 10 is a cross-sectional view for explaining the manufacturing process of the first embodiment of the semiconductor light receiving element according to the present invention (part 8).
- FIG. 11 is a cross-sectional view for explaining the manufacturing process of the first embodiment of the semiconductor light receiving element according to the present invention (part 9).
- FIG. 12 is a cross-sectional view for explaining the manufacturing process of the first embodiment of the semiconductor light receiving element according to the present invention (part 10).
- FIG. 13 is a view for explaining a cross-sectional structure of a second embodiment of the semiconductor light receiving element according to the present invention.
- FIG. 14 is a cross-sectional view for explaining a manufacturing process of the second embodiment of the semiconductor light receiving element according to the present invention (part 1).
- FIG. 15 is a cross-sectional view for explaining a manufacturing step of the second embodiment of the semiconductor light receiving element according to the present invention (part 2).
- FIG. 16 is a cross-sectional view for explaining a manufacturing step of the second embodiment of the semiconductor light receiving element according to the present invention (part 3).
- FIG. 17 is a view for explaining a cross-sectional structure of a third embodiment (array structure) of the semiconductor light receiving element according to the present invention.
- FIG. 18 is a view for explaining a cross-sectional structure of a fourth embodiment (array structure) of the semiconductor light receiving element according to the present invention.
- FIG. 19 is a diagram showing a schematic configuration of an optical interconnection system to which the semiconductor device according to the present invention can be applied.
- semiconductor base Board 52 ⁇ buffer layer, 53 ⁇ etching stop layer, 54 ⁇ protective layer, 101 ⁇ optical interconnection system, 103 ⁇ semiconductor light emitting device, 105 ⁇ drive circuit, 107 ⁇ optical waveguide substrate , 107a... Optical waveguide, 109 ⁇ Amplifier circuit, LS... Layer structure, ⁇ 1, ⁇ 2 ⁇ Module, PD1, PD2... Semiconductor light receiving element, PD3, ⁇ 4 ⁇ Semiconductor light receiving element array.
- FIG. 1 is a plan view showing a schematic configuration of a first embodiment of a semiconductor light receiving element according to the present invention.
- FIG. 2 is a diagram for explaining a cross-sectional structure of the semiconductor device according to the first embodiment, taken along line II-II in FIG. In FIG. 1, the bump electrode 41 is omitted.
- the semiconductor light receiving element PD1 includes a layer structure LS and a glass substrate 1.
- the semiconductor light receiving element PD1 is a back-illuminated semiconductor light receiving element in which light enters the layer structure LS from the glass substrate 1 side.
- the semiconductor light receiving element PD1 is, for example, a light receiving element for short-range optical communication in a wavelength band of 0.85 m.
- the layer structure LS includes an antireflection film 2, an n-type (first conductivity type) high-concentration carrier layer 3, an n-type light absorption layer 5, and an n-type cap layer 7, which are sequentially stacked. Contains.
- the glass substrate 1 is bonded to the antireflection film 2 side of the layer structure LS via the film 10.
- the glass substrate 1 has a thickness of about 0.3 mm and is optically transparent to incident light.
- the film 10 is formed on the high-concentration carrier layer 3 (the antireflection film 2) side of the layer structure LS.
- the film 10 is made of silicon oxide silicon))) and has a thickness of about 0.1 m.
- the antireflection film 2 is located between the high-concentration carrier layer 3 and the silicon oxide film 10 and has, for example, a SiN force.
- the thickness of the antireflection film 2 is defined as n, where n is the refractive index of the antireflection film 2, and
- the thickness of the antireflection film 2 is 1000 to 3000 A.
- the layer structure LS includes a light receiving unit 11, a first pad electrode arrangement unit 21, and a second pad electrode arrangement unit 3 Is formed with one.
- the light receiving unit 11, the first pad electrode arrangement unit 21, and the second pad electrode arrangement unit 31 are arranged on the glass substrate 1 in a state where they are separated from each other.
- the light receiving section 11 has a mesa shape (in this embodiment, a truncated cone) including the n-type high concentration carrier layer 3a, the n-type light absorption layer 5a, and the n-type cap layer 7a. .
- a p-type (second conductivity type) light receiving region 9 is formed on the cap layer 7a.
- the top of the light receiving section 11 and the light receiving area 9 have a circular shape when viewed from the light incident direction.
- a recess 13 is formed at the top of the light receiving section 11 outside the light receiving area 9 when viewed from the light incident direction.
- the depression 13 is formed in a groove shape so as to reach the high-concentration carrier layer 3 a and surround the light receiving region 9.
- the light receiving section 11 is configured to include the inner portion 1 la in a mesa shape including the light receiving region 9 and the outer portion 1 lb positioned so as to surround the inner portion 1 la.
- the concave portion 13 is formed in a C shape along the edge of the light receiving region 9 and leaving a part of the top of the light receiving portion 11 (a portion near the first pad electrode arrangement portion 21) as viewed from the light incident direction. Have been.
- An annular contact electrode 15 is arranged on the front surface side of the light receiving region 9. This contact electrode 15 is electrically connected to the light receiving region 9.
- the contact electrode 15 is made of Ti-Pt-Au and has a thickness of about 100Onm.
- the contact electrode 15 is arranged so as to be embedded in the light receiving region 9 (cap layer 7a) .
- the force is not limited to this, and may be disposed on the light receiving region 9 (cap layer 7a).
- a contact electrode 17 is arranged. This contact electrode 17 is electrically connected to the high concentration carrier layer 3a.
- the contact electrode 17 is made of a laminate of Au-GeZN iZAu and has a thickness of about 100Onm.
- the contact electrode 17 is also formed in a C-shape when viewed from the light incident direction, similarly to the depression 13.
- a passivation film 19 is formed on the front side of the light receiving section 11 so as to cover the light receiving area 9.
- the first pad electrode disposing portion 21 and the second pad electrode disposing portion 31 have a mesa-like shape including an n-type high concentration carrier layer 3b, an n-type light absorbing layer 5b, and an n-type cap layer 7b. In the embodiment, the shape is a truncated cone.
- the tops of the first pad electrode arrangement section 21 and the second pad electrode arrangement section 31 have a circular shape when viewed from the light incident direction.
- a first pad electrode 23 is disposed on the top of the first pad electrode disposition portion 21 on the noise film 19.
- a second pad electrode 33 is disposed on the nomination film 19.
- the first pad electrode 23 and the second pad electrode 33 are made of Ti Pt Au and have a thickness of about 1.5 m.
- the first pad electrode 23 and the second node electrode 33 have substantially the same height from the glass substrate 1 and have a circular shape when viewed from the light incident direction.
- a bump electrode 41 is disposed on each of the first pad electrode 23 and the second pad electrode 33, as shown in FIG.
- the high-concentration carrier layer 3 (3a, 3b) is a compound semiconductor layer and is made of, for example, AlGaAs (Al composition 0.3) having a carrier concentration of about 1 ⁇ 10 18 Zcm 3 .
- the thickness of the high concentration carrier layer 3 (3a, 3b) is about 2 / zm.
- the A1 composition ratio of the high-concentration carrier layer 3 is preferably set to 0.3 or more. If the light having a wavelength of 850 nm or more is received, the A1 yarn composition ratio X may be 0.04, but the more preferable high concentration carrier layer 3 has an A1 composition ratio of 0.3 or more. However, the A1 composition ratio of the high-concentration carrier layer 3 is appropriately determined depending on the wavelength of light to be received. For example, if short-wavelength light having a wavelength of 650 nm is received, the A1 composition ratio must be 0.4 or more. It becomes important.
- the light absorbing layer 5 is a compound semiconductor layer and is made of, for example, GaAs having a carrier concentration of about 1 ⁇ 10 ′′ Zcm 3.
- the light absorbing layer 5 (5a, 5b) has a thickness of 3 It is about ⁇ m.
- the cap layer 7 (7a, 7b) is a compound semiconductor layer and has a carrier concentration of, for example, 5 ⁇ 10 1
- AlGaAs Al composition 0.3
- the thickness of the cap layer 7 (7a, 7b) is about 0.3 ⁇ m.
- the light receiving region 9 is obtained by thermally diffusing a P-type impurity (for example, Zn) into a desired region of the cap layer 7a and inverting the region to a p-type, and has a depth of 0.4. m.
- the diameter of the light receiving area 9 is 5 to 200 ⁇ .
- the width of the recess 13 (groove) is about 5 ⁇ m.
- the light receiving diameter depends on the characteristics required for the light receiving element, it can be designed in a wide range from 1 m to 10 mm.
- the contact electrode 15 and the first pad electrode 23 are electrically connected by the first wiring electrode 43.
- the first wiring electrode 43 is arranged on the passivation film 19 so as to extend between the light receiving section 11 and the first pad electrode arrangement section 21.
- the first wiring electrode 43 is It extends along the side surface of the light receiving portion 11 and the side surface of the first pad electrode arrangement portion 21 over the region where the recessed portion 13 is not formed.
- the first wiring electrode 43 is made of Ti Pt Au and has a thickness of about 1.5 m.
- the portion of the first wiring electrode 43 located on the light receiving section 11 is located on the light receiving area 9 so as to cover the light receiving area 9 and has a circular shape.
- the portion of the first wiring electrode 43 located on the light receiving section 11 functions as a light reflection film. It should be noted that the light reflecting film may be formed separately from the first wiring electrode 43! / ⁇ .
- One end of the first wiring electrode 43 is connected to the contact electrode 15 through a contact hole 19 a formed in the passivation film 19, and the other end is connected to the first pad electrode 23.
- the light receiving region 9 is electrically connected to the first nod electrode 23 (bump electrode 41) through the contact electrode 15 and the first wiring electrode 43. That is, the extraction of the electrode on the light receiving region 9 side is realized by the contact electrode 15, the first wiring electrode 43, the first pad electrode 23, and the bump electrode 41.
- the contact electrode 17 and the second pad electrode 33 are electrically connected by the second wiring electrode 45.
- the second wiring electrode 45 extends between the depression 13 of the light receiving section 11 and the second pad electrode arrangement section 31 and is arranged on the nomination film 19. A portion of the second wiring electrode 45 located on the light receiving portion 11 is formed in a C shape when viewed from the light incident direction so as not to contact the first wiring electrode 43.
- the second wiring electrode 45 extends along the side surface of the recess 13, the side surface of the light receiving unit 11, and the side surface of the second pad electrode arrangement unit 31.
- the second wiring electrode 45 is made of Ti Pt Au and has a thickness of about 1.5 ⁇ m.
- One end of the second wiring electrode 45 is connected to the contact electrode 17 through a contact hole 19 a formed in the passivation film 19, and the other end is connected to the second pad electrode 33.
- the high-concentration carrier layer 3a is electrically connected to the second pad electrode 33 (bump electrode 41) through the contact electrode 17 and the second wiring electrode 45. That is, the extraction of the electrode on the high-concentration carrier layer 3a side is realized by the contact electrode 17, the second wiring electrode 45, the second pad electrode 33, and the bump electrode 41.
- FIGS. 3 to 12 show the semiconductor light receiving device according to the first embodiment.
- FIG. 4 is an explanatory diagram for explaining the manufacturing method, and shows a vertical cross-sectional configuration of the semiconductor light receiving element.
- a semiconductor substrate 51 and a glass substrate 1 are prepared.
- the semiconductor substrate 51 is made of, for example, n-type GaAs having a thickness of 300 to 500 m and a carrier concentration of about IX 10 18 Zcm 3 .
- the buffer layer 52 and the etching stop by hydride vapor phase epitaxy, chloride vapor phase epitaxy, metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), etc.
- the layer 53 and the protective layer 54 are sequentially grown and laminated (see FIG. 3).
- the n-type cap layer 7, the n-type light absorbing layer 5, and the n-type high-concentration carrier are formed on the protective layer 54 by hydride vapor phase epitaxy, chloride vapor phase epitaxy, MOCVD, MBE, or the like.
- Layer 3 is grown sequentially and stacked (see Figure 3).
- the buffer layer 52 is made of non-doped GaAs, and has a thickness of about 0.05 ⁇ m.
- the etching stop layer 53 is made of non-doped AlGaAs (Al thread 0.4), and has a thickness of about 1.0 / zm.
- the etching stop layer 53 is formed so as to be located between the semiconductor substrate 51 and the cap layer 7.
- the A1 composition ratio of the etching stopper layer 53 is preferably set to 0.4 or more. This is because this Al Ga As is used when etching GaAs described later.
- the protective layer 54 is made of non-doped GaAs and has a thickness of about 0.2 m.
- the protection layer 54 is formed so as to be located between the etching stop layer 53 and the cap layer 7.
- an antireflection film 2 and a film 10 are sequentially formed on the high-concentration carrier layer 3 by a plasma chemical vapor deposition (PCVD) method (see FIG. 3).
- the antireflection film 2 is formed so as to be located between the film 10 and the high-concentration carrier layer 3.
- the layer structure LS and the films 52-54, 10 are formed on the semiconductor substrate 51. Formed on
- the semiconductor substrate 51 on which the layer structure LS and the films 52 to 54 and 10 are formed is bonded to the glass substrate 1 (see FIG. 4).
- one surface (front surface) of the glass substrate 1 is cleaned.
- the glass substrate 1 and the semiconductor substrate 51 are overlapped so that the cleaned surface of the glass substrate 1 and the outermost surface film 10 of the semiconductor substrate 51 are in contact with each other. Pressing and heating are performed in such a state of being superposed, and the two substrates 51 and 1 are bonded together by fusion.
- the pressure applied between the superposed glass substrate 1 and the semiconductor substrate 51 is about 98 kPa, and the heating temperature at this time is preferably 500 to 700 ° C. Since the outermost surface film 10 on the semiconductor substrate 51 is made of silicon oxide, by applying pressure and heating under such conditions, the outermost surface film 10 and the surface of the glass substrate 1 are fused and the semiconductor substrate 51 is fused. 51 and the glass substrate 1 are bonded to each other.
- the outermost surface film 10 on the semiconductor substrate 51 which is not the surface of the glass substrate 1 is also clean.
- the power of the PCVD apparatus that has formed the outermost surface film 10 may be improved by performing fusion work immediately after the semiconductor substrate 51 is taken out.
- the stress generated between the semiconductor substrate 51 and the glass substrate 1 due to the difference in the thermal expansion coefficient can be reduced as much as possible, and the reduction in the adhesive strength and the generation of crystal defects due to the stress can be minimized. Can be suppressed.
- the semiconductor substrate 51 is removed. After the glass substrate 1 and the semiconductor substrate 51 are bonded to each other, the other surface (back surface) of the semiconductor substrate 51 is exposed on the opposite side of the glass substrate 1. In this step, the semiconductor substrate 51 and the buffer layer 52 are removed from the back side of the semiconductor substrate 51 by etching.
- the semiconductor substrate 51 and the buffer layer 52 can be etched, the etching rate is reduced with respect to the etching stop layer 53, and the semiconductor substrate 51 and the buffer layer 52 are removed by using an etchant. .
- the etching stopper layer 53 is etched.
- the etching stop layer 53 is removed using an etching solution having a low etching rate for the protective layer 54. Thereby, the glass substrate 1 on which the layer structure LS and the like are stacked is obtained.
- aqueous ammonia (NH OH) and hydrogen peroxide (H 2 O) are used as an etchant to be used.
- the combined glass substrate 1 and semiconductor substrate 51 are immersed in a mixed solution of NH 4 OH and H 2 O.
- the semiconductor substrate 51 is etched from the back side.
- the buffer layer 52 GaAs
- the buffer layer 52 is removed, and the etching stop layer 53 is exposed in the etching solution.
- the etching stop layer 53 (A1 Ga As) has an extremely high etching rate with this etching solution.
- the etching is automatically stopped when the etching stop layer 53 is exposed. Thus, first, the semiconductor substrate 51 and the buffer layer 52 are removed.
- the etching stop layer 53 and the protective layer 54 are removed. Subsequent to the fifth step, the glass substrate 1 on which the etching stop layer 53, the protective layer 54, the layer structure LS, and the like are left is replaced with NH 4 OH.
- the HC1 solution it is preferable to heat the HC1 solution to about 50 ° C in advance to increase the tuning speed. Since GaAs is hardly etched by HC1, only the etching stop layer 53 is etched, and the etching is automatically stopped when the protective layer 54 (GaAs) is exposed (see FIG. 5). Thus, the etching stop layer 53 is removed.
- the protective layer 54 is removed (see FIG. 6).
- the removal of the protective layer 54 is performed by combining NH OH and H 2 O.
- the protective layer 54 is also made of GaAs, the cap layer exposed thereafter is made of an AlGaAs layer! /, So it cannot be etched with this etching solution! /.
- a film 55 made of SiO or SiN is formed on the cap layer 7.
- the film 55 existing at the position where the light receiving region 9 is to be formed is patterned and opened (see FIG. 7). Then, using the film 55 patterned on the cap layer 7 as a mask, impurities (eg, For example, Zn is thermally diffused, and a part of the cap layer 7 is inverted to p-type. Thus, the light receiving region 9 is formed (see FIG. 7). Then, the film 55 is removed by buffered hydrofluoric acid (BHF).
- BHF buffered hydrofluoric acid
- a resist film 56 having an opening at a position where the depression 13 is to be formed is formed on the cap layer 7.
- Photolithography can be used to form the resist film 56.
- a high concentration of the resist film 56 is formed on the cap layer 7.
- a resist film 57 having an opening at a desired position is formed on the cap layer 7.
- Photolithography can be used to form the resist film 57.
- a mixture of Br and methanol is used to expose the anti-reflection film 2 until it is exposed.
- the light receiving section 11, the first pad electrode arrangement section 21 and the second pad electrode arrangement section 31 are electrically separated from each other and formed in a mesa shape (see FIG. 9). That is, the light receiving section 11 includes the high concentration carrier layer 3a, the light absorption layer 5a, and the cap layer 7a, and the first pad electrode arrangement section 21 and the second pad electrode arrangement section 31 include the high concentration carrier layer 3b, the light absorption layer 5b, This will include the cap layer 7b.
- the resist film 57 is made at a position corresponding to the outer portion lib, the progress of etching not only in the depth direction but also in the lateral direction can be appropriately controlled, and the formation of the recess 13 and Further, the light receiving section 11, the first pad electrode arrangement section 21, and the second pad electrode arrangement section 31 can be appropriately separated. As a result, the yield when manufacturing the semiconductor light receiving element PD1 can be increased. Subsequently, the resist film 57 is removed.
- Steps 10-13 are shown below.
- a resist film (not shown) having an opening at a position corresponding to the depression 13 is formed.
- a contact electrode 17 made of Au-GeZNiZAu is formed on the high-concentration carrier layer 3 (3a) exposed by forming the depression 13 by vapor deposition and a lift-off method ( See Figure 10).
- a resist film is formed again so as to have an opening at a position where the contact electrode 15 is to be formed.
- the contact electrode made of Ti-Pt-Au is formed on the light receiving region 9 by vapor deposition and lift-off method. 15 (see also FIG. 10).
- the resist film is removed.
- the contact electrode 15 is formed on the surface of the light receiving region 9 (cap layer 7a), which is a force formed so as to be embedded in the light receiving region 9 (cap layer 7a). You can do it! ,.
- a passivation film 19 having a SiN force is formed on the surface by the PCVD method.
- a resist film (not shown) having openings at positions corresponding to the contact electrodes 15 and 17 is formed, and a contact hole 19a is formed in the passivation film 19 using the resist film as a mask (see FIG. 11). Subsequently, the resist film is removed.
- a resist film (not shown) having openings at positions corresponding to the first pad electrode 23, the second pad electrode 33, the first wiring electrode 43, and the second wiring electrode 45 is formed. Then, using this resist film as a mask, a first pad electrode 23, a second pad electrode 33, a first wiring electrode 43, and a second wiring electrode 45 made of Ti Pt Au are formed by a lift-off method (FIG. 12). reference). At this time, the first wiring electrode 43 is formed so as to cover the light receiving region 9. Here, the first pad electrode 23 and the first wiring electrode 43 are formed integrally, and the second pad electrode 33 and the second wiring electrode 45 are formed integrally. Subsequently, the resist film is removed. Then sinter in H atmosphere.
- the semiconductor photodetector PD 1 having the configuration shown in FIGS. 1 and 2 is completed by the first to thirteenth steps.
- the bump electrode 41 can be obtained by forming a solder on the first pad electrode 23 and the second pad electrode 33 by a plating method, a solder ball mounting method, or a printing method, and performing reflow. Further, the bump electrode 41 is not limited to solder, but may be a conductive resin bump containing a metal such as a conductive bumper such as a gold bump, a nickel bump, or a copper bump.
- the layer structure LS stacked The mechanical strength of the high-concentration carrier layer 3, the light absorbing layer 5 and the cap layer 7) thus obtained is maintained by the glass substrate 1.
- the conventional semiconductor light receiving element As described above, it is possible to easily reduce the size of the semiconductor light receiving element PD1, which does not require the formation of a portion with the remaining substrate thickness.
- the layer structure LS is bonded to the glass substrate 1 via the film 10
- the layer structure LS and the glass substrate 1 are bonded to each other with an adhesive. Adhesion can be performed without using such a method. Therefore, the light that has also entered the glass substrate 1 side force can reach the layer structure LS without being absorbed by the adhesive or the like.
- the antireflection film 2 is formed between the film 10 and the high concentration carrier layer 3 (3a). Thereby, reflection of light that is going to be incident on the light receiving region 9 is prevented, and light incident on the light absorbing layer is increased, so that light sensitivity can be improved.
- the first wiring electrode 43 (light reflection film) is formed so as to cover the light receiving region 9, so that the light passes through the light absorption layer once without being absorbed.
- the light reflected from the first wiring electrode 43 is also incident on the light absorbing layer 5a again and absorbed. Thereby, the light sensitivity can be improved.
- the layer structure LS is formed in the light receiving section 11, the first pad electrode arrangement section 21, and the second pad electrode arrangement section 31.
- a depression 13 reaching the high-concentration carrier layer 3a is formed, and the first wiring electrode 43 extends between the light receiving section 11 and the first pad electrode arrangement section 21 to form the light receiving section 11 and the first 1
- the second wiring electrode 45 is formed along the side surface of the pad electrode disposition portion 21, and the second wiring electrode 45 extends between the depression portion 13 and the second pad electrode disposition portion 31, the concave portion 13 and the light receiving portion 11. And, it is formed along the side surface of the second pad electrode arrangement portion 31.
- the high concentration carrier layer 3a of the light receiving section 11 and the second pad electrode 33 are electrically connected to the second pad electrode 33 through the recess 13 formed so as to reach the high concentration carrier layer 3a of the light receiving section 11.
- the electrode is directly drawn out from the high-concentration carrier layer 3a of the light receiving section 11, and the series resistance can be significantly reduced.
- a semiconductor light receiving element PD1 having excellent high-speed response characteristics can be realized.
- the CR product which indicates the degree of signal transmission impairment, increases.
- the series resistance is greatly reduced as described above, the CR product is reduced. For this reason, if the CR product is maintained at the same level, that is, the high-speed response characteristics are maintained at the same level, the area of the light receiving region 9 is increased by adopting the semiconductor light receiving element according to this embodiment. be able to.
- each of the first pad electrode disposition portion 21 and the second pad electrode disposition portion 31 includes the high concentration carrier layer 3b, the light absorption layer 5b, and the cap layer. 7b, the first pad electrode 23 and the second pad electrode 33 can be easily arranged at the same height, and the semiconductor light receiving element PD1 can be mounted by bump bonding.
- the second pad electrode arranging part 31 which is not limited to the first pad electrode arranging part 21 is also separated from the light receiving part 11, so that the light receiving part 11 (receiving The distance between the light region 9) and the first pad electrode 23 and the distance between the light receiving section 11 (light receiving region 9) and the second pad electrode 33 are relatively wide.
- the electrodes are directly drawn from the high-concentration carrier layer 3a as described above, the series resistance is greatly reduced even when the wiring length is long.
- the recess 13 is formed in a groove shape so as to surround the light receiving region 9. Thereby, the connection area between the high-concentration carrier layer 3a of the light receiving section 11 and the second wiring electrode 45 (contact electrode 17) is increased, and the series resistance can be further reduced.
- the bump electrode 41 is disposed on the first pad electrode 23 and the second nod electrode 33. As a result, the semiconductor light receiving element PD1 that does not increase the wiring resistance can be mounted.
- the silicon oxide film 10 formed on the outermost surface side of the layer structure LS is in contact with one surface of the glass substrate 1.
- the semiconductor substrate 51 is removed, so that the glass substrate 1 is provided on the light incident surface side of the layer structure LS via the film 10.
- the semiconductor light receiving element PD1 to which is adhered can be easily manufactured.
- the glass substrate 1 exists even after the semiconductor substrate 51 has been removed. It will be held by the substrate 1. Before the glass substrate 1 is bonded, the mechanical strength of the layer structure LS is maintained by the semiconductor substrate 51.
- the etching stop layer is performed before the step of forming the layer structure LS (the stacked high-concentration carrier layer 3, the light absorption layer 5, and the cap layer 7).
- an etching solution that can etch the semiconductor substrate 51 and cannot etch the etching stop layer 53 and an etching solution that can etch the etching stop layer 53 and cannot etch the layer structure LS.
- the semiconductor substrate 51 can be removed, and thereafter, only the etching stop layer 53 can be removed. Therefore, the semiconductor substrate 51 can be reliably and easily removed while leaving the layer structure LS.
- the step of forming the protective layer 54 so as to be located between the etching stop layer 53 and the layer structure LS is performed after the step of forming the etching stop layer 53. It has.
- the layer structure LS (the stacked high-concentration carrier layer 3, light-absorbing layer 5, and cap layer 7) can be reliably prevented from being contaminated by the etchant.
- FIG. 13 is a view for explaining a sectional configuration of a second embodiment of the semiconductor light receiving element according to the present invention.
- the semiconductor light receiving element PD2 according to the second embodiment differs from the semiconductor light receiving element PD1 according to the first embodiment in that a lens portion la is formed on the glass substrate 1.
- the semiconductor light receiving element PD2 includes a layer structure LS and a glass substrate 1.
- the semiconductor light receiving element PD2 is a back-illuminated semiconductor light receiving element in which light is incident on the glass substrate 1 side layered structure LS.
- the semiconductor light receiving element PD2 is, for example, a light receiving element for short-range optical communication in a wavelength band of 0.85 m.
- the glass substrate 1 is provided with a lens portion la for condensing incident light.
- This lens part 1 a is formed to be depressed from the outermost surface lb of the glass substrate 1.
- FIGS. FIG. 14 to FIG. 16 are explanatory views for explaining the method for manufacturing the semiconductor light receiving element according to the second embodiment, and show the longitudinal sectional structure of the semiconductor light receiving element.
- first step to thirteenth step are sequentially performed.
- first to third steps in the second embodiment are the same as the first to third steps in the above-described first embodiment, and a description thereof will be omitted.
- the semiconductor substrate 51 on which the layer structure LS and the films 52 to 54 and 10 are formed is bonded to the glass substrate 1 (see FIG. 14).
- a glass substrate 1 on which a lens portion la is formed is prepared, and one surface (front surface) of the glass substrate 1 is cleaned.
- the glass substrate 1 and the semiconductor substrate 51 are overlapped so that the cleaned surface of the glass substrate 1 and the outermost surface film 10 are in contact with each other. Pressing and heating are performed in the state of being overlapped in this way, and both substrates 51 and 1 are bonded together by fusion.
- the bonding method between the semiconductor substrate 51 and the glass substrate 1 is the same as the bonding method in the fourth step in the first embodiment.
- the semiconductor substrate 51, the buffer layer 52, the etching stop layer 53, and the protective layer 54 are removed (see FIG. 15).
- the method of removing the semiconductor substrate 51, the buffer layer 52, the etching stop layer 53, and the protective layer 54 is the same as the removal method in the fifth and sixth steps in the first embodiment.
- a film 55 made of SiO or SiN is formed on the cap
- the film 55 existing at the position where the film 9 is to be formed is patterned and opened (see FIG. 16).
- a marker is provided on the front surface side of the glass substrate 1 and a double-sided exposure machine is used, so that the lens portion la and the position where the light receiving area 9 is to be formed can be easily matched with reference to the provided marker. be able to.
- the outer shape of the lens section la may be used as a marker.
- impurities for example, Z n
- BHF buffered hydrofluoric acid
- the eighth to thirteenth steps in the second embodiment are the same as the eighth to thirteenth steps in the first embodiment, and a description thereof will be omitted.
- the semiconductor light receiving element PD2 having the configuration shown in FIG. 13 is completed.
- the mechanical structure of the layer structure LS (the stacked high-concentration carrier layer 3, the light absorption layer 5, and the cap layer 7) is formed.
- the mechanical strength is maintained by the glass substrate 1, and the size of the semiconductor light receiving element PD2 can be easily reduced.
- the glass substrate 1 is provided with a lens portion la.
- the incident light can be efficiently collected.
- a semiconductor light receiving element PD2 having an excellent SN ratio and high reliability can be obtained.
- the lens portion la is formed so as to be depressed from the outermost surface lb of the glass substrate 1.
- the glass substrate 1 on which the lens portion la is formed can be easily bonded.
- the degree of freedom in designing the lens shape and the like is increased without being limited by the processing method and the like.
- the lens portion la may be formed after the semiconductor substrate 51 on which the layer structure LS and the films 52-54 and 10 are formed and the glass substrate 1 are bonded. While taking into account the degree of freedom in designing the lens shape and the like, it is preferable that the glass substrate 1 on which the lens portion la is formed in advance be bonded to the semiconductor substrate 51.
- FIG. 17 is a view for explaining a cross-sectional structure of a third embodiment (array structure) of the semiconductor light receiving element according to the present invention.
- FIG. 18 is a view showing a fourth embodiment of the semiconductor light receiving element according to the present invention.
- FIG. 3 is a diagram for explaining a cross-sectional structure of (array structure).
- the semiconductor light receiving element arrays PD3 and PD4 according to the third and fourth embodiments are so-called back illuminated semiconductor light receiving element arrays. As shown in FIG.
- the semiconductor light-receiving element arrays PD3 and PD4 each have a plurality of light-receiving portions 11 arranged in a one-dimensional or two-dimensional direction and arranged in a plurality in an array. ing.
- the first pad electrode arrangement part 21 and the second pad electrode arrangement part 31 respectively corresponding to the adjacent light receiving parts 11 are integrated and formed in a mesa shape. .
- the second pad electrodes 33 are electrically connected to each other.
- the mechanical structure of the layer structure LS (the stacked high-concentration carrier layer 3, the light absorption layer 5, and the cap layer 7) is used.
- the mechanical strength is maintained by the glass substrate 1.
- the pitch of the light receiving section 11 (light receiving area 9) can be narrowed, and the miniaturization (compactness) of the semiconductor light receiving element arrays PD3 and PD4 can be easily achieved.
- FIG. 19 is a diagram showing a schematic configuration of an optical interconnection system to which the semiconductor light receiving element according to the present invention can be applied.
- the optical interconnection system 101 is a system for transmitting a signal between a plurality of modules (for example, a CPU, an integrated circuit chip, and a memory) Ml and M2 by light, and includes a semiconductor light emitting element 103, a driving circuit 105 , An optical waveguide substrate 107, a semiconductor light receiving element PD1, an amplification circuit 109, and the like.
- the semiconductor light emitting element 103 can use a vertical cavity surface emitting laser (VCSEL) of a back emission type.
- the module Ml and the drive circuit 105 are electrically connected through bump electrodes and the like.
- the semiconductor light emitting element 103 and the drive circuit 105 are electrically connected through a bump electrode.
- the semiconductor light receiving element PD1 and the amplifier circuit 109 are electrically connected through the bump electrode 41.
- the amplifier circuit 109 and the module M2 are electrically connected through bump electrodes and the like.
- the electric signal output from the module Ml is sent to the drive circuit 105, converted into an optical signal by the semiconductor light emitting element 103, and output.
- the optical signal output from the semiconductor light emitting element 103 passes through the optical waveguide 107a of the optical waveguide substrate 107 and enters the semiconductor light receiving element PD1. Power.
- the optical signal input to the semiconductor light receiving element PD1 is converted into an electric signal, sent to the amplifier circuit 109, and amplified.
- the amplified electric signal is sent to the module M2. As described above, the electric signal output from the module Ml is transmitted to the module M2.
- the semiconductor light receiving element PD2 or the semiconductor light receiving element arrays PD3 and PD4 may be used instead of the semiconductor light receiving element PD1.
- the semiconductor light emitting element 103, the drive circuit 105, the optical waveguide substrate 107, and the amplifier circuit 109 are also arrayed.
- the present invention is not limited to the above embodiments.
- the thickness of the semiconductor substrate 51, the high concentration carrier layer 3 (3a, 3b), the light absorption layer 5 (5a, 5b), the cap layer 7 (7a, 7b), etc., and the materials used are limited to those described above. Absent.
- Si, InP, InGaAs, InSb, and InAsSb may be used instead of the above-mentioned GaAs.
- the shape of the recess 13 is not limited to the above-described groove surrounding the light receiving region, but may be any shape having a depth reaching the high concentration carrier layer 3a. May be. Of course, the depression 13 need not be formed.
- the force for integrally molding the first pad electrode 23 and the first wiring electrode 43 and for integrally molding the second pad electrode 33 and the second wiring electrode 45 is not limited to this. Each of them can be formed separately.
- the light receiving unit 11 After forming the recess 13, the light receiving unit 11, the first pad electrode arrangement unit 21, and the second pad electrode arrangement unit 31 are separated. After separating the light receiving section 11, the first pad electrode arrangement section 21 and the second pad electrode arrangement section 31, the depression section 13 may be formed.
- the semiconductor element according to the present invention transmits signals within a system device and between devices by light. Applicable to optical interconnection technology and the like.
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Optics & Photonics (AREA)
- Light Receiving Elements (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP04819834A EP1693902A1 (en) | 2003-12-04 | 2004-11-30 | Semiconductor light-receiving device and method for manufacturing same |
US10/581,081 US7834413B2 (en) | 2003-12-04 | 2004-11-30 | Semiconductor photodetector and method of manufacturing the same |
KR1020067007768A KR101092147B1 (ko) | 2003-12-04 | 2004-11-30 | 반도체 수광 소자 및 그 제조 방법 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003-406396 | 2003-12-04 | ||
JP2003406396A JP2005167090A (ja) | 2003-12-04 | 2003-12-04 | 半導体受光素子及びその製造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2005055327A1 true WO2005055327A1 (ja) | 2005-06-16 |
Family
ID=34650252
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2004/017798 WO2005055327A1 (ja) | 2003-12-04 | 2004-11-30 | 半導体受光素子及びその製造方法 |
Country Status (7)
Country | Link |
---|---|
US (1) | US7834413B2 (ja) |
EP (1) | EP1693902A1 (ja) |
JP (1) | JP2005167090A (ja) |
KR (1) | KR101092147B1 (ja) |
CN (1) | CN100466301C (ja) |
TW (1) | TWI363427B (ja) |
WO (1) | WO2005055327A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2895566A1 (fr) * | 2005-12-23 | 2007-06-29 | Atmel Grenoble Soc Par Actions | Capteur d'image aminci a plots de contact isoles par tranchee |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
MX2007016556A (es) * | 2005-06-30 | 2008-03-07 | Agc Flat Glass Na Inc | Dispositivo y metodo para la percepcion monoltica de imagenes. |
US8478081B2 (en) | 2005-06-30 | 2013-07-02 | Agc Flat Glass North America, Inc. | Monolithic image perception device and method |
JP5005227B2 (ja) * | 2006-02-01 | 2012-08-22 | 浜松ホトニクス株式会社 | 光検出素子、及び光検出素子の製造方法 |
JP5386862B2 (ja) * | 2008-06-18 | 2014-01-15 | 信越半導体株式会社 | 半導体装置の製造方法 |
JP2011165848A (ja) * | 2010-02-09 | 2011-08-25 | Hitachi Ltd | 面入射型フォトダイオード |
CN102779892B (zh) * | 2011-05-10 | 2015-01-21 | 中国科学院上海微系统与信息技术研究所 | 基于异质集成和垂直光耦合的硅基InGaAs PIN光电探测器 |
US10790407B2 (en) * | 2014-08-06 | 2020-09-29 | The Boeing Company | Fabrication of sensor chip assemblies with microoptics elements |
FR3026891A1 (fr) * | 2014-10-06 | 2016-04-08 | St Microelectronics Crolles 2 Sas | Dispositif d'imagerie integre a illumination face arriere avec routage d'interconnexion simplifie |
JP6903896B2 (ja) * | 2016-01-13 | 2021-07-14 | ソニーグループ株式会社 | 受光素子の製造方法 |
JP6884948B2 (ja) * | 2017-03-17 | 2021-06-09 | 国立研究開発法人情報通信研究機構 | 高速フォトディテクターアレー |
JP7361490B2 (ja) * | 2019-05-07 | 2023-10-16 | 日本ルメンタム株式会社 | 半導体受光素子及び半導体受光素子の製造方法 |
FR3100658A1 (fr) * | 2019-09-10 | 2021-03-12 | Stmicroelectronics (Crolles 2) Sas | Dispositif électronique comprenant des composants optiques et électroniques intégrés et procédé de fabrication |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60101929A (ja) * | 1983-10-19 | 1985-06-06 | エヌ・ベー・フイリツプス・フルーイランペンフアブリケン | 透明な半導体支持構体 |
JPS63161680A (ja) * | 1986-12-25 | 1988-07-05 | Mitsubishi Electric Corp | 半導体受光素子 |
JPH0595130A (ja) * | 1991-10-01 | 1993-04-16 | Nippon Telegr & Teleph Corp <Ntt> | 半導体受光装置 |
JPH05102513A (ja) * | 1991-10-04 | 1993-04-23 | Nikko Kyodo Co Ltd | 半導体受光素子 |
JPH05267708A (ja) * | 1992-03-19 | 1993-10-15 | Fujitsu Ltd | 光半導体装置の電極構造 |
JPH05291604A (ja) * | 1992-04-07 | 1993-11-05 | Oki Electric Ind Co Ltd | 半導体受光素子及びその製造方法 |
JPH0677518A (ja) * | 1992-08-26 | 1994-03-18 | Nec Corp | 半導体受光素子 |
JP2002231992A (ja) * | 2001-02-02 | 2002-08-16 | Toshiba Corp | 半導体受光素子 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03104287A (ja) | 1989-09-19 | 1991-05-01 | Fujitsu Ltd | 半導体受光素子の製造方法 |
JPH0537004A (ja) | 1991-07-25 | 1993-02-12 | Sumitomo Electric Ind Ltd | 受光素子 |
JPH05152551A (ja) | 1991-11-27 | 1993-06-18 | Sanyo Electric Co Ltd | 固体撮像素子の製造方法 |
JPH06296035A (ja) | 1993-04-07 | 1994-10-21 | Nippon Telegr & Teleph Corp <Ntt> | 光検出器及びその製造方法 |
JPH06326293A (ja) | 1993-05-12 | 1994-11-25 | Hamamatsu Photonics Kk | 光検出装置 |
ATE313857T1 (de) * | 1995-05-19 | 2006-01-15 | Heidenhain Gmbh Dr Johannes | Strahlungsempfindliches detektorelement |
JP3924352B2 (ja) | 1997-06-05 | 2007-06-06 | 浜松ホトニクス株式会社 | 裏面照射型受光デバイス |
JP3956647B2 (ja) | 2001-05-25 | 2007-08-08 | セイコーエプソン株式会社 | 面発光レ−ザの製造方法 |
-
2003
- 2003-12-04 JP JP2003406396A patent/JP2005167090A/ja active Pending
-
2004
- 2004-11-30 WO PCT/JP2004/017798 patent/WO2005055327A1/ja active Application Filing
- 2004-11-30 KR KR1020067007768A patent/KR101092147B1/ko not_active IP Right Cessation
- 2004-11-30 CN CNB2004800253245A patent/CN100466301C/zh not_active Expired - Fee Related
- 2004-11-30 EP EP04819834A patent/EP1693902A1/en not_active Withdrawn
- 2004-11-30 US US10/581,081 patent/US7834413B2/en not_active Expired - Fee Related
- 2004-12-02 TW TW093137191A patent/TWI363427B/zh not_active IP Right Cessation
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60101929A (ja) * | 1983-10-19 | 1985-06-06 | エヌ・ベー・フイリツプス・フルーイランペンフアブリケン | 透明な半導体支持構体 |
JPS63161680A (ja) * | 1986-12-25 | 1988-07-05 | Mitsubishi Electric Corp | 半導体受光素子 |
JPH0595130A (ja) * | 1991-10-01 | 1993-04-16 | Nippon Telegr & Teleph Corp <Ntt> | 半導体受光装置 |
JPH05102513A (ja) * | 1991-10-04 | 1993-04-23 | Nikko Kyodo Co Ltd | 半導体受光素子 |
JPH05267708A (ja) * | 1992-03-19 | 1993-10-15 | Fujitsu Ltd | 光半導体装置の電極構造 |
JPH05291604A (ja) * | 1992-04-07 | 1993-11-05 | Oki Electric Ind Co Ltd | 半導体受光素子及びその製造方法 |
JPH0677518A (ja) * | 1992-08-26 | 1994-03-18 | Nec Corp | 半導体受光素子 |
JP2002231992A (ja) * | 2001-02-02 | 2002-08-16 | Toshiba Corp | 半導体受光素子 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2895566A1 (fr) * | 2005-12-23 | 2007-06-29 | Atmel Grenoble Soc Par Actions | Capteur d'image aminci a plots de contact isoles par tranchee |
Also Published As
Publication number | Publication date |
---|---|
TW200531300A (en) | 2005-09-16 |
US20070284685A1 (en) | 2007-12-13 |
CN100466301C (zh) | 2009-03-04 |
TWI363427B (en) | 2012-05-01 |
KR20060115997A (ko) | 2006-11-13 |
JP2005167090A (ja) | 2005-06-23 |
CN1846314A (zh) | 2006-10-11 |
US7834413B2 (en) | 2010-11-16 |
KR101092147B1 (ko) | 2011-12-12 |
EP1693902A1 (en) | 2006-08-23 |
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