WO2005050701A3 - Structures contraintes de dispositif a semi-conducteur comprenant un materiau semi-conducteur granulaire - Google Patents
Structures contraintes de dispositif a semi-conducteur comprenant un materiau semi-conducteur granulaire Download PDFInfo
- Publication number
- WO2005050701A3 WO2005050701A3 PCT/US2004/037434 US2004037434W WO2005050701A3 WO 2005050701 A3 WO2005050701 A3 WO 2005050701A3 US 2004037434 W US2004037434 W US 2004037434W WO 2005050701 A3 WO2005050701 A3 WO 2005050701A3
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- WIPO (PCT)
- Prior art keywords
- semiconductor material
- semiconductor device
- device structures
- stressed
- granular
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title abstract 5
- 239000000463 material Substances 0.000 title abstract 3
- 239000000758 substrate Substances 0.000 abstract 2
- 238000000137 annealing Methods 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 abstract 1
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- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors
- H01L31/115—Devices sensitive to very short wavelength, e.g. X-rays, gamma-rays or corpuscular radiation
- H01L31/119—Devices sensitive to very short wavelength, e.g. X-rays, gamma-rays or corpuscular radiation characterised by field-effect operation, e.g. MIS type detectors
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- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
Abstract
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006539779A JP4843498B2 (ja) | 2003-11-14 | 2004-11-09 | 半導体デバイス構造を製造する方法 |
AT04810633T ATE512465T1 (de) | 2003-11-14 | 2004-11-09 | Verspannte halbleiter-einrichtungsstrukturen mit granularem halbleitermaterial |
EP04810633A EP1683187B1 (fr) | 2003-11-14 | 2004-11-09 | Structures contraintes de dispositif a semi-conducteur comprenant un materiau semi-conducteur granulaire |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/707,018 US7122849B2 (en) | 2003-11-14 | 2003-11-14 | Stressed semiconductor device structures having granular semiconductor material |
US10/707,018 | 2003-11-14 |
Publications (3)
Publication Number | Publication Date |
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WO2005050701A2 WO2005050701A2 (fr) | 2005-06-02 |
WO2005050701A8 WO2005050701A8 (fr) | 2005-11-03 |
WO2005050701A3 true WO2005050701A3 (fr) | 2006-01-05 |
Family
ID=34573430
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2004/037434 WO2005050701A2 (fr) | 2003-11-14 | 2004-11-09 | Structures contraintes de dispositif a semi-conducteur comprenant un materiau semi-conducteur granulaire |
Country Status (7)
Country | Link |
---|---|
US (2) | US7122849B2 (fr) |
EP (1) | EP1683187B1 (fr) |
JP (1) | JP4843498B2 (fr) |
KR (1) | KR100946038B1 (fr) |
CN (1) | CN100468785C (fr) |
AT (1) | ATE512465T1 (fr) |
WO (1) | WO2005050701A2 (fr) |
Families Citing this family (59)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10245153A1 (de) * | 2002-09-27 | 2004-04-15 | Infineon Technologies Ag | Integrierter Feldeffekttransistor mit zwei Steuerbereichen, Verwendung dieses Feldeffekttranistors und Herstellungsverfahren |
JP4085891B2 (ja) * | 2003-05-30 | 2008-05-14 | ソニー株式会社 | 半導体装置およびその製造方法 |
US7410846B2 (en) * | 2003-09-09 | 2008-08-12 | International Business Machines Corporation | Method for reduced N+ diffusion in strained Si on SiGe substrate |
US6887751B2 (en) | 2003-09-12 | 2005-05-03 | International Business Machines Corporation | MOSFET performance improvement using deformation in SOI structure |
US6872641B1 (en) * | 2003-09-23 | 2005-03-29 | International Business Machines Corporation | Strained silicon on relaxed sige film with uniform misfit dislocation density |
US7144767B2 (en) * | 2003-09-23 | 2006-12-05 | International Business Machines Corporation | NFETs using gate induced stress modulation |
US7119403B2 (en) * | 2003-10-16 | 2006-10-10 | International Business Machines Corporation | High performance strained CMOS devices |
US7303949B2 (en) * | 2003-10-20 | 2007-12-04 | International Business Machines Corporation | High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture |
US7037770B2 (en) * | 2003-10-20 | 2006-05-02 | International Business Machines Corporation | Method of manufacturing strained dislocation-free channels for CMOS |
US7129126B2 (en) * | 2003-11-05 | 2006-10-31 | International Business Machines Corporation | Method and structure for forming strained Si for CMOS devices |
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US7029964B2 (en) | 2003-11-13 | 2006-04-18 | International Business Machines Corporation | Method of manufacturing a strained silicon on a SiGe on SOI substrate |
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- 2004-11-09 EP EP04810633A patent/EP1683187B1/fr not_active Not-in-force
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- 2004-11-09 WO PCT/US2004/037434 patent/WO2005050701A2/fr active Application Filing
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Also Published As
Publication number | Publication date |
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US7488658B2 (en) | 2009-02-10 |
US20080064172A1 (en) | 2008-03-13 |
EP1683187A2 (fr) | 2006-07-26 |
US7122849B2 (en) | 2006-10-17 |
ATE512465T1 (de) | 2011-06-15 |
KR20070015499A (ko) | 2007-02-05 |
WO2005050701A2 (fr) | 2005-06-02 |
JP4843498B2 (ja) | 2011-12-21 |
JP2007511909A (ja) | 2007-05-10 |
EP1683187B1 (fr) | 2011-06-08 |
CN1879227A (zh) | 2006-12-13 |
CN100468785C (zh) | 2009-03-11 |
WO2005050701A8 (fr) | 2005-11-03 |
KR100946038B1 (ko) | 2010-03-09 |
US20050106799A1 (en) | 2005-05-19 |
EP1683187A4 (fr) | 2008-08-27 |
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