WO2005033949A1 - Dispositif a memoire a semi-conducteur - Google Patents

Dispositif a memoire a semi-conducteur Download PDF

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Publication number
WO2005033949A1
WO2005033949A1 PCT/JP2004/014905 JP2004014905W WO2005033949A1 WO 2005033949 A1 WO2005033949 A1 WO 2005033949A1 JP 2004014905 W JP2004014905 W JP 2004014905W WO 2005033949 A1 WO2005033949 A1 WO 2005033949A1
Authority
WO
WIPO (PCT)
Prior art keywords
program
memory device
semiconductor memory
rom
extension
Prior art date
Application number
PCT/JP2004/014905
Other languages
English (en)
Japanese (ja)
Inventor
Masahiro Nakanishi
Tomoaki Izumi
Tetsushi Kasahara
Kazuaki Tamura
Kiminori Matsuno
Original Assignee
Matsushita Electric Industrial Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co., Ltd. filed Critical Matsushita Electric Industrial Co., Ltd.
Publication of WO2005033949A1 publication Critical patent/WO2005033949A1/fr

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1415—Saving, restoring, recovering or retrying at system level
    • G06F11/1441—Resetting or repowering
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1415—Saving, restoring, recovering or retrying at system level
    • G06F11/1417—Boot up procedures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1479—Generic software techniques for error detection or fault masking
    • G06F11/1482—Generic software techniques for error detection or fault masking by means of middleware or OS functionality

Definitions

  • the present invention relates to a memory device using a non-volatile semiconductor memory, and more specifically, a control program is divided and stored in a mask ROM in the semiconductor memory device and a part of the recordable non-volatile memory.
  • Semiconductor memory device using a non-volatile semiconductor memory, and more specifically, a control program is divided and stored in a mask ROM in the semiconductor memory device and a part of the recordable non-volatile memory.
  • Japanese Unexamined Patent Publication No. Hei 11-94855 discloses a read-only memory (hereinafter, referred to as a ROM) including a mask ROM and the like, and an EEPROM, which is a main storage unit of the semiconductor memory device.
  • a technique is disclosed in which a control program is divided and stored in different areas.
  • FIG. 1 is a block diagram showing a configuration of a conventional semiconductor memory device as described above.
  • This semiconductor memory device is connected to the host system 501.
  • This semiconductor memory device has a controller 502A and an EEPROM 503 as modules.
  • the controller 502A is a module having a host interface 504, a CPU 505, a RAM 506, an EEPROM interface 507, and a ROM 508.
  • the RAM 506 is a memory that can be written and read at any time.
  • the ROM 508 is a read-only mask memory that holds the program FW1.
  • the ROM 508 also holds a main program and a transfer program for transferring the extension program FW2 recorded in the EEPROM 503 to the controller 502A.
  • Extension program FW2 is semi-conductive This is a program added according to the function expansion of the body memory device.
  • the program FW1 held in the ROM 508 includes a transfer program for transferring the extension program FW2 in the EEPROM 503 to the RAM 506 in addition to the original main program.
  • the EPROM 503 is a module including a programmable ROM that can be electrically recorded and erased, and is connected to the controller 502A via a memory bus.
  • the EEPROM 503 stores general data input from the host system 501, and also stores an extension program FW2 in a partial area 509.
  • the CPU 505 executes the transfer program for the EEPROM 507.
  • the CPU 505 activates a transfer program in the program FW1 stored in the ROM 508.
  • the extension program FW2 stored in the area 509 of the EEPROM 503 is read and transferred to the RAM 506 via the EEPROM interface 507.
  • the CPU 505 controls the controller 502A by using the main program stored in the ROM 508 and the extension program FW2 transferred to the RAM 506.
  • the controller 502A reads data from the EEPROM 503 via the host interface 504 and the EEPROM interface 507 in response to a data read / write instruction from the host system 501, or reads data from the EEPROM 503. Is written.
  • the program as the semiconductor memory device is divided into the program FW1 and the extension program FW2. Then, by retaining the extension program FW2 in the area 509 of the EEPROM 503, the function of the semiconductor memory device can be extended only by rewriting the extension program FW2 in the area 509 (for example, (Purging up) can be executed in a short period of time.
  • FIG. 2 is a configuration diagram of a nonvolatile memory array built in the EEPROM 503.
  • a global bit line A (abbreviated as GBL-A in the drawing) is connected to a local bit line (LBL) via a select transistor Tr.A and a select transistor Tr.C.
  • a single bit line (LBL) is connected from the global pit line B (GBL-B) via a selection transistor Tr.B and a selection transistor Tr.D.
  • a large number of memory cells are connected in matrix form to the local bit lines.
  • the memory cell in the bit line direction is selected by the selection transistor Tr, and one memory cell on the bit line is selected by selecting one gate line at the same time.
  • 256 memory cells are connected in parallel per bit line per bit line. Note that a unit of one bit line is called one string.
  • an assist gate AG-E is connected to the gate of the assist transistor ATr in the odd-numbered column
  • an assist gate AG- ⁇ is connected to the gate of the assist transistor ATr in the even-numbered column.
  • a positive potential is applied to the word line, and whether the data value is 0 or 1 is determined based on the presence or absence of a current flowing in the memory cell.
  • a positive voltage is applied to each gate of the selection transistor Tr.A and the selection transistor Tr.D, and a positive voltage is applied to the word line A.
  • the selection transistor Tr.B and the selection transistor The potential of the transistors Tr, C and the unselected word lines is 0 V.
  • a positive voltage is applied to assist gate AG-E, and 0 V is applied to assist gate AG- AG. In this state, the memory cell MA is selected, and the memory cell MB is not selected.
  • an electric potential is applied to a drain of the memory cell, and data in the memory cell is determined based on whether or not a current flows.
  • a potential is applied to the global bit line GBL-B, and the memory cell MA and the selection transistor Tr are passed through the selection transistor Tr.D. Determine whether or not current flows through the path A. This current value depends on the threshold voltage (hereinafter, referred to as Vth) of the memory cell.
  • Vth threshold voltage
  • a semiconductor memory device includes a memory module including a nonvolatile memory capable of electrically erasing and recording data, a controller module performing control for reading and writing data in a nonvolatile memory, and a program holding a program. And a read-only ROM to read.
  • the controller module includes a RAM that can be written and read at any time, and a CPU that controls the operation of the controller module based on the ROM and a program stored in the RAM.
  • the program processed by the CPU includes an extension program in addition to the main program for operating the controller module, the main program is recorded in ROM, and the extension program is stored in a part of the memory module.
  • a restoration program for restoring the abnormal state of the nonvolatile memory and a transfer program for transferring the extension program to the RAM are recorded in the ROM.
  • FIG. 1 is a block diagram showing a structural example of a conventional semiconductor memory device.
  • FIG. 2 is a configuration diagram of an EEPROM memory array used in a semiconductor memory device.
  • FIG. 3 is a block diagram showing a configuration of the semiconductor memory device according to the first embodiment of the present invention.
  • FIG. 4 is a flowchart showing an execution procedure of the CPU in the controller after the device is started.
  • FIG. 5 is a block diagram showing a configuration of a semiconductor memory device according to Embodiment 2 of the present invention. BEST MODE FOR CARRYING OUT THE INVENTION
  • FIG. 3 is a block diagram showing the configuration of the semiconductor memory device according to the present embodiment.
  • This semiconductor memory device is connected to the host system 501.
  • This semiconductor memory device is configured to include a controller 502B and an EPROM 503. These functional blocks are
  • the controller 502B has a host interface 504, a CPU 505, a RAM 506, an EPROM interface 507, and a ROM 101 in the same module. Therefore, the controller 502B is also called a controller module.
  • the ROM 101 is a read-only memory and holds the program FW1.
  • the program FW1 includes a main program, a transfer program for transferring the extension program FW2 recorded in the EEPROM 503 to the controller 502B, and a recovery program for the EEPROM 503.
  • EEPROM 503 is one of the nonvolatile memories.
  • the area 102 of the EEPROM 503 is a partial memory area of the EEPROM, and stores the program F This area stores the extension program FW2 other than Wl.
  • General data input from the host system 501 is recorded in another area of the EE PROM 503.
  • the functions of the other blocks are the same as those of the conventional semiconductor memory device.
  • the configuration of the nonvolatile memory array built in the EEPROM 503 is the same as that shown in FIG.
  • FIG. 4 is a flowchart showing an execution procedure of the CPU 505 immediately after the startup of the semiconductor memory device.
  • the device starts.
  • the program FW1 in the ROM 101 is read and the controller 502B is started.
  • the process proceeds to step S3 to search for a memory cell in which Vth has become negative due to power-off during erasing or the like, and forcibly set the transistor of the memory cell in which Vth has become negative to a positive potential. By doing so, a leak current can be prevented, and as a result, erroneous reading can be avoided.
  • This process is executed by the recovery program (Step S3) that restores the EEPROM in the program FW1.
  • step S4 the process proceeds to step S4 to check whether the search has been completed for all transistors. If not completed, return to step S3 and repeat this process.
  • step S5 the transfer program stored in ROM 101. That is, the extension program FW2 is transferred from the EEPROM 503 to the RAM 506 via the EEPROM interface 507.
  • step S6 the process proceeds to a normal processing loop.
  • a dedicated control circuit may be incorporated in the module of the controller 502B or the module including the EEPROM 503, and the control circuit may transfer the extension program FW2.
  • the working RAM of the CPU 505 is built in the CPU 505 itself.
  • FIG. 5 is a block diagram showing a configuration of the semiconductor memory device according to the second embodiment.
  • the same parts as those in the first embodiment are denoted by the same reference numerals, and the description of the functions will be omitted.
  • the controller 502C is a controller module having a host interface 504, a CPU 505, a RAM 506, an EPROM interface 507, and a ROM 508.
  • a CPU 203 and a ROM 204 as a control unit are provided in addition to an EE PROM 202 which is a non-volatile memory array.
  • the ROM section 204 stores an EPROM recovery program.
  • an area 205 of the extension program FW2 is provided in the EE PROM section 202.
  • a dedicated control circuit may be built in the controller 502C or the EEPROM 201, and the control circuit may transfer the extension program FW2.
  • the working RAM of the CPU 505 is assumed to be built in the CPU 505 itself.
  • the CPU 505 starts processing when the recovery processing by the recovery program stored in the ROM unit 204 is completed, and the expansion program FW2 Transfer to the RAM 506, the operation by the extension program FW2 can be executed.
  • the semiconductor memory device of the present invention can be used for purging in addition to recording general data, such as a mobile phone, a portable audio player for recording and reproducing audio signals, a portable PDA, a voice recorder, and an in-vehicle AV device. Anything that can load the program of YON-UP and has an EEPROM can be used. It is especially useful for portable electronic devices that are prone to battery drain and erroneous operation.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Read Only Memory (AREA)

Abstract

Dans un dispositif à mémoire à semi-conducteur utilisant une mémoire rémanente, telle qu'une EEPROM, même dans le cas où des données stockées dans la mémoire rémanente ne peuvent être lues correctement du fait d'une interruption d'alimentation en courant ou analogue, un programme de récupération est activé afin de récupérer rapidement la fonction en tant que dispositif à mémoire. Pour ce faire, après l'activation du programme de récupération stocké dans une ROM, un programme (FW2) stocké dans l'EEPROM est transféré à une RAM, et ensuite, une UC exécute un traitement sur la base du programme (FW2) transféré dans la RAM.
PCT/JP2004/014905 2003-10-03 2004-10-01 Dispositif a memoire a semi-conducteur WO2005033949A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2003345550 2003-10-03
JP2003-345550 2003-10-03

Publications (1)

Publication Number Publication Date
WO2005033949A1 true WO2005033949A1 (fr) 2005-04-14

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8320191B2 (en) 2007-08-30 2012-11-27 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62257559A (ja) * 1986-05-01 1987-11-10 Fujitsu Ltd エラ−処理方式
JP2002289713A (ja) * 1994-03-03 2002-10-04 Rohm Usa Inc ファウラーノルドハイムプログラミング及び消去を利用する、低電圧単一トランジスタ型フラッシュｅｅｐｒｏｍセル
JP2003058377A (ja) * 2001-08-17 2003-02-28 Iwatsu Electric Co Ltd マイクロコントローラの機能拡張方式
JP2003058432A (ja) * 2001-08-09 2003-02-28 Hitachi Ltd メモリカード及びメモリコントローラ

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62257559A (ja) * 1986-05-01 1987-11-10 Fujitsu Ltd エラ−処理方式
JP2002289713A (ja) * 1994-03-03 2002-10-04 Rohm Usa Inc ファウラーノルドハイムプログラミング及び消去を利用する、低電圧単一トランジスタ型フラッシュｅｅｐｒｏｍセル
JP2003058432A (ja) * 2001-08-09 2003-02-28 Hitachi Ltd メモリカード及びメモリコントローラ
JP2003058377A (ja) * 2001-08-17 2003-02-28 Iwatsu Electric Co Ltd マイクロコントローラの機能拡張方式

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8320191B2 (en) 2007-08-30 2012-11-27 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device
US9030877B2 (en) 2007-08-30 2015-05-12 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device

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