WO2005033949A1 - Semiconductor memory device - Google Patents

Semiconductor memory device Download PDF

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Publication number
WO2005033949A1
WO2005033949A1 PCT/JP2004/014905 JP2004014905W WO2005033949A1 WO 2005033949 A1 WO2005033949 A1 WO 2005033949A1 JP 2004014905 W JP2004014905 W JP 2004014905W WO 2005033949 A1 WO2005033949 A1 WO 2005033949A1
Authority
WO
WIPO (PCT)
Prior art keywords
program
memory device
rom
semiconductor memory
module
Prior art date
Application number
PCT/JP2004/014905
Other languages
French (fr)
Japanese (ja)
Inventor
Masahiro Nakanishi
Tomoaki Izumi
Tetsushi Kasahara
Kazuaki Tamura
Kiminori Matsuno
Original Assignee
Matsushita Electric Industrial Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP2003345550 priority Critical
Priority to JP2003-345550 priority
Application filed by Matsushita Electric Industrial Co., Ltd. filed Critical Matsushita Electric Industrial Co., Ltd.
Publication of WO2005033949A1 publication Critical patent/WO2005033949A1/en

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Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/04Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0433Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14Error detection or correction of the data by redundancy in operation
    • G06F11/1402Saving, restoring, recovering or retrying
    • G06F11/1415Saving, restoring, recovering or retrying at system level
    • G06F11/1441Resetting or repowering
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14Error detection or correction of the data by redundancy in operation
    • G06F11/1402Saving, restoring, recovering or retrying
    • G06F11/1415Saving, restoring, recovering or retrying at system level
    • G06F11/1417Boot up procedures
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14Error detection or correction of the data by redundancy in operation
    • G06F11/1479Generic software techniques for error detection or fault masking
    • G06F11/1482Generic software techniques for error detection or fault masking by means of middleware or OS functionality

Abstract

In a semiconductor memory device using a nonvolatile memory, such as EEPROM, even in an event that data stored in the nonvolatile memory cannot be correctly read due to a power supply interruption or the like, a recovery program is activated to quickly recover the function as of a memory device. For this purpose, after the activation of the recovery program stored in a ROM, a program (FW2) stored in the EEPROM is transferred to a RAM, and thereafter, a CPU performs a processing based on the program (FW2) transferred to the RAM.

Description

Specification semiconductor memory device technology field

The present invention relates to a memory device using a semiconductor non-volatile memory, specifically, a mask ROM in the semiconductor memory device, and a portion of the area of ​​the recording non-volatile memory, by dividing the control program storage related to semiconductor memory device that. BACKGROUND

As a conventional semiconductor memory device, in JP-1 one 5948 5 No. (Reference 1), a read only memory (hereinafter, referred to as ROM) consisting of a mask ROM or the like and, of EEP ROM which is a main storage unit of the semiconductor memory device one to a part of a region, a technique for storing is disclosed a control program division to.

Figure 1 is a proc diagram showing a configuration of a conventional semiconductor memory device as described above. This semiconductor memory device is connected to the host system 50 1. The semi-conductor memory device includes a controller 502 A, the EEP ROM 503 as module one le. The controller 502 A is a module having a host interface 504, CPU 50 5, RAM 506, EEPR OM interface 507, RO M 508. RAM 506 is a memory capable of random access read, and phosphorylase Bok interface 504 temporarily stores the data input and output via the EEPROM in evening face 507, providing the C PU 5 0 5. ROM508 is a read-only mask memory for holding program FW1. ROM 508 is a main program, also holds transfer program for transferring the extended program FW2 recorded in EEPROM 5 03 to the controller 502 A side. Extended program FW2 is a program that is added in accordance with the extension of the semiconductors memory device.

Here the program FW1 held in ROM508, in addition to the original main program, including the transfer program for transferring the extended program FW 2 in EEPROM503 the R AM 5 06. Meanwhile EEP ROM 503 is a module that includes an electrically recording and erasable programmable ROM, a is connected to the controller 502 A via the memory bus. EEPROM 5 0 3 may store a general data input from the host system 50 1, and stores the expanded program FW2 in a partial region 509. When the general data Ya expansion program FW2 is transferred to the controller 502 A, C PU 5 0 5 is to run the transfer program against EEP ROM fin evening face 507.

A conventional semiconductor memory device constructed as above will be described with reference to Figure 1. First by turning on the power source of the semiconductor memory device, C PU 505 initiates the transfer program in the program FW 1 stored in the ROM 508. At this time, the extended program FW2 stored in the area 509 of the EEPROM 503 is read and transferred to the RAM506 through the EEPROM interface 5 07. Then C PU 505 is ROM 50 8 on the stored main program, and controls the controller 50 2 A using the expansion program FW 2 transferred to RAM 506. The controller 5 02 A in response to the write instruction of data from the host system 50 1, ho Sutoin evening through the face 504 and E EPROM interface 507, reads data from the EEP ROM 503, and against the EEPROM 503 data do the writing.

Thus to divide the program as a semiconductor memory device to program FW1 and extended program FW2. Then, by holding the extended program FW2 in the region 509 of the EEP ROM 50 3, only rewriting of the expansion program FW2 region 509, the short-term expansion of functions of the semiconductor memory device (e.g., purge Yung-up) it can be executed.

However, in the conventional semiconductor memory device as described above, EE PROM 50 3 of abnormal state, for example, the influence of power-off or the like in the case of falls into a state that does not properly read the data in the next startup, the expansion program the FW2 there is a problem that can not be properly transferred to the R AM 506.

In this case the semiconductor memory device, evening day under the influence of power-off or the like in the next startup is the phenomenon that not properly read, will be described with reference to Figure 2. Figure 2 is a block diagram of a nonvolatile memory array incorporated in the EEPROM 503. Memory cells for storing data bits in here, i.e. an enlarged view of a portion of the distribution 設形 state of the transistor T r partially illustrates. Selected from the global bit line A (in the drawing GBL- A hereinafter) transistor T r. A, select transistor T r. Mouth one Karubitto line via the C (LBL) is connected. The glow one Barupitto line B (GBL- B) from the selection transistor T r. B, selected Trang Soo evening T r. Via a D mouth one Karubitto lines (LBL) is connected. Memory cells to the local bit line of this is connected a number between Bok helix shape. Select transistor T r selects a memory cell in the bit line direction by, for one selection of memory cells on the bit lines by simultaneously one selecting one word line Wa to. 1-necked one Karubitto line units, the 256 memory cells are connected in parallel. It should be noted that the mouth one Karubitto-ray unit is called a first string. Further to the gate of the assist transistor AT r in the odd-numbered columns in each main Moriseru is connected Assistant Togeto AG- E, the assist gate AG-〇 is connected to the gate Bok assist transistor AT r in the even-numbered columns.

First a description will be given of the basic operation of the data read. Reading, by applying a positive potential to the word line, the value of the data in the presence or absence of current flowing through the memory cell is determined whether 0 or 1. When reading the memory cell MA, a positive voltage is applied to the gates of the select transistor T r. A selection transistor T r. D, a positive voltage is applied to the word line A. At this time, the selection transistor T r. B selectively transitional scan evening T r, C, the potential of the non-selected word line is 0 V. Furthermore, a positive voltage to the assist gate AG- E, the assist gate AG-〇 applying a 0 V. In this state, the memory cell MA is selected, the memory cell MB is deselected. Reading of data held in the memory cell determines the data of the memory cell by whether applied to the conductive position the drain of the memory cell, current flows. When reading the data of the main Moriseru MA, as shown in Figure 2, a potential is applied to the glow one Barubitto line GBL- B, the memory cell MA via the selection transistor T r. D, select transistor T r . it determines whether current flows through a path of a. The current value is the threshold voltage of the memory cell (hereinafter, referred to as V th) it depends on. V th by performing the writing of data will be in a high state, V th is in a low state by performing the erase.

Will now be described factors misreading may occur in data. This occurs when the power shutdown or the like is not erased properly awake during data erasing. That To clear Isseki De erases by lowering the V th of the memory cell by applying a negative voltage to the Wado line. In this case performs an operation of lowering the V th to the value zero, the erase operation such as a power cut-off during the operation of this is happening will be aborted, sometimes V th of Memorise Le becomes negative. It becomes a factor of erroneous reading out described this phenomenon later.

Erroneous reading will be described. As described above, when issuing readings data of the memory cell, a positive voltage is marked addition to the gate (word line) of the selected memory cell, applying a 0 V to the word line of the unselected memory cell to. At this time, the V th of Hisen-option memory cell is 0 V or less (a negative value), the current path such as broken lines shown in Figure 2 occurs. This is referred to as non-selective leak. V th of the selected memory cell MA is a write state, when no current is supplied, the V th of the non-selected menu Moriseru MC is assumed to be negative, would otherwise, in the memory cell MA current flows since it is not, it is determined that a write state. However, current flows since the V th of the non-selected memory cell MC is negative, resulting in determine the constant When it is erased state.

When such condition exists, all the memory cells on the same string is determined as the erased state. That not actually been erased data, it wants intends being read erroneously as if the data already written is erased. Because there are phenomena described above, immediately after startup may become the state EEPROM 503 or we extended program FW 2 is not read correctly. Disclosure of the Invention

The semiconductor memory device of the present invention, holding a memory module electrically data comprises Fu揮 nonvolatile memory erasable and recordable, and a controller module that performs control for reading and writing data in the nonvolatile memory, the program it is intended to and a dedicated ROM out read to. Controller one La module includes a random access readable RAM, and the C PU for controlling the operation of the controller module on the basis of a program stored in the ROM and the RAM. The program that processes the C PU, when the controller modular Yule containing added expanded program to the main program for the operating records the main program ROM, a partial region of the memory module expansion program It is recorded in the. And characterized in that the recovery program for recovering an abnormal state of the non-volatile memory, and an extended program transfer program to forward to the RAM and recorded in the ROM.

With such a configuration, when the abnormal state in a nonvolatile memory for storing data is Ji live also, by executing the restoration program is first stored in the ROM at the start of a semiconductor memory device, a nonvolatile memory data it is possible to correctly read like Thailand. BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 is a block diagram showing the structure of a conventional semiconductor memory device. FIG. 2 is a configuration diagram of EEP ROM of the memory array used in a semiconductor memory device.

FIG. 3 is a block diagram showing a configuration of a semiconductor memory device according to the first embodiment of the present invention.

Figure 4 after activation of the device, a flow Chiya one Bok showing the execution procedure of the CPU in the controller.

FIG. 5 is a block diagram showing a configuration of a semiconductor memory device according to the second embodiment of the present invention. BEST MODE FOR CARRYING OUT THE INVENTION

A semiconductor memory device according to the first embodiment of the present invention will be described with reference to FIGS. 3 and 4. Figure 3 is a block diagram showing a configuration of a semiconductor memory device according to the present embodiment. This semiconductor memory device is connected to the host system 50 1. This semiconductor memory device is configured to include a controller 502 B, EEP ROM 50 3. Module of these functional blocks a semiconductor memory device

- it is incorporated into the substrate as Le.

Controller 502 B includes a host interface 504, CPU 50 5, R AM 506, the EEP ROM interface 507, ROM 1 0 1 in the same modular Yule. Thus also referred controller Mogi Yu Le controller 502 B.

ROM 1 0 1 is a read-only memory, and stores programs FW1. The A program FW1, main program, EEPROM 50 of the order to transfer 3 has been extended program FW2 recorded in the controller port one la 502 B side transfer program, is intended to include recovery program of EEPROM 503.

EEPROM 50 3 is one of the non-volatile memory. Region 102 of the EEP ROM 50 3 is a part of the memory area of ​​the EEPROM, which is an area for storing an extended program FW2 other than the program F Wl. Data General input from the host system 50 1 is recorded in other areas of the EE PROM 503. Functions of the other blocks are the same as the conventional semiconductor memory device. The non-volatile memory array incorporated in EEPROM503 configuration is the same as that shown in Figure 2.

The operation of the semiconductor memory device in this embodiment will be described with reference to Figure 4. Figure 4 immediately after startup of the semiconductor memory device is a flowchart showing the execution procedure of the CPU 50 5. When the power is turned on in step S 1, apparatus is activated. In the next step S 2, out read the ROM 10 1 program FW1, activates the controller 502 B. Then the process proceeds to step S 3, searches the memory cell V th is negative by a power shutdown or similar anti Sanaka, V th is forced to a positive potential the transistor of the memory cell becomes negative. By doing so, prevents leakage current, the erroneous reading as a result can be avoided and child are. This processing is executed by the recovery program to recover the EEP ROM in the program FW1 (Step S 3).

Subsequently, the routine goes to the step S 4, to check whether the search in all of the transistor has been completed. If not completed the process returns to step S 3 repeats this process. When the processing for all the transistors are completed, it reads the transfer program stored in the ROM 1 0 1 proceeds from step S 4 to S 5. From immediately Chi EEPROM 50 3 via EEPROM interface 50 7 transfers the extended program FW2 in RAM 506. Then Te Step S 6 smell, the process proceeds to the loop of normal processing.

Note For the transfer of the extended program FW 2, may by a built-in control circuit dedicated to the module include a module or EEP ROM 503 of the controller 502 B, also the control circuit performs the transfer of the extended program FW2 such les ^ in addition, the working of the RAM of the C PU 505 is assumed to be built into the C PU 50 5 itself. As described above, according to the first embodiment, at the time of startup of the apparatus reads and executes the first recovery program stored in the ROM 1 0 1, by executing then reads the transfer program, extended program the FW 2 can be correctly transferred to the RAM 50 6.

(Example 2)

Next, a semiconductor memory device according to the second embodiment of the present invention will be describes the use of Figure 5. FIG. 5 is a block diagram showing a configuration of a semiconductor memory device according to the second embodiment. The same portions as in Example 1 in Figure 5 is given the same reference numerals, and description thereof is omitted features. Difference from the first embodiment is a ROM unit that stores a recovery program in the program FW1, is that provided in the memory module containing the EEPROM 20 1. In this second embodiment, the controller 502 C is shall be the controller module having a host interface Hue Ichisu 504, CPU 505, RAM 506, EEP ROM interface 507, ROM 508.

The EEPROM20 1 is a non-volatile memory, in addition to the EE PROM 202 consisting of non-volatile Memoriare I, provided CPU unit 203, ROM 204 as a control Yunitto. ROM 204 stores the EEPR 0 M recovery program. Also within EE PROM 202 provide a region 205 of the extended program FW 2. During activation of the device, C PU 505 instructs the start of the recovery program to the C PU unit 203 via the EEP ROM Intafue Ichisu 507, C PU unit 203 based on the recovery program stored in the ROM unit 20 to run the recovery process. Meanwhile, CPU 203 a ready signal busy - output as status, it stops the process of C PU 50 5. At the time the recovery program has been completed, the ready signal to the ready state. In this case CPU505 stores the extended program FW2 obtained from EE P ROM 20 1 to RAM 506.

Note the ready signal, it may be reported to the controller 502 C via the memory bus. Regarding the transfer of the extended program FW2, the control circuit of the dedicated controller 502 C, or EEPROM20 be built to 1, the control circuit may be subjected to transfer of the extended program FW2. Further, RAM for working CPU 505 is assumed to be incorporated in the C PU 50 5 itself.

As described above, according to the second embodiment of the present invention, at the time of startup, CPU 50 5 starts processing when the recovery processing by the stored recovery program initially in the ROM 204 is completed, the expansion program FW2 the Rukoto be forwarded to the RAM 506, it is possible to perform the operation by extended program FW2

Industrial Applicability

The semiconductor memory device of the present invention, a mobile phone, audio player portable you record and reproduce audio signals, portable PDA, a voice recorder, such as an AV equipment for vehicle, in addition to the recording of general data, purge as long as it has the EE P ROM can programming load the ram of the four-up can be suitably used. Particularly consumption of the battery, which is useful for erroneous operation easily occurs portable electronic devices.

Claims

O 2005/033949 10 claims
1. Clear electrically data, the memory modules that record containing the non-volatile memory,
And controller Ramojiyu J Les performs control for reading and writing data in the nonvolatile memory,
In the semiconductor memory device having a a read-only ROM for holding the program
The controller module,
Optionally a write readable RAM, and a C PU for controlling the operation of the controller port one Ramojiyuru based on a program held in the R_〇 M and the RAM,
Program for processing of the CPU, when containing an extended program in addition to the main program for the controller modular Yule operates, and records the main program in the ROM, the pre-Symbol memory module the expansion program recorded in a part of the area,
The recovery program for recovering an abnormal state of the nonvolatile memory, and a semiconductor memory device, wherein a transfer program for transferring the expansion program into the RAM and recorded in the ROM.
2. The ROM is a semiconductor memory device according to claim 1, FEATURE: in that provided in the controller module.
3. The ROM is a semiconductor memory device according to claim 1, wherein you, characterized in that provided in the memory module.
4. The control circuitry in the configurable Bok roller module or in the memory module is provided, a semiconductor according to claim 1, wherein the transfer operation corresponding to the transfer program, characterized in that the by connexion executed by the control circuit memory device.
5. The memory module,
Includes a non-volatile memory composed of the nonvolatile memory array, writing of the non-volatile memory, and a control unit for controlling the reading,
Program for processing of the CPU, when the controller module containing a main program plus extension program for operation, and records the main program in the ROM, the expansion program the previous SL nonvolatile memory recorded in a part of the area,
The recovery program for recovering an abnormal state of the nonvolatile memory, and said transfer program for transferring the expanded program to the R AM beforehand the R_〇 characterized by recording the M claim 3 semiconductor memory device according .
6. The memory module,
In addition to the non-volatile memory composed of the nonvolatile memory array has a control Yunitto for controlling the writing and reading of the nonvolatile memory,
The ROM is a semiconductor memory device according to claim 2, wherein the storing at least the control Yuni' Bok program.
7. The con Bok roller module,
Upon power-up, the semiconductor memory device according to claim 6, characterized in that to start the operation based on the recovery program.
8. The expansion program, a semiconductor memory device according to claim 1, characterized in that the program corresponding to the function expansion of the semiconductor memory device.
9. Abnormal state of the non-volatile memory is a semiconductor memory device according to claim i, wherein the influence of power-off, such as a state of not properly read the data on the next startup.
PCT/JP2004/014905 2003-10-03 2004-10-01 Semiconductor memory device WO2005033949A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2003345550 2003-10-03
JP2003-345550 2003-10-03

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8320191B2 (en) 2007-08-30 2012-11-27 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62257559A (en) * 1986-05-01 1987-11-10 Fujitsu Ltd Error processing system
JP2002289713A (en) * 1994-03-03 2002-10-04 Rohm Usa Inc Low voltage single transistor flash eeprom cell using fowler-nordheim programming and erase
JP2003058432A (en) * 2001-08-09 2003-02-28 Hitachi Ltd Memory card and memory controller
JP2003058377A (en) * 2001-08-17 2003-02-28 Iwatsu Electric Co Ltd Functional expansion system of microcontroller

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62257559A (en) * 1986-05-01 1987-11-10 Fujitsu Ltd Error processing system
JP2002289713A (en) * 1994-03-03 2002-10-04 Rohm Usa Inc Low voltage single transistor flash eeprom cell using fowler-nordheim programming and erase
JP2003058432A (en) * 2001-08-09 2003-02-28 Hitachi Ltd Memory card and memory controller
JP2003058377A (en) * 2001-08-17 2003-02-28 Iwatsu Electric Co Ltd Functional expansion system of microcontroller

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8320191B2 (en) 2007-08-30 2012-11-27 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device
US9030877B2 (en) 2007-08-30 2015-05-12 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device

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