WO2005013358A3 - Anordnung eines elektrischen bauelements auf einem substrat und verfahren zur herstellung der anordnung - Google Patents

Anordnung eines elektrischen bauelements auf einem substrat und verfahren zur herstellung der anordnung Download PDF

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Publication number
WO2005013358A3
WO2005013358A3 PCT/EP2004/051460 EP2004051460W WO2005013358A3 WO 2005013358 A3 WO2005013358 A3 WO 2005013358A3 EP 2004051460 W EP2004051460 W EP 2004051460W WO 2005013358 A3 WO2005013358 A3 WO 2005013358A3
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WIPO (PCT)
Prior art keywords
film
component
substrate
arrangement
power semiconductor
Prior art date
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PCT/EP2004/051460
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English (en)
French (fr)
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WO2005013358A2 (de
Inventor
Karl Weidner
Franz Auerbach
Original Assignee
Siemens Ag
Eupec Gmbh & Co Kg
Karl Weidner
Franz Auerbach
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag, Eupec Gmbh & Co Kg, Karl Weidner, Franz Auerbach filed Critical Siemens Ag
Priority to US10/566,438 priority Critical patent/US7649272B2/en
Publication of WO2005013358A2 publication Critical patent/WO2005013358A2/de
Publication of WO2005013358A3 publication Critical patent/WO2005013358A3/de

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3737—Organic materials with or without a thermoconductive filler
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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    • H01—ELECTRIC ELEMENTS
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/2405—Shape
    • H01L2224/24051—Conformal with the semiconductor or solid-state device
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
    • H—ELECTRICITY
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    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Laminated Bodies (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

Die Erfindung betrifft eine Anordnung (1) eines elektrischen Bauelements (3) auf einem Substrat (2), wobei mindestens eine einen Kunststoff aufweisende Folie (5) vorhanden ist und zumindest ein Teil (52) der Folie mit dem Bauelement und dem Substrat derart verbunden ist, dass eine durch das Bauelement und das Substrat gegebene Oberflächenkontur (11) in einer Oberflächenkontur (51) des Teils der Folie abgebildet ist. Die Folie wird derart auf dem Bauelement und dem Substrat auflaminiert, dass die Folie der Topologie der Anordnung aus Bauelement und Substrat folgt. Die Folie steht mit dem Bauelement und dem Substrat in form- und kraftschlüssigen Kontakt. Die Folie weist einen Verbundwerkstoff mit einem vom Kunststoff verschiedenen Füllstoff auf. Mit Hilfe des Füllstoffs beziehungsweise des dadurch gewonnen Verbundwerkstoffs werden die Verarbeitbarkeit der Folie und die elektrischen Eigenschaften der Folie beeinflusst. So können weitere Funktionen in der Folie integriert werden. Das Bauelement ist beispielsweise ein Leistungshalbleiterbauelement. Beispielsweise wird eine elektrisch isolierende und thermisch leitfähige Folie eingesetzt. Durch die Folie hindurch wird eine Kontaktfläche des Leistungshalbleiterbauelement elektrisch kontaktiert. Durch die thermische Leitfähigkeit der Folie kann eine Wärme, die im Betrieb des Leistungshalbleiterbauelements entsteht, effizient abgeleitet werden.
PCT/EP2004/051460 2003-07-31 2004-07-12 Anordnung eines elektrischen bauelements auf einem substrat und verfahren zur herstellung der anordnung WO2005013358A2 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US10/566,438 US7649272B2 (en) 2003-07-31 2004-07-12 Arrangement of an electrical component placed on a substrate, and method for producing the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10335155.8 2003-07-31
DE10335155A DE10335155B4 (de) 2003-07-31 2003-07-31 Verfahren zum Herstellen einer Anordnung eines elektrischen Bauelements auf einem Substrat

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WO2005013358A2 WO2005013358A2 (de) 2005-02-10
WO2005013358A3 true WO2005013358A3 (de) 2005-07-21

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US (1) US7649272B2 (de)
DE (1) DE10335155B4 (de)
WO (1) WO2005013358A2 (de)

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DE102005034873B4 (de) * 2005-07-26 2013-03-07 Siemens Aktiengesellschaft Anordnung eines elektrischen Bauelements und eines auf dem Bauelement auflaminierten Folienverbunds und Verfahren zur Herstellung der Anordnung
DE102005037321B4 (de) * 2005-08-04 2013-08-01 Infineon Technologies Ag Verfahren zur Herstellung von Halbleiterbauteilen mit Leiterbahnen zwischen Halbleiterchips und einem Schaltungsträger
DE102005041100A1 (de) * 2005-08-30 2007-03-08 Siemens Ag Halbleiterstruktur mit einem lateral funktionalen Aufbau
WO2007076014A2 (en) * 2005-12-23 2007-07-05 World Properties, Inc. Thermal management circuit materials, method of manufacture thereof, and articles formed therefrom
DE102007036046A1 (de) * 2007-08-01 2009-02-05 Siemens Ag Planares elektronisches Modul
US8841782B2 (en) * 2008-08-14 2014-09-23 Stats Chippac Ltd. Integrated circuit package system with mold gate
DE102009017732A1 (de) * 2009-04-11 2010-10-21 Semikron Elektronik Gmbh & Co. Kg Leistungshalbleiterbauelement mit einer Randpassivierung und Verfahren zu dessen Herstellung
DE102013219433B4 (de) * 2013-09-26 2019-05-29 Siemens Aktiengesellschaft Elektronisches Leistungsmodul mit elastischen Kontakten und Stapelaufbau mit einem solchen Leistungsmodul
DE102017104926A1 (de) 2017-03-08 2018-09-13 Olav Birlem Verbindung für einen Sensor

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GB2269059A (en) * 1992-07-18 1994-01-26 Central Research Lab Ltd Insulation displacement anisotropic electrical connection.
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US6541378B1 (en) * 2001-11-06 2003-04-01 Lockheed Martin Corporation Low-temperature HDI fabrication
DE10235771A1 (de) * 2002-08-05 2004-02-26 Texas Instruments Deutschland Gmbh Gekapselter Chip und Verfahren zu seiner Herstellung

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Also Published As

Publication number Publication date
US20060197222A1 (en) 2006-09-07
US7649272B2 (en) 2010-01-19
DE10335155A1 (de) 2005-03-03
WO2005013358A2 (de) 2005-02-10
DE10335155B4 (de) 2006-11-30

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