WO2005001934A3 - Hochfrequenz-package - Google Patents

Hochfrequenz-package Download PDF

Info

Publication number
WO2005001934A3
WO2005001934A3 PCT/EP2004/051282 EP2004051282W WO2005001934A3 WO 2005001934 A3 WO2005001934 A3 WO 2005001934A3 EP 2004051282 W EP2004051282 W EP 2004051282W WO 2005001934 A3 WO2005001934 A3 WO 2005001934A3
Authority
WO
WIPO (PCT)
Prior art keywords
frequency package
component
film
circuit carrier
package
Prior art date
Application number
PCT/EP2004/051282
Other languages
English (en)
French (fr)
Other versions
WO2005001934A2 (de
Inventor
Gernot Schimetta
Karl Weidner
Joerg Zapf
Original Assignee
Siemens Ag
Gernot Schimetta
Karl Weidner
Joerg Zapf
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag, Gernot Schimetta, Karl Weidner, Joerg Zapf filed Critical Siemens Ag
Priority to EP04741915A priority Critical patent/EP1639642A2/de
Priority to US10/527,961 priority patent/US20060162157A1/en
Priority to JP2005518163A priority patent/JP2006510235A/ja
Publication of WO2005001934A2 publication Critical patent/WO2005001934A2/de
Publication of WO2005001934A3 publication Critical patent/WO2005001934A3/de

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3164—Partial encapsulation or coating the coating being a foil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0102—Calcium [Ca]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01068—Erbium [Er]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19106—Disposition of discrete passive components in a mirrored arrangement on two different side of a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49144—Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Manufacturing & Machinery (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Microwave Amplifiers (AREA)
  • Wire Bonding (AREA)

Abstract

Zur Herstellung eines Hochfrequenz-Packages wird ein Bauelement über Kontakte (2) mit einem Schaltungsträger (3) verbunden, die das Bauelement gegenüber dem Schaltungsträger beabstanden, eine Folie (5) auf das Bauelement (1) und den Schaltungsträger (3) aufgebracht und die Folie metallisiert (6).
PCT/EP2004/051282 2003-06-30 2004-06-29 Hochfrequenz-package WO2005001934A2 (de)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP04741915A EP1639642A2 (de) 2003-06-30 2004-06-29 Hochfrequenz-package
US10/527,961 US20060162157A1 (en) 2003-06-30 2004-06-29 Economical high-frequency package
JP2005518163A JP2006510235A (ja) 2003-06-30 2004-06-29 廉価な高周波パッケージ

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10329329.9 2003-06-30
DE10329329A DE10329329B4 (de) 2003-06-30 2003-06-30 Hochfrequenz-Gehäuse und Verfahren zu seiner Herstellung

Publications (2)

Publication Number Publication Date
WO2005001934A2 WO2005001934A2 (de) 2005-01-06
WO2005001934A3 true WO2005001934A3 (de) 2005-05-12

Family

ID=33546724

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2004/051282 WO2005001934A2 (de) 2003-06-30 2004-06-29 Hochfrequenz-package

Country Status (7)

Country Link
US (1) US20060162157A1 (de)
EP (1) EP1639642A2 (de)
JP (1) JP2006510235A (de)
KR (1) KR100697434B1 (de)
CN (1) CN100382306C (de)
DE (1) DE10329329B4 (de)
WO (1) WO2005001934A2 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100691160B1 (ko) * 2005-05-06 2007-03-09 삼성전기주식회사 적층형 표면탄성파 패키지 및 그 제조방법
KR100703090B1 (ko) * 2005-08-30 2007-04-06 삼성전기주식회사 후면 접지형 플립칩 반도체 패키지
DE102006025162B3 (de) 2006-05-30 2008-01-31 Epcos Ag Flip-Chip-Bauelement und Verfahren zur Herstellung
DE102010054782A1 (de) * 2010-12-16 2012-06-21 Epcos Ag Gehäustes elektrisches Bauelement
JP5799541B2 (ja) 2011-03-25 2015-10-28 株式会社ソシオネクスト 半導体装置及びその製造方法
FR2984882A1 (fr) 2011-12-23 2013-06-28 Saint Gobain Ct Recherches Procede de fabrication d'un produit mesoporeux.
KR101356791B1 (ko) * 2012-01-20 2014-01-27 한국과학기술원 박막형 수퍼커패시터 및 그의 제조 방법
CN105702664A (zh) * 2012-11-16 2016-06-22 日月光半导体制造股份有限公司 半导体封装构造及其制造方法
US9484313B2 (en) * 2013-02-27 2016-11-01 Advanced Semiconductor Engineering, Inc. Semiconductor packages with thermal-enhanced conformal shielding and related methods
US10542630B2 (en) 2014-06-23 2020-01-21 Tdk Corporation Housing for an electric component, and method for producing a housing for an electric component
CN106816420A (zh) * 2015-11-30 2017-06-09 讯芯电子科技（中山）有限公司 一种声波元件封装结构及其制造方法
US10741501B1 (en) * 2018-10-22 2020-08-11 Keysight Technologies, Inc. Systems and methods for sheathing electronic components

Citations (8)

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Publication number Priority date Publication date Assignee Title
US5639989A (en) * 1994-04-19 1997-06-17 Motorola Inc. Shielded electronic component assembly and method for making the same
WO2001078041A1 (de) * 2000-04-05 2001-10-18 Epcos Ag Bauelement mit beschriftung
US6492194B1 (en) * 1999-10-15 2002-12-10 Thomson-Csf Method for the packaging of electronic components
TW517368B (en) * 2002-01-22 2003-01-11 Via Tech Inc Manufacturing method of the passivation metal on the surface of integrated circuit
DE10136743A1 (de) * 2001-07-27 2003-02-13 Epcos Ag Verfahren zur hermetischen Verkapselung eines Bauelementes
DE10142542A1 (de) * 2001-08-30 2003-03-27 Infineon Technologies Ag Anordnung eines Halbleiterchips in einem Gehäuse, Chipkarte und Chipmodul
DE10164502A1 (de) * 2001-12-28 2003-07-17 Epcos Ag Verfahren zur hermetischen Verkapselung eines Bauelements
DE10256945A1 (de) * 2002-12-05 2004-06-17 Epcos Ag Elektronisches Bauelement mit mehreren Chips und Verfahren zur Herstellung

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US6274391B1 (en) * 1992-10-26 2001-08-14 Texas Instruments Incorporated HDI land grid array packaged device having electrical and optical interconnects
US5477082A (en) * 1994-01-11 1995-12-19 Exponential Technology, Inc. Bi-planar multi-chip module
FR2728392A1 (fr) * 1994-12-16 1996-06-21 Bull Sa Procede et support de connexion d'un circuit integre a un autre support par l'intermediaire de boules
DE69621983T2 (de) * 1995-04-07 2002-11-21 Shinko Electric Industries Co., Ltd. Struktur und Verfahren zur Montage eines Halbleiterchips
DE19548048C2 (de) * 1995-12-21 1998-01-15 Siemens Matsushita Components Elektronisches Bauelement, insbesondere mit akustischen Oberflächenwellen arbeitendes Bauelement (OFW-Bauelement)
DE59704079D1 (de) * 1996-05-24 2001-08-23 Epcos Ag Elektronisches bauelement, insbesondere mit akustischen oberflächenwellen arbeitendes bauelement - ofw-bauelement
US5899705A (en) * 1997-11-20 1999-05-04 Akram; Salman Stacked leads-over chip multi-chip module
DE19806818C1 (de) * 1998-02-18 1999-11-04 Siemens Matsushita Components Verfahren zur Herstellung eines elektronischen Bauelements, insbesondere eines mit akustischen Oberflächenwllen arbeitenden OFW-Bauelements
DE19818824B4 (de) * 1998-04-27 2008-07-31 Epcos Ag Elektronisches Bauelement und Verfahren zu dessen Herstellung
DE10002852A1 (de) * 2000-01-24 2001-08-02 Infineon Technologies Ag Abschirmeinrichtung und elektrisches Bauteil mit einer Abschirmeinrichtung
TW445612B (en) * 2000-08-03 2001-07-11 Siliconware Precision Industries Co Ltd Solder ball array structure to control the degree of collapsing

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5639989A (en) * 1994-04-19 1997-06-17 Motorola Inc. Shielded electronic component assembly and method for making the same
US6492194B1 (en) * 1999-10-15 2002-12-10 Thomson-Csf Method for the packaging of electronic components
WO2001078041A1 (de) * 2000-04-05 2001-10-18 Epcos Ag Bauelement mit beschriftung
DE10136743A1 (de) * 2001-07-27 2003-02-13 Epcos Ag Verfahren zur hermetischen Verkapselung eines Bauelementes
DE10142542A1 (de) * 2001-08-30 2003-03-27 Infineon Technologies Ag Anordnung eines Halbleiterchips in einem Gehäuse, Chipkarte und Chipmodul
DE10164502A1 (de) * 2001-12-28 2003-07-17 Epcos Ag Verfahren zur hermetischen Verkapselung eines Bauelements
TW517368B (en) * 2002-01-22 2003-01-11 Via Tech Inc Manufacturing method of the passivation metal on the surface of integrated circuit
US20030138991A1 (en) * 2002-01-22 2003-07-24 Moriss Kung Method for forming a metal layer on an IC package
DE10256945A1 (de) * 2002-12-05 2004-06-17 Epcos Ag Elektronisches Bauelement mit mehreren Chips und Verfahren zur Herstellung

Also Published As

Publication number Publication date
US20060162157A1 (en) 2006-07-27
DE10329329A1 (de) 2005-02-17
DE10329329B4 (de) 2005-08-18
CN1701440A (zh) 2005-11-23
KR20050042200A (ko) 2005-05-04
EP1639642A2 (de) 2006-03-29
KR100697434B1 (ko) 2007-03-20
JP2006510235A (ja) 2006-03-23
WO2005001934A2 (de) 2005-01-06
CN100382306C (zh) 2008-04-16

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