WO2004095567A8 - Kontrolle des dickenabtrags von einem scheibenverbund und teststruktur zur abtragskontrolle - Google Patents

Kontrolle des dickenabtrags von einem scheibenverbund und teststruktur zur abtragskontrolle

Info

Publication number
WO2004095567A8
WO2004095567A8 PCT/DE2004/000801 DE2004000801W WO2004095567A8 WO 2004095567 A8 WO2004095567 A8 WO 2004095567A8 DE 2004000801 W DE2004000801 W DE 2004000801W WO 2004095567 A8 WO2004095567 A8 WO 2004095567A8
Authority
WO
WIPO (PCT)
Prior art keywords
wafer
monitoring
thickness
test structure
reduction
Prior art date
Application number
PCT/DE2004/000801
Other languages
English (en)
French (fr)
Other versions
WO2004095567A1 (de
Inventor
Ralf Lerner
Original Assignee
X Fab Semiconductor Foundries
Ralf Lerner
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE2003117747 external-priority patent/DE10317747B3/de
Application filed by X Fab Semiconductor Foundries, Ralf Lerner filed Critical X Fab Semiconductor Foundries
Priority to EP04727825A priority Critical patent/EP1616348A1/de
Priority to DE112004000735T priority patent/DE112004000735D2/de
Priority to US10/553,470 priority patent/US7598098B2/en
Priority to PCT/DE2004/000801 priority patent/WO2004095567A1/de
Publication of WO2004095567A1 publication Critical patent/WO2004095567A1/de
Publication of WO2004095567A8 publication Critical patent/WO2004095567A8/de

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Automation & Control Theory (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Element Separation (AREA)

Abstract

Es soll ein einfaches Kontroll oder Testverfahren zur Kontrolle eines Dickenabtrags von einem gebondeten Halbleiterscheiben-Paar geschaffen werden, welches Fehlereinflüsse beim Scheibenabtragen (Polieren, Schleifen oder Läppen) vermindert. Die Kosten des Abtragsprozesses sollen durch Minimieren des Kontrollaufwandes ebenso reduziert werden, wie entstehende Ausschüsse. Vorgeschlagen wird eine Teststruktur (4,5,6,7,8,9), bestehend aus einer systematischen Reihe von mehreren, unterschiedlich tiefen Gräben, die in die (aktive) Scheibe (2) eingebracht sind. Eine beim Abtragen, insbesondere einem Polieren, angezielte Dicke (h6;h7) der aktiven Scheibe (2) entspricht einer Tiefe (t6;t7) eines Bezugsgrabens (6;7) der Gräben der Teststruktur, welcher Bezugsgraben (6) von flacheren und tieferen Gräben umgeben ist (5,7). Die aktive Scheibe (2) wird mit der Seite (2a), von der die Teststruktur eingebracht wurde, auf die zweite Scheibe des Halbleiter-Scheibenpaars als Trägerscheibe (1) gebondet. Ein Abtragen, insbesondere ein Polieren, von der Rückseite (2b) der aktiven Scheibe (2) bis zum Freilegen des Bezugsgrabens (6) wird vorgenommen. Das Ergebnis wird optisch beobachtet (30), zur Kontrolle des Dickenabtrags von der ersten Scheibe (2).
PCT/DE2004/000801 2003-04-17 2004-04-16 Kontrolle des dickenabtrags von einem scheibenverbund und teststruktur zur abtragskontrolle WO2004095567A1 (de)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP04727825A EP1616348A1 (de) 2003-04-17 2004-04-16 Kontrolle des dickenabtrags von einem scheibenverbund und teststruktur zur abtragskontrolle
DE112004000735T DE112004000735D2 (de) 2003-04-17 2004-04-16 Kontrolle des Dickenabtrags von einem Scheibenverbund und Teststruktur zur Abtragskontrolle
US10/553,470 US7598098B2 (en) 2003-04-17 2004-04-16 Monitoring the reduction in thickness as material is removed from a wafer composite and test structure for monitoring removal of material
PCT/DE2004/000801 WO2004095567A1 (de) 2003-04-17 2004-04-16 Kontrolle des dickenabtrags von einem scheibenverbund und teststruktur zur abtragskontrolle

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10317747.7 2003-04-17
DE2003117747 DE10317747B3 (de) 2003-04-17 2003-04-17 Verfahren zur Kontrolle des Dickenabtrags von gebondeten Halbleiterscheibenpaaren
PCT/DE2004/000801 WO2004095567A1 (de) 2003-04-17 2004-04-16 Kontrolle des dickenabtrags von einem scheibenverbund und teststruktur zur abtragskontrolle

Publications (2)

Publication Number Publication Date
WO2004095567A1 WO2004095567A1 (de) 2004-11-04
WO2004095567A8 true WO2004095567A8 (de) 2005-12-22

Family

ID=33311745

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2004/000801 WO2004095567A1 (de) 2003-04-17 2004-04-16 Kontrolle des dickenabtrags von einem scheibenverbund und teststruktur zur abtragskontrolle

Country Status (3)

Country Link
US (1) US7598098B2 (de)
EP (1) EP1616348A1 (de)
WO (1) WO2004095567A1 (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7588948B2 (en) * 2003-04-17 2009-09-15 X-Fab Semiconductor Foundries Ag Test structure for electrically verifying the depths of trench-etching in an SOI wafer, and associated working methods
US9685524B2 (en) * 2005-03-11 2017-06-20 Vishay-Siliconix Narrow semiconductor trench structure
TWI489557B (zh) 2005-12-22 2015-06-21 Vishay Siliconix 高移動率ｐ-通道溝槽及平面型空乏模式的功率型金屬氧化物半導體場效電晶體
US8409954B2 (en) 2006-03-21 2013-04-02 Vishay-Silconix Ultra-low drain-source resistance power MOSFET
CN102376693B (zh) * 2010-08-23 2016-05-11 香港科技大学 单片磁感应器件
CN102402126B (zh) * 2010-09-17 2014-07-16 中芯国际集成电路制造(北京)有限公司 一种用于检测光刻过程中照明条件的结构及其检测方法
US9412883B2 (en) 2011-11-22 2016-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for MOS capacitors in replacement gate process
CN102881582B (zh) * 2012-09-11 2015-12-09 中国科学院苏州纳米技术与纳米仿生研究所 深硅刻蚀方法
US10236226B2 (en) * 2016-03-15 2019-03-19 Raytheon Company In-situ calibration structures and methods of use in semiconductor processing
RU175042U1 (ru) * 2017-06-20 2017-11-16 Закрытое акционерное общество "ГРУППА КРЕМНИЙ ЭЛ" Тестовый элемент для контроля качества анизотропного травления канавок
CN112967943B (zh) * 2020-11-05 2022-03-25 重庆康佳光电技术研究院有限公司 一种暂态基板上led芯片的压合深度检测方法及暂态基板

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0376221A (ja) * 1989-08-18 1991-04-02 Mitsubishi Electric Corp ウエハの研磨方法
DE19741971A1 (de) * 1997-09-23 1999-04-01 Siemens Ag Verfahren zum Herstellen Direct-Wafer-Bond Si/Si02/Si-Substrate
US5972787A (en) * 1998-08-18 1999-10-26 International Business Machines Corp. CMP process using indicator areas to determine endpoint
KR20000040104A (ko) * 1998-12-17 2000-07-05 김영환 실리콘 온 인슐레이터 웨이퍼의 제조방법
US6515826B1 (en) * 2000-08-14 2003-02-04 International Business Machines Corporation Magnetic head induction coil fabrication method utilizing aspect ratio dependent etching
US6514858B1 (en) * 2001-04-09 2003-02-04 Advanced Micro Devices, Inc. Test structure for providing depth of polish feedback
JP2003017444A (ja) * 2001-06-29 2003-01-17 Sumitomo Mitsubishi Silicon Corp 半導体ウェーハの加工取り代の測定方法およびその装置
US6864176B2 (en) * 2002-05-28 2005-03-08 Asia Pacific Microsystems, Inc. Fabrication process for bonded wafer precision layer thickness control and its non-destructive measurement method

Also Published As

Publication number Publication date
US20060292825A1 (en) 2006-12-28
US7598098B2 (en) 2009-10-06
WO2004095567A1 (de) 2004-11-04
EP1616348A1 (de) 2006-01-18

Similar Documents

Publication Publication Date Title
WO2004095567A8 (de) Kontrolle des dickenabtrags von einem scheibenverbund und teststruktur zur abtragskontrolle
MY125775A (en) Method for treating substrates for microelectronics and substrates obtained by said method.
WO2002084720A3 (fr) Dispositif d'exposition, systeme de traitement de substrat et procede permettant de produire ce dispositif
WO2002015247A3 (en) Method and apparatus for processing a semiconductor wafer using novel final polishing method
US5756399A (en) Process for making semiconductor wafer
TW200734778A (en) Apparatus for manufacturing bonded substrate
CN103875061B (zh) 剥离晶片的再生加工方法
HK1068840A1 (en) Method for polishing a substrate surface
CN101960558B (zh) 贴合晶片的制造方法
EP1793021A3 (de) Verfahren zur Behandlung von Halbleitern unter Verwendung von einem Gegenstand aus Silizium Karbid
TW200706307A (en) Semiconductor wafer peripheral edge polisher and method therefor
EP1677346A3 (de) Bearbeiten von Substraten, insbesondere von Halbleitersubstraten
FR2874745A1 (fr) Plaque semiconductrice presentant une structure stratifiee avec de faibles warp et bow, et procedes pour sa preparation
JP2004510334A5 (de)
TW200625433A (en) Method for manufacturing silicon wafer
TW200514845A (en) Process solutions containing surfactants used as post-chemical mechanical planarization treatment
TW200731380A (en) Semiconductor wafer manufacturing method, semiconductor wafer double-sided grinding method, and semiconductor wafer double-sided grinding apparatus
EP1555337A3 (de) Einkristall-Diamantsubstrat und dessen Herstellungsverfahren
DE50001511D1 (de) Verfahren zum vereinzeln eines wafers
EP1676672A4 (de) Wafer-halteträger, diesen verwendende doppelseitige schleifvorrichtung und doppelseitiges schleifverfahren für wafer
WO2005050705A3 (en) Silicon carbide components of semiconductor substrate processing apparatuses treated to remove free-carbon
CN103794489B (zh) 等离子蚀刻的方法
JPH1110532A (ja) ウェーハホルダおよび半導体ウェーハの製造方法
EP1538663A3 (de) Verfahren zur Behandlung der Rückseite eines Wafers und entsprechende Behandlungsvorrichtung
CN105283943B (zh) 贴合晶圆的制造方法

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NA NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): BW GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 2004727825

Country of ref document: EP

CFP Corrected version of a pamphlet front page
CR1 Correction of entry in section i

Free format text: IN PCT GAZETTE 45/2004 UNDER (81) ADD "DE".

WWP Wipo information: published in national office

Ref document number: 2004727825

Country of ref document: EP

REF Corresponds to

Ref document number: 112004000735

Country of ref document: DE

Date of ref document: 20060209

Kind code of ref document: P

WWE Wipo information: entry into national phase

Ref document number: 112004000735

Country of ref document: DE

DPEN Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed from 20040101)
WWE Wipo information: entry into national phase

Ref document number: 2006292825

Country of ref document: US

Ref document number: 10553470

Country of ref document: US

WWP Wipo information: published in national office

Ref document number: 10553470

Country of ref document: US