WO2004066384A1 - Structure de circuit programmable et procede pour la produire - Google Patents

Structure de circuit programmable et procede pour la produire

Info

Publication number
WO2004066384A1
WO2004066384A1 PCT/EP2003/000684 EP0300684W WO2004066384A1 WO 2004066384 A1 WO2004066384 A1 WO 2004066384A1 EP 0300684 W EP0300684 W EP 0300684W WO 2004066384 A1 WO2004066384 A1 WO 2004066384A1
Authority
WO
WIPO (PCT)
Prior art keywords
conductive layer
layer
circuit structure
programmable circuit
conductor
Prior art date
Application number
PCT/EP2003/000684
Other languages
German (de)
English (en)
Inventor
Michael Reiss
Uwe Paschen
Thomas Kroeger
Holger Vogt
Heinz Deiters
Original Assignee
Fraunhofer Ges Forschung
Michael Reiss
Uwe Paschen
Thomas Kroeger
Holger Vogt
Heinz Deiters
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fraunhofer Ges Forschung, Michael Reiss, Uwe Paschen, Thomas Kroeger, Holger Vogt, Heinz Deiters filed Critical Fraunhofer Ges Forschung
Priority to PCT/EP2003/000684 priority Critical patent/WO2004066384A1/fr
Publication of WO2004066384A1 publication Critical patent/WO2004066384A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/20—Programmable ROM [PROM] devices comprising field-effect components
    • H10B20/25—One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links

Definitions

  • the present patent application relates to a one-time programmable circuit structure and to a method for producing a one-time programmable circuit structure.
  • Uniquely programmable electronic memory cells are used in numerous integrated electronic circuits and circuit structures. They are used individually or in small numbers to make one-off adjustments to the circuit structure or to program them. This includes, for example, saving calibration parameters, masking or marking faulty or defective sections of the circuit structure, replacing such areas with functional redundant areas, selecting certain functions or functionalities. These settings are generally made before the circuit structure is used, and particularly often immediately after its manufacture.
  • An EPROM electrically programmable read only memory
  • OTP cells one time programmable
  • fuse cells are generally used as OTP cells, the electrical resistance of which can be permanently changed once by applying one or more electrical current pulses.
  • Fuse cells have a small electrical trical resistance. After programming or burning by one or more electrical current pulses, fuse cells have a significantly higher resistance, which is generally greater than 10 k ⁇ .
  • the two binary states "0" and "1" are assigned to the two resistance ranges of the new and the burned or blown fuse cell.
  • Antifuse cells have a high electrical resistance when new or unfired. By applying one or more electrical current pulses, they are burned or programmed and then have a low electrical resistance.
  • Antifuse cells or antifuse structures have a thin tunnel oxide layer, the electrical resistance of which is high.
  • the tunnel oxide layer is blown by a high current flow and changes into a low-resistance or conductive state.
  • Structures are also known in which oxide or nitride layers are arranged between a through hole and an underlying metal layer and electrically insulate them from one another. These oxide or nitride layers are burnt out by a sufficiently high current flow and then change into a conductive state. Examples of antifuse cells are described in the patents US 5,682,058 A, US 5,856,213 A, and US 5,962,910 A.
  • tunnel oxide or nitride antifuse structures are the relatively high required programming voltage of typically 16 V to 18 V. Voltages at this level are not readily compatible, in particular with modern CMOS processes and the high levels of integration that can be achieved in the process.
  • the object of the present invention is to provide a programmable circuit structure, a method for its production and a method for programming a programmable circuit structure which enable greater reliability, a lower programming voltage and problem-free integration into a CMOS process.
  • the present invention provides a programmable circuit structure having a conductor with at least a first conductive layer and a second conductive layer.
  • the second conductive layer is locally removed to expose an area of the first conductive layer to obtain an exposed area of the first conductive layer.
  • the exposed area of the first conductive layer can be severed by applying a predetermined programming current to the circuit structure.
  • the present invention further provides a method of manufacturing a programmable circuit structure that includes a conductor with a predetermined program Mierstrom separable conductor area.
  • a conductor is provided which has at least a first conductive layer and a second conductive layer.
  • the second conductive layer is locally removed to expose an area of the first conductive layer to obtain an exposed area of the first conductive layer that is severable by application of the predetermined programming current.
  • the present invention provides a method for programming a programmable circuit structure according to the invention, in which the exposed portion of the first conductive layer is severed by driving the predetermined programming current through the conductor.
  • the present invention is based on the idea of forming a severable conductor structure from an exposed region of a conductor layer, which is part of a metallization level of a circuit structure.
  • An advantage of the present invention is that metallization levels generally already have a layer structure of a plurality of metal and conductor layers or other electrically conductive layers, the severable conductor structure being formed from a first conductive layer of the metallization level.
  • the present invention is based on the idea of forming the severable conductor structure from the first conductive layer by forming a recess in a second conductive layer of the metallization level in order to expose a region of the first conductive layer.
  • the severable conductor structure is formed by the exposed area of the first conductor layer.
  • the present invention can thus be easily integrated into a conventional CMOS process, since it only uses standard materials and standard processing steps that are completely compatible with CMOS technology.
  • Another advantage of the present invention is that the manufacturing method according to the invention for the invented programmable circuit structure according to the invention requires only a very few additional method steps compared to a corresponding non-programmable circuit structure.
  • the present invention is further based on the knowledge that a conductor structure made of a conductive layer of a metallization level has a lower electrical resistance than a polysilicon layer of a conventional fuse structure.
  • This has the advantage that a significantly lower programming voltage is required in order to program the programmable circuit structure according to the invention or to cut through its severable conductor structure.
  • the programming voltage required in the present invention is also significantly lower than in conventional antifuse structures with an oxide or nitride layer.
  • Another advantage of the present invention is that the exposed area of the first conductive layer or the severable conductor structure, depending on the exemplary embodiment, is further away from the substrate of the programmable circuit structure.
  • programming voltages of the programmable circuit structure according to the invention are less than 10 V and thus significantly lower than in the case of polysilicon fuse structures.
  • the programmable circuit structure according to the invention is preferably produced using thin-film technology.
  • An embodiment of the present invention provides that the exposed area or the severable conductor structure is formed from a barrier layer.
  • the barrier layer preferably consists of titanium Ti and / or titanium nitride TiN and is an integral part of a metallization level in modern CMOS processes. In scarf tion structures that do not yet provide any barrier layers, these can be inserted into the manufacturing process without further ado and without negative interactions. It is produced as the first layer of a metallization level or deposited on a carrier structure.
  • a second conductive layer is deposited on the barrier layer, which preferably comprises an aluminum layer or another metal layer, which generates most of the electrical conductivity of the metallization level.
  • the barrier layer and the metal layer are laterally structured together.
  • the barrier layer primarily serves to prevent a chemical reaction of the lowermost layers of the aluminum or metal layer with the substrate (silicon substrate).
  • the second conductive layer of the metallization level is removed by selective etching or etching with an etching medium which does not or only insignificantly etches or removes the barrier layer, and the first conductive layer remains as the only conductive layer.
  • the barrier layer due to its material and a small thickness, makes only a small contribution to the electrical conductivity of the metallization level, a conductor structure formed from the barrier layer can be cut through with a relatively low combustion current or programming current.
  • a fuse cell whose separable conductor structure in addition to the barrier layer also includes the thick and low-resistance metal layer, has a very high combustion current.
  • the electrical resistance of the separable conductor structure formed from the barrier layer is significantly lower than the electrical resistance of a polysilicon fuse structure. In comparison to the conventional polysilicon fuse structure, the severable conductor structure according to the invention therefore requires a significantly lower programming voltage.
  • the exposed area of the first conductive layer of the programmable circuit structure according to the invention has a medium resistance as a severable conductor structure and can therefore be cut with a relatively low programming voltage and a relatively low programming current.
  • the exposed area connects two wiring conductors or conductor tracks within the same metallization level, the two conductor tracks being electrically insulated from one another by severing the exposed area.
  • the simplest way to implement this exemplary embodiment is to remove the metal layer, which predominantly produces the electrical conductivity of the metallization level, locally in an area in which the severable conductor structure is to be formed, in order to expose an area of the conductive layer whose resistance is preferably higher than that of the locally removed metal layer.
  • the exposed region of the first conductive layer forms an electrically conductive connection of a region of the metallization level with a through hole conductor, which is connected to an adjacent, preferably underlying metallization level of the circuit structure is.
  • the exposed area forms an electrically conductive connection with the adjacent metallization level.
  • the first conductive layer in which a coating is is richly exposed to form the separable conductor structure not the barrier layer but an anti-reflective coating.
  • An anti-reflective coating (ARC layer) is often provided on a metallization level in order to avoid disturbing reflections in subsequent photolithographic steps. It preferably consists of TiN, which is applied immediately after the aluminum layer or immediately after other metal layers of the metallization level or generally formulated directly after a second conductive layer and is laterally structured together with the latter.
  • the metal layer of the metallization level is removed locally.
  • the severable conductor structure produced in this way from the antireflection coating thus has a self-supporting structure.
  • no barrier layer is preferably provided under the metal layer of the metallization level, since this would short-circuit the separable conductor structure.
  • the barrier layer is removed together with the metal layer.
  • a variant of this exemplary embodiment provides that the separable conductor structure formed from the antireflection layer is not self-supporting, but instead hangs on the underside of a web formed from an insulating layer, for example a passivation layer, or is mechanically connected to it.
  • a further exemplary embodiment of the present invention provides that the severable conductor structure is formed from another, preferably thin layer, which is part of the metallization level.
  • the aluminum deposition is interrupted, for example, in the generation of the metallization level, a material to which aluminum can be selectively etched, for example TiN, is applied and the remaining aluminum is then deposited.
  • the common lateral structuring takes place as a whole. partial layers of the metallization level.
  • the metal layers of the metallization level are then removed locally, so that only the conductor layer remains as a self-supporting structure.
  • the metallization level either has no barrier layer and no antireflection coating, or these are removed together with the metal layers in the metallization level or even beforehand when etching a passivation opening.
  • the severable conductor structure can also be formed from another or the first conductive layer intended only for this purpose, instead of from a barrier layer or anti-reflective coating that is provided in any case.
  • a barrier layer or anti-reflective coating that is provided in any case.
  • FIGS. 1A and 1B are schematic sectional views of a first exemplary embodiment of the present invention before and after a firing;
  • Fig. 2 is a schematic plan view of the first embodiment of the present invention
  • 3 shows a schematic sectional illustration of a second exemplary embodiment of the present invention
  • Fig. 4 is a schematic sectional view of a third embodiment of the present invention.
  • FIG. 5 shows a schematic sectional illustration of a fourth exemplary embodiment of the present invention.
  • FIG. 6 shows a schematic sectional illustration of a fifth exemplary embodiment of the present invention.
  • Fig. 7 is a schematic sectional view of a sixth embodiment of the present invention.
  • Fig. 8 is a schematic plan view of the sixth embodiment of the present invention.
  • 9A to 9C are schematic sectional representations of the first exemplary embodiment of the present invention.
  • 10A to IOC show schematic sectional representations of a seventh exemplary embodiment of the present invention.
  • 1A and IB are schematic representations of a vertical section through a programmable circuit structure according to a first exemplary embodiment of the present invention.
  • 1A and IB represent a section of the programmable circuit structure in two different states.
  • the circuit structure has a carrier structure 10, which is preferably a semiconductor ter substrate or another substrate having a device layer and one or more metallization levels.
  • a metallization level 20 is attached to the carrier structure 10, which is the only one or one of several and preferably the uppermost metallization level of the circuit structure.
  • the metallization level 20 consists of a barrier layer 22, which in turn has a Ti layer 24 on the carrier structure 10 and on the Ti layer 24 a TiN layer 26, which is preferably thicker than the Ti layer 24.
  • the barrier layer represents a first conductive layer of the metallization level 20.
  • the metallization level 20 further comprises a metal layer 28 on the barrier layer 22, which has, for example, aluminum, copper or another metal and preferably a high electrical conductivity.
  • the metal layer 28 represents a second conductive layer of the metallization level 20.
  • the barrier layer 28 preferably has a higher or substantially higher sheet resistance ⁇ Q than the metal layer 28.
  • the material or materials of the barrier layer 22 preferably have a higher or significantly higher specific Resistance than the material or materials of the metal layer 28.
  • a passivation layer 30 is applied on the metallization level 20, which has, for example, silicon oxide or silicon nitride.
  • the TiN layer 26 and the Ti layer 24 of the barrier layer 22 are not or not substantially removed by the selective etching step.
  • a recess 34 is formed in the metal layer 28.
  • an area 36 of the barrier layer 22 is exposed. Due to the previous lateral structuring of the metallization level 20, there is now an area 28a of the metal layer 28 shown on the left in FIG. 1A, which is electrically conductively connected to an area 28b of the metal layer 28 shown on the right in FIG. 1A only via the exposed area 36 of the barrier layer 22 is.
  • the structure as shown in FIG. 1A remains with the electrically conductive connection between the areas 28a, 28b of the metal layer 28.
  • the barrier layer 22 has an interruption 38, so that there is no longer an electrically conductive connection between the regions 28a, 28b of the metal layer 28 or the same are electrically insulated from one another.
  • An electrical connection can continue to exist via precipitation of the Ti and TiN on adjacent surfaces, but this is a much higher one has electrical resistance as the unprogrammed exposed region 36 of the barrier layer 22 shown in FIG. 1A.
  • the exposed area 36 of the barrier layer 22 thus represents a conductor structure that can be cut through by a sufficiently high electrical current.
  • a current that is sufficiently large to safely cut through the exposed area 36 or to convert it from a low-resistance to a high-resistance state is considered as Called programming stream.
  • this type of fuse structure is also referred to as a barrier fuse. Since the severable conductor structure is arranged near the surface of the circuit structure, this type is also referred to as surface fuse.
  • FIG. 2 is a schematic plan view of the programmable circuit structure according to the invention shown in vertical section in FIGS. 1A and IB or a section thereof.
  • the dashed line AA represents the sectional plane shown in FIGS. 1A and IB.
  • regions 28a, 28b of the metal layer 28 and the exposed region 36 of the barrier layer 22 are shown. It can be seen that the metallization plane 20 has been structured laterally in such a way that the exposed region 36 of the barrier layer 22 has lateral constrictions 40.
  • This lateral constriction or the remaining width, the length of the exposed area 36 of the barrier layer 22, the thickness of the barrier layer 22 or of its exposed area 36 and the specific resistance of the material or materials that make up the barrier layer 22, the resistance of the exposed area 36 for a current flow from the area 28a to the area 28b of the metal layer 28 is determined or can be set almost as desired.
  • This resistance and the thermal conductivity of the regions of the carrier structure 10 adjoining the exposed region 36 of the barrier layer 22 the energy, the power, the current and the voltage are determined, which are required to cut through the exposed area 36 of the barrier layer 22 with a current or voltage pulse of a certain length.
  • the edge of the opening 32 in the passivation layer 30 is represented by a dashed rectangular frame.
  • the opening 32 together with the parameters of the etching step with which the recess 34 interrupting the metal layer 28 is produced, determines the length of the exposed area 36 of the barrier layer 22.
  • the exposed area 36 of the barrier layer 22 corresponds to the narrow, rectangular one Area defined by the side constrictions 40.
  • the opening 32 is chosen to be smaller, so that even if the opening 32 is inaccurately adjusted laterally with respect to the laterally structured metallization plane 20, the opening 32 is arranged entirely within the narrow section of the barrier layer 22 defined by the constrictions 40.
  • the electrical properties of the exposed region 36 of the barrier layer 22 and in particular the required programming voltage or the required programming current are in this case independent of a lateral misadjustment of the opening 32 relative to the metallization level 20, at least within certain limits.
  • the width of the opening 32 is preferably chosen to be large enough that a misalignment of the opening 32 relative to the metallization plane 20 in the lateral direction or in a direction transverse to the direction of current flow through the exposed region 36 has no effect within certain limits to the size of the exposed area. Furthermore, the dimensions of the opening 32 are selected such that the etching medium has as good and uniform access as possible to the metallization level 20 and thus a laterally homogeneous removal of the metal layer 28. As an alternative to the lateral constrictions 40 shown in FIG.
  • the exposed region 36 of the barrier layer 22 has the same width as the regions 28a, 28b of the metal layer 28 or one or more lateral constrictions or recesses and arranged on one or both sides, symmetrically or asymmetrically / or one or more kinks or curves which cause a change in the direction of current flow along the exposed region 36 of the barrier layer 22.
  • a zigzag or meandering shape of the exposed region 36 of the barrier layer 22 formed in this way brings about an increased electrical resistance of the severable conductor structure or of the exposed region 36 with at the same time a relatively small space requirement.
  • the circle 50 shown in broken lines encompasses all the features of the present exemplary embodiment, which together form a fuse structure of the programmable circuit structure.
  • the carrier structure 10 shown only partially in FIGS. 1A, IB is first provided.
  • the carrier structure 10 preferably comprises a substrate, for example a semiconductor substrate, with a component layer in which one or more active and / or passive electronic components are arranged.
  • One or more metallization planes are preferably arranged above the component layer and are spatially separated from one another and from the component layer by electrically insulating layers and are electrically insulated.
  • a lateral structuring of the same conductor tracks or wiring conductors for forming electrical connections or for interconnecting the components of the component layer forms in the metallization levels. Wiring conductors in different metallization levels are connected through hole conductors in the electrically insulated layers connected to each other in an electrically conductive manner.
  • the thin Ti layer 24 and then the preferably thicker TiN layer 26 are deposited or produced over the entire area on the carrier structure 10.
  • the barrier layer 22 composed of the Ti layer 24 and the TiN layer 26 and the metal layer 28 together form the single or one of several metallization levels of the programmable circuit structure, the metallization level 20 preferably being the uppermost or last metallization level of the programmable circuit structure.
  • the metallization level 20, which was initially generated over the entire surface, is then structured laterally in order to form wiring conductors or conductor tracks, bond pads or contact areas and other structures.
  • the passivation layer 30 is finally deposited over the entire area on the structured metallization level 20.
  • the passivation layer 30 is preferably produced conformally, i. H. it covers the structured metallization level 20 with an essentially constant layer thickness, its side walls or flanks produced during the structuring and the sections of the carrier structure 10 exposed during the structuring of the metallization level 20.
  • the opening 32 is then produced in the passivation layer 30. This is preferably done in one and the same step together with the creation of openings above the bond pads and possibly further openings in the passiv Crossing layer 30.
  • a photoresist mask is preferably first produced on the passivation layer 30 by means of a photolithographic step, the openings of which in a subsequent etching step enable the local attack of an etching medium on the passivation layer 30 or its local removal. In this case, preferably only the passivation layer 30 is removed, but not the metallization level 20 or the metal layer 28.
  • the openings of the passivation layer 30 above the bond pads and all further openings which are not assigned to a separable conductor structure to be formed are covered in order to prevent the metal layer 28 from being removed in the area of the bond pads in the following etching step.
  • the metal layer 28 is locally removed in a selective etching step in order to form the recess 34 and to expose the barrier layer 22.
  • the region 36 of the barrier layer 22 is thereby exposed.
  • This etching step or the etching medium used in the process are selective in the sense that the metal layer 28 is removed completely, but the barrier layer 22 is not, or not significantly, removed.
  • the opening 32 in the passivation layer 30 and the recess 34 in the metal layer 28 are alternatively formed first.
  • the openings above the bond pads are then created in a separate step.
  • FIG. 3 is a schematic representation of a vertical section through a programmable circuit structure according to a second exemplary embodiment of the present invention, which is also referred to as a via fuse or through-hole fuse.
  • the carrier structure 10 here has a further metallization level 60. This is applied, for example, to a substrate with a component layer and / or further metallization levels, the illustration of which has been omitted.
  • ARC anti-reflective coating
  • An electrically insulating layer 70 is applied over the anti-reflective coating 64, on which in turn the metallization level 20 already known from the first exemplary embodiment and the passivation layer 30 are arranged thereon.
  • a channel or a through hole 72 is formed in the electrically insulating layer 70 and extends from the metallization level 20 to the further metallization level 60.
  • the side walls 74 and the bottom 76 of the through hole 72 adjoining the further metallization level 60 are covered with the barrier layer 22 known from the first exemplary embodiment and form a conductive channel.
  • a recess 34 is arranged above the through hole 72 as in the first exemplary embodiment.
  • the metallization plane 20 in this exemplary embodiment is preferably structured differently laterally.
  • the metallization plane 20 is laterally preferably structured such that the region 28a of the metal layer 28 remaining outside the recess 34 partially or completely surrounds the recess 34.
  • the separable conductor structure 36 formed by the creation of the recess 34 from the barrier layer 22 therefore does not establish a connection between two laterally spaced regions 28a, 28b of a metal layer 28 within the same metallization plane 20 in this exemplary embodiment, but rather a connection between see the area 28a of the metal layer 28 in the metallization level 20 and the further metallization level 60 or the area shown here.
  • the exposed area is locally melted or vaporized and thus interrupted or at least with high resistance, similar to the first exemplary embodiment.
  • the location at which the exposed region 36 of the barrier layer 22 is severed depends on its thickness, the current distribution within it and the thermal conductivity properties of the surrounding materials. If, for example, the thickness of the barrier layer 22 or of the exposed area 36 on the side wall 74 of the through hole 72 is thinner than outside of the through hole 72, the exposed area 36 is very likely to be severed there, especially since the current density on the side wall 74 is also the highest. Most and the heat dissipation are relatively poor.
  • programming i.e. Burning
  • a ring-shaped vaporized, i.e. separated, area are generated.
  • the second exemplary embodiment requires at least two metallization levels 20, 60.
  • the further metal layer 62 is deposited on layers of the carrier structure 10 lying underneath.
  • An antireflection coating 64 is generally produced on the metal layer 62, for example in the form of a thin TiN layer. This layer prevents or reduces disturbing reflections of light on the surface of the further metallization level 60 in subsequent photolithographic steps.
  • the electrically insulating layer 70 which preferably comprises an oxide or a nitride and is also referred to as via oxide, is then produced on the further metallization level 60.
  • the through hole 72 which extends as far as the further metallization level 60, is produced in the electrically insulating layer 70, optionally simultaneously with other through holes.
  • the barrier layer 22 is produced from a Ti layer 24 and a TiN layer 26 over the electrically insulating layer 70 structured in this way.
  • the barrier layer 22 also covers the inner wall or side wall 74 and the bottom 76 of the through hole 72 or the area of the antireflection coating 74 of the further metallization level 60 that is exposed through the through hole 72.
  • the metal layer 28 is produced or deposited over the entire surface of the barrier layer 22, which thereby also fills the through hole 72.
  • the lateral structuring of the metallization level 20, the deposition and opening of the passivation layer 30 and the production of the recess 34 in the metal layer 28 take place as in the first exemplary embodiment.
  • the material of the metal layer 28 is also removed again from the through hole 72.
  • FIG. 4 is a schematic illustration of a vertical section through a third exemplary embodiment of the present invention, which represents a variant of the second exemplary embodiment illustrated with reference to FIG. 3.
  • the third exemplary embodiment shown in FIG. 4 differs from the one shown in FIG. 3 in that the through hole 72 is filled by a through hole conductor 78 in the form of a plug made of tungsten (tungsten plug) or another metal.
  • the use of such the through hole completely filling the electrically conductive through hole conductor is common in CMOS processes and in particular in the case of small and very small structure sizes.
  • the barrier layer 22 is generally produced in front of the plug 78 and therefore covers the side wall 74 and bottom 76 of the through hole 72 in a manner similar to that in the second exemplary embodiment of the present invention illustrated in FIG. 3.
  • the barrier layer 22 and the plug 78 in in the reverse order, so that the plug 78, in contrast to the illustration in FIG. 4, directly adjoins the side wall 74 and the bottom 76 of the through hole 72.
  • the exposed region 36 of the barrier layer 22, i. H. the fusible conductor structure only the flat, substantially annular exposed portion of the barrier layer 22 between the through hole 72 and the portion 28a of the metal layer 28.
  • an area surrounding the through hole which will typically be annular, will burn away becomes.
  • the tungsten plug can remain in the through hole or can be removed therefrom.
  • the programmable circuit structure according to the third exemplary embodiment of the present invention illustrated with reference to FIG. 4 is produced in a method or with similar method steps as the programmable circuit structure of the second exemplary embodiment of the present invention illustrated with reference to FIG. 3.
  • the production method differs only in that after the barrier layer 22 has been deposited or produced, tungsten or another material for producing the plug 78 is first deposited on the barrier layer 22, which in particular fills the through hole 72.
  • the material of the plug is then etched or chemico-mechanically polished (CMP). etched 78 outside of the through hole 72 again. This is followed, as in the second exemplary embodiment illustrated with reference to FIG.
  • FIG. 5 is a schematic illustration of a vertical section through a programmable circuit arrangement according to a fourth exemplary embodiment of the present invention, which is also referred to as a bridge fuse.
  • This exemplary embodiment differs from the first exemplary embodiment illustrated with reference to FIGS. 1A and IB in that the severable conductor structure here is an exposed region 36 of an anti-reflective coating 80 or another conductor layer 80 on the metal layer 28.
  • the anti-reflective coating 80 is the last or uppermost layer within the metallization level 20 and is therefore directly below the passivation layer 30.
  • the exposed area 36 of the passivation layer 30 therefore spans the recess 34 as a self-supporting structure in the form of a web or a bridge and thus connects it the areas 28a, 28b of the metal layer 28. Since the exposed area 36 of the antireflection coating 80 does not essentially adjoin heat-conductive solid material, it has slightly different thermal properties than the exposed area 36 of the barrier layer 22 from that shown in FIGS. 1A and IB first embodiment. In particular, heat released by an electrical current in the exposed area 36 of the antireflection coating 80 flows away to a much lesser extent. As a result, a lower total energy is required in order to cut through the conductor structure that can be severed. Furthermore, structures in the vicinity of the exposed area 36 are subjected to a much lower thermal load.
  • the metal layer 28 is first produced on the carrier structure and then the antireflective coating 80, which is preferably substantially thinner, is subsequently produced thereon. Both together, if appropriate, together with a barrier layer 22 (not shown) form the metallization level 20, which is subsequently structured laterally in order to form conductor tracks or wiring conductors. In this case, a lateral structure is preferably generated at the same time, as was described in connection with FIG. 2 in the first exemplary embodiment.
  • the deposition of the passivation layer 30, the creation of the opening 32 etc. are carried out similarly to the first exemplary embodiment.
  • the etching step for producing the recess 34 in the metal layer 28 or the etching medium used is selective with respect to the antireflection coating 80, so that the metal layer 28 and possibly a barrier 22 are completely removed, while the antireflection coating 80 is not or not significantly removed. will wear.
  • the etching medium penetrates laterally under the anti-reflective coating 80 into the cavity 34. In contrast to the previous exemplary embodiments, it is therefore not possible to use an etching process with an anisotropic characteristic, but rather only a distinctly isotropic etching process.
  • FIG. 6 is a schematic illustration of a vertical section through a programmable circuit arrangement according to a fifth exemplary embodiment of the present invention, which can be understood as a variant of the bridge fuse shown on the basis of the FIG.
  • the severable conductor structure here is an exposed region 36 of a first conductive layer which, like the bar, 1A and 1B are arranged on the underside of the metallization level 20, like the antireflection coating 80 of the fourth embodiment shown in FIG. 5, on the top side of the metallization level 20, but the one intermediate layer 82 is located inside represents the metallization level 20.
  • the metallization level 20 here has a third conductive layer 28 ', the intermediate layer 82 being arranged between these two conductive layers 28, 28'.
  • the metallization level 20 has an anti-reflective coating 80, which is interrupted by the recess 34 as well as the conductive layers 28, 28 '.
  • the exposed region 36 of the intermediate layer 82 as a separable conductor structure connects regions 28a, 28'a, on the one hand, and regions 28b, 28'b, on the other hand, of the metal layers 28, in a web-like or bridge-like manner, as in the fourth exemplary embodiment illustrated with reference to FIG. 5 , 28 'electrically conductive with one another.
  • the exposed area 36 of the intermediate layer 82 is thermally only weakly coupled to its surroundings, as in the fourth exemplary embodiment shown in FIG. 5. This results in the same advantages that were mentioned above for the fourth exemplary embodiment.
  • An additional advantage of the fifth exemplary embodiment shown in FIG. 6 is that the properties of the intermediate layer 82, in particular its thickness and its material, in contrast to those of the antireflection coating 80, can be optimized for the severable conductor structure. In contrast to the anti-reflective coating 80, no consideration needs to be given to the optical properties of the intermediate layer 82.
  • the metal layers 28, 28 ' have the same or different materials and the same, similar or different thicknesses.
  • the metallization level 20 can have further layer layers. ten, in particular, for example, have a barrier layer as in the first three exemplary embodiments of the present invention illustrated with reference to FIGS. 1 to 4.
  • the metal layer 28 is first deposited over the entire area on the carrier structure 10.
  • the intermediate layer 82 is deposited thereon, for example from TiN and preferably with a smaller thickness than the metal layer 28.
  • the metal layer 28 ′ is produced on the intermediate layer 82.
  • the production of the metal layers 28, 28' and the intermediate layer 82 can also be considered such that the deposition of the material of the metal layers 28, 28 'is short after the deposition of a first part interrupted to deposit the intermediate layer 82 and then a second portion of the material.
  • the anti-reflective coating 80 is produced on the metal layer 28 '.
  • the metal layers 28, 28 ', the intermediate layer 82 and the antireflection coating 80 together form the metallization level 20, which is then preferably laterally structured together in order to produce wiring conductors or conductor tracks, as in the previous exemplary embodiments.
  • the manufacturing process is continued in a manner similar to the previous exemplary embodiments with the creation and opening of the passivation layer 30, the covering of passivation openings via bond pads and the selective etching of the metal layers 28, 28 '.
  • This creates two recesses, a recess 34 between regions 28a, 28b of the metal layer 28 and a recess 34 'between regions 28'a, 28'b of the metal layer 28'.
  • the recesses 34, 34 ' lie below or above the region 36 of the intermediate layer 82 thus exposed.
  • the removal of the metal layer 28 proceeds laterally or laterally to form the recess 34. Therefore, only pronounced isotropic etching processes can be used.
  • FIG. 7 is a schematic illustration of a vertical section through a programmable circuit structure according to a sixth exemplary embodiment of the present invention, which represents a further variant of the bridge fuse illustrated with reference to FIG. 5.
  • This exemplary embodiment differs from the fourth exemplary embodiment illustrated in FIG. 5 in that the exposed area 36 of the anti-reflective coating 80 is not arranged in a self-supporting manner but is attached to the underside of a web 84 formed from the passivation layer 30 and mechanically connected to it.
  • This web 84 mechanically stabilizes the exposed area 36 and thereby increases the reliability of the programmable circuit structure.
  • the web 84 increases the heat dissipation from the exposed area 36 of the antireflection coating 80.
  • typical materials of the passivation layer 30, for example oxides or nitrides have a relatively low thermal conductivity.
  • FIG. 8 is a schematic top view of the exemplary embodiment from FIG. 7, which corresponds to that from FIG. 2.
  • the lateral structure of the exemplary embodiment differs from the lateral structure of the first exemplary embodiment illustrated with reference to FIGS. 1A, IB, 2 and from the fourth exemplary embodiment illustrated with reference to FIG. 5 only in that instead of one opening 32 two openings 32a, 32b in the Passivation layer 30 are provided.
  • the openings 32a, 32b laterally adjoin the area in which the antireflection coating 80 is exposed through the recess 34 and thus the exposed area 36 of the antireflection coating 80 is created.
  • the web 84 remains between the openings 32a, 32b preferably has the same lateral structure as the exposed area 36 of the anti-reflective coating 80 and alternatively has a different lateral structure.
  • the metallization level is preferably initially structured wider than the area to be finally exposed.
  • the final structuring of the antireflection coating 80 is then carried out together with the structuring of the passivation layer 30 or when the openings 32a, 32b are created in the passivation layer 30.
  • an etching process or an etching medium is used, which not only removes the passivation layer 30 but also the anti-reflective coating 80 underneath.
  • an etching process or an etching medium is used which, in addition to the metal layer 28, also removes all other layers of the metallization level 20, possibly including a barrier layer (not shown), but not the anti-reflective coating 80.
  • FIGS. 9A, 9B and 9C A problem is described below with reference to FIGS. 9A, 9B and 9C, which can occur depending on the method steps used and the materials used in the production of a programmable circuit structure according to the first exemplary embodiment of the present invention.
  • 9A to 9C represent vertical sections perpendicular to the direction of current flow of the finished severable conductor structure.
  • FIG. 9A shows the programmable circuit structure after generation and lateral structuring of the metallization level 20 and the application of the passivation layer 30 over the entire area. The passivation layer 30 is then structured laterally in order to produce the opening 32. The state thus generated is shown in Fig. 9B.
  • residues 90 of the passivation layer 30, so-called spacers remain on the side walls of the barrier layer 22 and the metal layer 28 produced by the lateral structuring of the metallization plane 20.
  • these spacers 90 in the finished programmable circuit structure shown in FIG. 9C can influence and in particular worsen the burning properties of the severable conductor structure.
  • the spacers 90 can be removed in an additional etching step.
  • the areas of the passivation layer 30 that are not to be removed are also attacked in the process. However, since the spacers 90 are generally thin or narrow, they are completely removed within a short time, during which the passivation layer 30 is only partially removed.
  • the barrier layer 22 and the metal layer 28 of the metallization level 20 are not laterally structured or not only simultaneously. Instead, the barrier layer 22 is at least in the Region or part of the region in which it is later exposed by removing the metal layer 28, laterally structured before the application of the metal layer.
  • the barrier layer 22 is structured in such a way that, as can be seen in FIG. 10A, its width measured transversely to the current flow direction of the later exposed region 36 is less than the width in which the metal layer 28 is structured at this point. In other words, the metal layer 28 laterally overlaps the barrier layer 22. As a result, the barrier layer 22 is spaced apart from the passivation layer 30, material of the metal layer 28 initially being arranged between the barrier layer 22 and the passivation layer 30. In other words, the barrier layer 22 does not touch the passivation layer 30 in the area shown, unlike in FIGS. 9A to 9C.
  • the independent lateral structuring of the barrier layer 22 required for this requires an additional mask and etching step. The lateral structuring of the metal layer 28 is then carried out with a larger lacquer size.
  • FIG. 10B shows the state of the programmable circuit structure after the opening 32 has been created in the passivation layer 30.
  • FIG. IOC shows the state of the programmable circuit structure after the formation of the recess 34 by locally removing the metal layer 28.
  • the barrier layer 22 is now from the remnants 90 spaced.
  • the above exemplary embodiments were shown with specific layer sequences for the metallization level 20, the further metallization level 60, the barrier layer 22 and the anti-reflective coatings 64, 80.
  • the present invention is also possible with different layer follow and can be realized with other materials.
  • the first conductive layer both in the form of the barrier layer 22 and in the form of the anti-reflective coating 80 or the intermediate layer 82 and the second conductive layer in the form of the metal layer 28 each consist of one layer or of a system of several layers.
  • an etching process or an etching medium must be used, in which all layers of the metallization level 20 are selectively removed or removed except for the conductor layer from which the separable conductor structure or the exposed area 36 is formed.
  • the programmable circuit structure according to the invention can also be implemented without using a barrier layer or an antireflection layer to form a conductor structure that can be severed.
  • other conductor layers which are either part of a conventional metallization level or are additionally added, are used to form the separable conductor structure.
  • the severable conductor structure in the form of the exposed region 36 of the first conductive layer preferably has a flat, planar structure, as in the exemplary embodiments shown. It preferably has a thickness of 20 nm to 500 nm measured perpendicular to the metallization plane 20 and a width of 50 nm to 10 ⁇ m measured perpendicular to the direction of current flow and parallel to the metallization plane 20.
  • the severable conductor structure also preferably has a length of 50 nm to 20 ⁇ m measured parallel to the direction of current flow.
  • the arrangements including the Openings 32 in the passivation layer 30 and the recess 34 are axially symmetrical with the through hole 72. Alternatively, however, asymmetrical arrangements are also used.

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

La présente invention concerne une structure de circuit programmable comprenant un conducteur qui présente au moins une première couche conductrice (22) et une seconde couche conductrice (28a, 28b). La seconde couche conductrice (28a, 28b) est retirée de façon localisée, afin de dégager une zone (36) de la première couche conductrice (22) et d'obtenir une zone dégagée (36) de la première couche conductrice (22). Cette zone dégagée (36) de la première couche conductrice (22) peut être sectionnée par application d'un courant de programmation prédéfini sur la structure de circuit.
PCT/EP2003/000684 2003-01-23 2003-01-23 Structure de circuit programmable et procede pour la produire WO2004066384A1 (fr)

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PCT/EP2003/000684 WO2004066384A1 (fr) 2003-01-23 2003-01-23 Structure de circuit programmable et procede pour la produire

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PCT/EP2003/000684 WO2004066384A1 (fr) 2003-01-23 2003-01-23 Structure de circuit programmable et procede pour la produire

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WO2004066384A1 true WO2004066384A1 (fr) 2004-08-05

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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2116828A1 (de) * 1970-04-08 1971-11-04 Rca Corp Elektrischer (Sicherungs ) Schmelzeinsatz
US4089734A (en) * 1974-09-16 1978-05-16 Raytheon Company Integrated circuit fusing technique
US4740485A (en) * 1986-07-22 1988-04-26 Monolithic Memories, Inc. Method for forming a fuse
DE3731621A1 (de) * 1987-09-19 1989-03-30 Texas Instruments Deutschland Verfahren zum herstellen einer elektrisch programmierbaren integrierten schaltung
EP0374690A1 (fr) * 1988-12-19 1990-06-27 National Semiconductor Corporation Structure de connexion fusible programmable permettant la gravure plasma de métaux.
EP0480409A1 (fr) * 1990-10-09 1992-04-15 Nec Corporation Méthode de fabrication d'un contact Ti/TiN/Al comprenant une étape de pulvérisation réactive
DE19600398C1 (de) * 1996-01-08 1997-03-27 Siemens Ag Schmelzsicherung in einer integrierten Halbleiterschaltung, deren Verwendung in einer Speicherzelle (PROM) sowie Verfahren zu ihrer Herstellung
US6249037B1 (en) * 1998-01-29 2001-06-19 Micron Technology, Inc. Integrated circuitry fuse forming methods, integrated circuitry programming methods, and related integrated circuitry

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2116828A1 (de) * 1970-04-08 1971-11-04 Rca Corp Elektrischer (Sicherungs ) Schmelzeinsatz
US4089734A (en) * 1974-09-16 1978-05-16 Raytheon Company Integrated circuit fusing technique
US4740485A (en) * 1986-07-22 1988-04-26 Monolithic Memories, Inc. Method for forming a fuse
DE3731621A1 (de) * 1987-09-19 1989-03-30 Texas Instruments Deutschland Verfahren zum herstellen einer elektrisch programmierbaren integrierten schaltung
EP0374690A1 (fr) * 1988-12-19 1990-06-27 National Semiconductor Corporation Structure de connexion fusible programmable permettant la gravure plasma de métaux.
EP0480409A1 (fr) * 1990-10-09 1992-04-15 Nec Corporation Méthode de fabrication d'un contact Ti/TiN/Al comprenant une étape de pulvérisation réactive
DE19600398C1 (de) * 1996-01-08 1997-03-27 Siemens Ag Schmelzsicherung in einer integrierten Halbleiterschaltung, deren Verwendung in einer Speicherzelle (PROM) sowie Verfahren zu ihrer Herstellung
US6249037B1 (en) * 1998-01-29 2001-06-19 Micron Technology, Inc. Integrated circuitry fuse forming methods, integrated circuitry programming methods, and related integrated circuitry

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