Classifications

• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
  • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
  • G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
  • G01R31/2806—Apparatus therefor, e.g. test stations, drivers, analysers, conveyors
  • G01R31/2808—Holding, conveying or contacting devices, e.g. test adapters, edge connectors, extender boards
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
  • G01R1/02—General constructional details
  • G01R1/04—Housings; Supporting members; Arrangements of terminals
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
  • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
  • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
  • G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
  • G01R31/2805—Bare printed circuit boards

Definitions

• the invention relates to an adapter for testing one or more conductor arrangements.
• the invention relates to an adapter for testing printed circuit boards and other essentially approximately plate-shaped, bare conductor arrangements.
• Such conductor arrangements are e.g. Chip carriers that have a chip side on which contact points are provided for connection to an integrated circuit and have a connection side on which larger contact points are provided for connection to a further conductor arrangement. These contact points on the connection side can be arranged in a regular grid.
• Known devices for testing bare printed circuit boards can basically be divided into two groups.
• the first group includes the devices with adapters, so-called parallel testers, in which all contact points of a circuit board are contacted simultaneously by means of the adapter.
• the second group includes the so-called finger testers. These are devices that scan the individual contact points sequentially with two or more test fingers.
• Test devices with adapters can be found, for example, in DE 42 37 591 A1, DE 44 06 538 A1, DE 43 23276 A, EP 215 146 B1 and DE 38 38413 A1.
• Such adapters basically serve to adapt the uneven configuration of the contact points of the circuit board to be tested to the predetermined basic grid of the electrical test device.
• the contact points are no longer arranged in a uniform grid, which is why the contact pins producing the connection between the contact grid and the contact points are arranged in the adapter with an inclined position or deflection, or a so-called translator is provided, which ensures the uniform contact grid "translated" into the uneven configuration of the contact points.
• These adapters are therefore also known as raster adjustment adapters.
• the individual conductor tracks of bare printed circuit boards are marked for interruptions in the conductor tracks ("interruption test") and for electrical connections to other conductor tracks (“short circuit test”) testing.
• the short-circuit test can include the detection of low-resistance as well as high-resistance connections.
• each conductor track is examined for a short circuit or each branch of a conductor track for an interruption, so that a correspondingly high number of individual measurement processes must be carried out in modern circuit boards with a large number of conductor tracks.
• EP 0 508 062 B1 discloses a method for testing printed circuit boards, in which an inhomogeneous electrical field is applied to the printed circuit board to be examined, an electrical potential which is formed on the basis of the inhomogeneous electrical field being taken from a measuring probe at a contact point and the potential is compared with the potential of other test points and / or with a reference. This method is called field measurement.
• EP 0 508 062 B1 corresponds to US 5,268,645 and EP 0 772 054 A2 corresponds to US 5,903,160. Reference is made in full to the disclosure of these documents and this is incorporated into the present application.
• DE 197 00 505 A1 discloses a method for testing printed circuit boards in which a plurality of power networks and / or ground networks of a printed circuit board are short-circuited and signal networks with a high test voltage are tested for short-circuit with respect to this connection of networks.
• the interconnection of networks is first placed at a high potential and then the individual signal networks are tested against this interconnection. This can drastically reduce the number of tests, which are very time-consuming due to the high voltages, because the signal networks do not have to be tested individually against each power or ground network.
• chip carriers special requirements are placed on the test device.
• Chip carriers are small printed circuit boards or conductor arrangements which have contact points on one side, the chip side, to which one or more integrated circuits without housing can be directly connected and electrically connected to the contact points of the chip carrier by means of bonding.
• the contact points on the chip side are electrically connected by means of conductor tracks to a corresponding contact point on the opposite side of the chip carrier, the connection side.
• the chip carriers can have a spatial structure (see, for example, US Pat. No. 5,006,963).
• the contact points on the chip side are usually arranged very close together and are small. This is referred to in technical jargon as "high-pitch".
• the contact points on the connection side are usually larger and generally arranged in a grid.
• a BGA grid ball grid array grid
• Such chip carriers are described, for example, in MC 2 M® BGA Type Multi-Chip Modules This publication is available on the Internet at www.valtronic.ch Further chip carriers are disclosed, for example, in US 5,066,963.
• the contact points on the chip side of the chip carrier are so finely designed and closely arranged that they cannot be contacted with conventional adapters. It is therefore not possible to test such chip carriers with a parallel tester. Chip carriers are mass products that are manufactured in very large numbers. The contact points on the chip side could be contacted with conventional finger testers. A test with conventional finger testers is not economically viable because the sequential scanning of all contact points takes too much time when testing the chip carrier. For testing chip carriers, special test devices have therefore been developed which have an adapter for contacting the connection side, the contact elements of which are arranged on the connection side in accordance with the contact points of the chip carrier.
• the contact elements of the adapter are usually arranged in a predetermined grid, in particular a BGA grid.
• the chip side of the chip carrier is contacted, however, by means of freely movable contact fingers.
• the devices for testing chip carriers are thus combined parallel / finger testers. With this device, a high throughput can be achieved when testing chip carriers.
• these special devices are very expensive, since both evaluation electronics corresponding to a parallel tester and a finger tester correspond to appropriate evaluation electronics is to be provided and the test device can only be used for very special conductor arrangements, namely chip carriers.
• US 2001/013783 A1 discloses a device for testing bare printed circuit boards.
• This device has a so-called probe section, which is comparable to an adapter and on which a multiplicity of probes are provided.
• a circuit board to be tested is placed on this probe section.
• Test heads are provided which are located on the insulation film with their test probes and can be moved on this for contacting individual circuit board test points.
• the probes of the probe section are connected to evaluation electronics via switching devices.
• the unit consisting of probe section, switching electronics and evaluation device forms a parallel tester.
• DE 44 17 580 C2 discloses a device for testing electronic circuit boards.
• This test device is designed for testing the circuit boards provided with electrical components.
• the test device described therein has an adapter in the form of a nail board on which a circuit board to be tested can be placed.
• the upper side of the board with the electrical components provided therein is contacted by means of a sensor arrangement which has a contact pin which can be moved over the board. Function tests of the individual electrical components are carried out with this device.
• This device is designed similarly to the combined parallel / finger tester explained above.
• DE 38 38 413 A1 discloses an adapter for an electronic test device for printed circuit boards, which has pad-like plugs made of an electrically conductive elastic elastomer on its contact surfaces.
• EP 0 772 054 A2 relates to a method which is used in a finger tester. However, this does not disclose the use of an adapter.
• the invention is therefore based on the object of providing simple, inexpensive means with which bare conductor arrangements, which are chip carriers or are designed similarly to these, can be tested very quickly with a conventional test device.
• An adapter according to the invention for testing one or more conductor arrangements with a plurality of conductor tracks in a finger tester, the conductor arrangements having a side on which contact points are provided which are spaced apart by at least a predetermined distance from the next adjacent contact point, so that this side of the Conductor arrangement can be contacted by means of an adapter, comprises:
• At least one contact field with a set of contact elements the contact elements of the contact field being arranged in an arrangement corresponding to the contact points of the conductor arrangement, wherein
• Contact elements of the contact field are each electrically connected to a further contact element in such a way that the conductor tracks of the conductor arrangement (s) are connected to form a test network, at least on the side (s) of the conductor arrangement (s) not contacted with the adapter a
• the invention thus creates an adapter with which conductor arrangements are contacted on one side, the conductor tracks of the conductor arrangements being electrically connected to one or more further conductor tracks of this or another conductor arrangement.
• the test networks that arise here have at least one contact point on the side of the conductor arrangement that is not contacted with the adapter, so that these test networks can be contacted by means of a test finger of a finger tester. All conductor tracks to be tested are part of a test network that can be contacted on the side of the conductor arrangement that cannot be contacted with the adapter.
• This system consisting of an adapter and one or more conductor arrangements can be arranged in a finger tester and the test networks can be scanned. Due to the fact that several conductor tracks are connected to test networks via the adapter, several conductor tracks are tested at the same time during the individual measuring processes, which considerably increases the test speed compared to a conventional test in a finger tester.
• the adapter itself is not directly connected to evaluation electronics, as is the case with conventional parallel testers, it can be produced simply and inexpensively. This applies in particular if the contact points of the conductor arrangement are arranged in a predetermined, preferably standardized, grid. For such conductor arrangements, under certain conditions even standardized adapters are used, which do not have to be specially designed for the conductor arrangement.
• the conductor tracks of the conductor arrangement (s) are electrically connected to one another via the adapter such that the test networks have at least two contact points on the side of the conductor arrangement (s) not contacted with the adapter.
• the provision of at least two contact points in a test network allows an interruption test of the test network by means of a resistance measurement.
• the conductor tracks of the conductor arrangement can thus be quickly and easily tested for interruptions in a finger tester by means of a resistance measurement.
• the adapters themselves are not connected to the evaluation electronics but only the test fingers to the evaluation electronics.
• the adapters according to the invention are therefore inexpensive to manufacture and expand the field of use of finger testers, since with such an adapter it makes economic sense due to the shortened test time to test certain conductor arrangements with a finger tester, which have so far only been tested with a parallel tester or a specially designed test device.
• the adapter according to the invention also allows the testing of conductor arrangements that have contact points on two sides in a one-sided finger tester.
• the field of application of conventional one-sided finger testers can thus be expanded to conductor arrangements which have contact points on two sides.
• conductor tracks of different conductor arrangements can be electrically connected to one another to form a test network. It is also possible to provide a plurality of conductor arrangements on an adapter, conductor tracks within a single conductor arrangement being electrically connected to one another via the adapter, and conductor tracks of different conductor arrangements being connected to one another by means of the adapter to form a test network.
• test networks can be tested for a short circuit with a single test tap and, if there are corresponding reference guide values, even for an interruption.
• test measurements can be carried out using a known finger tester, the throughput being no less than in the test devices specially designed for testing chip carriers. When using field measurement, the throughput can even be increased.
• FIG. 1 shows two chip carriers in a perspective view with a view of the chip side or the connection side
• FIG. 2 shows the chip carrier from FIG. 1, only the contact points, conductor tracks and plated-through holes and the edge boundaries being shown,
• FIG. 3 shows an adapter according to the invention with the hip carriers from figures 1 and 2,
• FIG. 4 shows an arrangement of the contact pins of the adapter from FIG. 3 together with the chip carrier
• FIG. 5 shows a further adapter according to the invention in a perspective view
• FIG. 6 shows the adapter from FIG. 5, with individual conductor tracks of the adapter being shown, in a top view
• FIG. 7 shows a finger tester in which an adapter according to the invention is inserted
• FIG. 8 a top view of another adapter according to the invention.
• FIG. 9 roughly simplifies the arrangement of interconnected conductor tracks of a chip carrier
• FIG. 10 shows an adapter with chip carriers fixed thereon in a perspective view.
• the adapter has an adapter body 3, which in the present exemplary embodiment is a plastic plate made of a non-electrically conductive material.
• an adapter body 3 which in the present exemplary embodiment is a plastic plate made of a non-electrically conductive material.
• the through bores are arranged in the form of two matrices, each with 10 ⁇ 10 through bores 4.
• the center distance between two adjacent through holes 4 is 0.5-1 mm in each case.
• the through bores 4 are thus formed in a regular, square grid, which corresponds to a ball grid array (BGA).
• BGA ball grid array
• the contact pins 5 each have a test probe 6, 7 at their two ends.
• the contact pins 5 are drawn a large piece from the through hole 4 above in Figure 3.
• the contact pins 5 with their test probes 6, 7 protrude only a few tenths of a mm from the upper and lower surfaces 8, 9 of the adapter body 3.
• the contact pins 5 are preferably so-called spring contact pins, which are formed with a spring element, so that the contact pins 5 can be elastically compressed.
• the contact pins are preferably provided with a frictional engagement means approximately in the area of their longitudinal center, which ensures that the contact pins 5 do not fall out of the through bores 4.
• the test probes 6 and 7 of a matrix of contact pins 5 in the area of one of the two surfaces 8, 9 of the adapter body 3 each form a contact field 17, 18 for contacting a chip carrier 2.
• such a chip carrier 2 is a small printed circuit board which has a chip side 10 and a connection side 11 (FIGS. 1, 2).
• Small contact pads 12 are formed on the chip side 10, which in plan view form a ring of four arcuate segments 13. These contact pads 12 are used for bonding integrated circuits (not shown). From some of these contact pads 12, conductor tracks 14 lead to plated-through hole 15. Usually, or at least almost all contact pads 12 are connected to a conductor track 14 to form a plated-through hole 15. Only a few conductor tracks 14 are shown in FIGS. These vias 15 are formed in the grid of the ball grid array on the chip carrier 2 and each extend from the chip side 10 to the connection side 11.
• the vias 15 each form a contact point 16.
• the vias 15 are Bores with a diameter of e.g. ⁇ 0.1 mm, which are completely coated or filled with an electrically conductive material.
• the electrically conductive material forms a contact pad 16.
• the diameter of the contact pad 16 is significantly larger than the length or width of the contact pads 12 on the chip side 10 and is, for example 0.5 mm.
• the contact points 16 are arranged in the regular grid (BGA grid) explained above, so that they are very far apart from one another in comparison to the contact pads 12 on the chip side 10 and are therefore much easier to contact with an adapter.
• chip carriers are generally formed from a multilayer printed circuit board. For this reason, the plated-through holes in such a chip carrier do not always extend through the entire chip carrier. 1-4 are schematically simplified in this regard.
• connection from the chip side to the connection side is accomplished by means of the plated-through hole. Only in the case of complex chip carriers are conductor tracks provided which connect only two contact points on the chip side to one another and are not guided to the connection side. The number of such traces are, however, small in comparison to those which are led from the chip side to the connection side.
• test such a chip carrier 2 To test such a chip carrier 2, it is placed with its contact points 16 on a set of test probes 6, each of which forms a contact field 17. Another chip carrier 2 is placed with its contact points 16 on the test probes 7, which form a further contact field 18.
• the test probes 6, 7 of the contact fields 17, 18 are electrically connected to one another in pairs via the contact pins 5, so that the contact points 16 of the two chip carriers 2 are electrically connected to one another in pairs (FIG. 4).
• Two pairs of chip carriers 2 can be arranged on the adapter 1 of the present exemplary embodiment, the contact points 16 of the respectively opposite chip carriers 2 being electrically connected to one another in pairs.
• the adapter 1 and the chip carrier 2 are arranged in a finger tester 20 for testing (FIG. 7).
• a finger tester 20 has a plurality of test fingers 21, in each of which a test electrode 22 is integrated.
• the test electrodes 22 are connected to evaluation electronics.
• the test fingers 21 can be moved parallel to the upper or lower surface of the adapter with the aid of the slides 23, parallel to the surfaces of the chip carriers 2, so that the electrodes can be contacted with the contact pads 12 of the chip carriers 2.
• Such a finger tester has, for example, 16 test fingers 21, eight being arranged above and eight below the adapter 1 in order to be able to contact the chip carriers 2 arranged on both sides of the adapter 1.
• the test fingers 21 are each fastened to a slide 23 which can be moved in a plane parallel to the surfaces of the adapter 1.
• the slides 23 are each provided with a vertically aligned actuating cylinder 24 with which the test fingers 21 can be rotated about the vertical axis.
• a movement device is integrated in the test finger 21, with which the test fingers 21 can be moved perpendicular to the surface of the chip carrier 2 in order to contact the contact pads 12 with the test electrodes 22.
• two conductor tracks 25 of two chip carriers 2 are electrically connected to one another and together with the electrical connection of the adapter, which in the present exemplary embodiment (FIGS. 3, 4) are external by the contact pins 5, a test network.
• the ends of such a test network are each formed by a contact pad 12. Since the conductor tracks 25 of the chip carrier are generally not such a test network usually has only two ends. These two ends or the corresponding contact pads 12 can be contacted simultaneously with one test electrode 22 each. If a measuring current is applied to the test network by means of the test electrodes 22 and the resistance of the test network is determined, it can be concluded from this whether the two conductor tracks 25 of the two chip carriers 2 have an interruption.
• chip carriers can thus be tested in a conventional finger tester, at least two chip carriers being tested simultaneously in one test run.
• the throughput of chip carriers to be tested corresponds to that of the special test device explained at the beginning, which has both an adapter and a test finger.
• FIGS. 5 and 6 Another embodiment of an adapter according to the invention is shown in FIGS. 5 and 6.
• This adapter 1 has a multi-layer printed circuit board as the adapter body 3.
• contact knobs 26, 27 are arranged as contact elements instead of the test probes 6, 7 described above, which are formed from an electrically conductive rubber material.
• These contact studs 26, 27 in turn form two contact fields 17, 18, the contact studs 26, 27 being positioned within a contact field in the arrangement corresponding to the contact points 16 of a chip carrier 2 to be tested, so that each contact stud 26 is positioned in each case a contact point 16 can be contacted.
• the contact knobs 26, 27 of the two contact fields 17, 18 are arranged in a matrix arrangement corresponding to a BGA.
• the contact knobs 26 of the contact field 17 are connected in pairs to the contact knobs 27 of the contact field 18, ie in the same row and the same column of the matrix via electrical conductor tracks 28.
• the contact knobs which are provided in the respective contact field 17, 18 at the same position - z. B. each bottom left in Figure 6 - electrically connected.
• Such a pairing of the contact elements of the contact fields 17, 18 has the effect that if two identical chip carriers with the same orientation are placed on the contact fields 17, 18, the same types of conductor tracks 14 of the chip carriers are electrically connected to one another, whereby the test algorithm is considerably simplified, since the same types of conductor tracks 14 are tested together, that is to say that the corresponding contact pads 12 of the chip carriers 2 are to be contacted in order, for example, to carry out an interruption test.
• this adapter has one or more conductor tracks 29 (FIG. 6) which serves as antenna (s) for the field measurement method.
• the field measurement method is described in detail in EP 508 062 B1 and EP 772 054 A2.
• an inhomogeneous electric field is generated by means of the antenna 29 and then the test potential 21 taps from each test network the electrical potential which arises at the test network.
• By comparing with the potential of another test network and / or with a reference it can be determined whether there is a short circuit on the test network. This field measurement thus allows checking for a short circuit of this test network with only one measuring tap on a test network.
• interruptions can also be determined using this field measurement method according to the methods according to EP 0 772 054 A2, only one test tap on the test network being necessary.
• test networks each comprise at least two conductor tracks of two chip carriers 2, at least two conductor tracks are tested simultaneously in a single measurement. Since the field measurement method only requires a single tap to test for interruptions and / or short circuits, several conductor tracks are tested simultaneously with each test tap. As a result, the throughput of chip carriers 2 to be tested is significantly increased even in comparison with the known special devices for testing chip carriers.
• the adapter according to the invention is described above with reference to exemplary embodiments in which the contact elements of the contact fields 17, 18 are connected to one another in pairs.
• chip carriers formed from printed circuit boards it is customary to prepare several chip carriers on one printed circuit board during manufacture. hen, each represent a so-called benefit. For example, five or ten such uses can be provided on a printed circuit board.
• FIG. 8 shows a further adapter which is designed similarly to the adapter shown in FIGS. 5 and 6.
• This adapter 1 has a printed circuit board as the adapter body 3.
• Contact knobs 30 are arranged on the surface of the adapter body 3 as contact elements, which in turn are formed, for example, from an electrically conductive rubber material. These contact knobs form a single contact field 31.
• the contact knobs are each positioned in the arrangement corresponding to the contact points 16 of a chip carrier 2 to be tested, so that one contact point 16 can be contacted with each contact knob 30.
• the contact knobs 30 are arranged in a matrix arrangement of 10 ⁇ 10 corresponding to a BGA.
• the contact knobs 30 are connected to one another in the individual rows of the matrix with conductor tracks 32.
• a conductor track 32 connects every second contact knob 30 to one of the rows.
• Two conductor tracks 32 are provided for each row of contact studs.
• Such a conductor arrangement can be formed directly on the surface of a simple circuit board. A multilayer printed circuit board is not necessary for this.
• five contact knobs 30 are electrically connected to one another. This means that five conductor tracks of the chip carrier 2, if all contact points 16 should be connected to a conductor track 14, are electrically connected to one another.
• Such an adapter can be used for testing chip carriers 2, whose contact points 16 on the connection side 11 in a standardized latching arrangement. are arranged. This means that this adapter can be used for different chip carriers 2, provided the grid of the contact point 16 matches the arrangement of the contact knobs 30. This means that a new adapter does not have to be constructed for a chip carrier in order to test it in a finger tester, provided the arrangement of the contact points 16 of the chip carrier 2 is standardized and with the arrangement of the contact knobs 30 of the adapter 1 matches.
• contact knobs 30 it is of course also possible to link the contact knobs 30 to one another in another way, for example contact knobs of different rows being electrically connected to one another or the number of contact knobs electrically connected to one another being larger or smaller.
• contact elements here: contact knobs 30
• individual conductor tracks 32 can be electrically connected to corresponding conductor tracks in a corresponding further contact field.
• FIG. 9 schematically shows, in a roughly simplified manner, the conductor tracks of a chip carrier 2, which are led from the chip side to the connection side.
• every second conductor track of a row of conductor tracks is electrically connected to one another.
• Two test networks 33, 34 are thus formed in each row.
• the shielded adjacency criterion because each individual conductor track is shielded from an adjacent conductor track from the next neighboring conductor track of the same test network.
• Such a design of the test network ensures that any short circuit between conductor tracks in the chip carrier can be determined by a short circuit test between the corresponding test networks, which can each comprise a large number of conductor tracks.
• such a connection of many interconnects allows a significant reduction in the number of test networks and thus a significant reduction in the number of measurement processes.
• five conductor tracks linked together In the adapter according to FIG. 8, five conductor tracks linked together.
• all interconnects are linked to form only two test networks, which would mean that only a single measurement would have to be carried out in order to test the chip carrier for a short circuit.
• FIG. 10 shows a further adapter according to the invention, which is constructed similarly to the adapter shown in FIG. 3. The same parts are therefore provided with the same reference symbols.
• the adapter 1 has four matrices each with 10 ⁇ 10 through bores 4 for receiving one contact pin 5 each. Eight contact fields are thus formed for receiving eight chip carriers 2.
• Adjacent to an adapter body 3 are antenna plates 35, each of which has a cable 36 for applying a potential to the antenna formed in the antenna plate.
• the corresponding bores for the passage of the contact pins 5 are formed in the antenna plates 35.
• the antenna can be formed in the antenna plate 35 as a contact layer which extends over almost the entire antenna plate 35 and is insulated in the area of only the bore for receiving the contact pins 5. However, the antenna can also have a complex structure.
• two fixing plates 37 are provided, which have the same external dimensions as the adapter body 3 and the antenna plate 35.
• These fixing plates 37 each have four openings 38, which are somewhat smaller than the outline of the chip carrier 2 to be tested.
• the openings 38 are undercut somewhat, so that a circumferential, inwardly projecting limiting web 39 is formed at each opening 38.
• a chip carrier can be inserted into each opening 38, the edge of the chip carrier rests against the boundary web 39.
• the fixing plates 37, the antenna plates 35 and the adapter body 3 have corresponding through bores 40, in which screw connection means 41, i.e. corresponding screws and nuts, with which the fixing plates 37 and the adapter body arranged between them and the antenna plates 35 arranged between them are clamped into a unit, the individual chip carriers being pressed by the fixing plates 37 onto the corresponding contact fields.
• screw connection means 41 i.e. corresponding screws and nuts
• the screw connection means 41 constitute a tensioning device. These tensioning devices are expediently evenly distributed over the surface of the adapter 1, so that a uniformly distributed tension is exerted on the adapter 1.
• This adapter on which the chip carriers are clamped by means of the fixing plates 37, can be arranged and tested as a unit in a finger tester. No additional devices are required in the finger tester itself to accommodate the adapter and the chip carrier.
• An alternative method for testing a circuit board with many uses provides an adapter for testing only one or very few uses, that is to say that this adapter has only one or a few contact fields.
• This adapter is pressed onto the side of the circuit board that can be contacted by the adapter by means of a corresponding mechanism and a corresponding measuring process is carried out. After completing this measurement process, the mechanism is used to remove the adapter from the circuit board, move it for further use and press it against it. Another test measurement process can be carried out.
• the adapter is thus quilted between the individual benefits or between groups of few benefits.
• conductor tracks which are formed on a chip carrier, as antennas instead of antennas specially provided in the adapter.
• the chip carrier has larger, branched conductor tracks, e.g. has a conductor track for a voltage supply or for ground.
• the adapter according to the invention has been explained above on the basis of exemplary embodiments for testing chip carriers.
• an adapter according to the invention not only chip carriers but also any conductor arrangements can be tested which have contact points on one side which are not arranged very closely next to one another and which, for. B. have a distance of at least 0.5 mm.
• the contact points on the other side can be of any design. In particular, they can be arranged very small and close to one another, since such contact points can be easily contacted with the test finger.
• Chip carriers that have a spatial contour in the area of the chip side can also be tested with the adapter according to the invention and a finger tester.
• the invention relates to an adapter for testing a conductor arrangement, in particular for testing a chip carrier.
• a conductor arrangement has contact elements on one side that are not arranged with a high density and have a minimum distance of, for example, 0.5 mm.
• the adapter has at least two contact fields, each with a set of contact elements, with the contact elements of the contact fields each providing a conductor arrangement on the not very densely formed contacts. tact points is contactable.
• the contact elements of one of the contact fields are electrically connected to a contact element of another contact field, so that the conductor tracks of two conductor arrangements are electrically connected to one another and can be tested simultaneously.
• Chip carrier 23 sledges
• Connection side 35 32 conductor track

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• Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• General Physics & Mathematics (AREA)
• General Engineering & Computer Science (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Testing Of Individual Semiconductor Devices (AREA)
• Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
• Testing Or Measuring Of Semiconductors Or The Like (AREA)
• Measuring Leads Or Probes (AREA)
• Tests Of Electronic Circuits (AREA)

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• 2002
  • 2002-12-20 DE DE10260238A patent/DE10260238B4/de not_active Expired - Fee Related
• 2003
  • 2003-11-17 TW TW092132186A patent/TWI234002B/zh not_active IP Right Cessation
  • 2003-11-25 AU AU2003292115A patent/AU2003292115A1/en not_active Abandoned
  • 2003-11-25 KR KR1020057011514A patent/KR100638330B1/ko not_active IP Right Cessation
  • 2003-11-25 JP JP2004562651A patent/JP2006510026A/ja not_active Withdrawn
  • 2003-11-25 WO PCT/EP2003/013253 patent/WO2004059329A1/de active Application Filing
  • 2003-11-25 CN CNA200380103923XA patent/CN1714294A/zh active Pending

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