DE69019436T2 - Adapter für integrierte Schaltkreiselemente und Verfahren unter Verwendung des Adapters zur Prüfung von zusammengebauten Elementen. - Google Patents

Adapter für integrierte Schaltkreiselemente und Verfahren unter Verwendung des Adapters zur Prüfung von zusammengebauten Elementen.

Info

Publication number
DE69019436T2
DE69019436T2 DE69019436T DE69019436T DE69019436T2 DE 69019436 T2 DE69019436 T2 DE 69019436T2 DE 69019436 T DE69019436 T DE 69019436T DE 69019436 T DE69019436 T DE 69019436T DE 69019436 T2 DE69019436 T2 DE 69019436T2
Authority
DE
Germany
Prior art keywords
adapter
integrated circuit
assembled
circuit element
test adapter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69019436T
Other languages
English (en)
Other versions
DE69019436D1 (de
Inventor
Tamio Saito
Toshio Yamamoto
Naoharu Ohikata
Jiro Ono
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Steel Chemical and Materials Co Ltd
Original Assignee
Nippon Steel Chemical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP1190099A external-priority patent/JPH0354842A/ja
Priority claimed from JP1198685A external-priority patent/JPH0362941A/ja
Application filed by Nippon Steel Chemical Co Ltd filed Critical Nippon Steel Chemical Co Ltd
Publication of DE69019436D1 publication Critical patent/DE69019436D1/de
Application granted granted Critical
Publication of DE69019436T2 publication Critical patent/DE69019436T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals
    • G01R31/318538—Topological or mechanical aspects
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G01R1/06—Measuring leads; Measuring probes
    • G01R1/067—Measuring probes
    • G01R1/073—Multiple probes
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
    • G01R31/31905—Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Wire Bonding (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
DE69019436T 1989-07-21 1990-07-20 Adapter für integrierte Schaltkreiselemente und Verfahren unter Verwendung des Adapters zur Prüfung von zusammengebauten Elementen. Expired - Fee Related DE69019436T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP1190099A JPH0354842A (ja) 1989-07-21 1989-07-21 集積回路素子のテスト方法
JP1198685A JPH0362941A (ja) 1989-07-31 1989-07-31 集積回路素子実装用基材

Publications (2)

Publication Number Publication Date
DE69019436D1 DE69019436D1 (de) 1995-06-22
DE69019436T2 true DE69019436T2 (de) 1995-09-28

Family

ID=26505868

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69019436T Expired - Fee Related DE69019436T2 (de) 1989-07-21 1990-07-20 Adapter für integrierte Schaltkreiselemente und Verfahren unter Verwendung des Adapters zur Prüfung von zusammengebauten Elementen.

Country Status (3)

Country Link
US (1) US5150047A (de)
EP (1) EP0414378B1 (de)
DE (1) DE69019436T2 (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5132614A (en) * 1989-08-03 1992-07-21 Kabushiki Kaisha Toshiba Semiconductor device and method and apparatus for testing the same
US5442642A (en) * 1992-12-11 1995-08-15 Micron Semiconductor, Inc. Test signal generator on substrate to test
JPH06249919A (ja) * 1993-03-01 1994-09-09 Fujitsu Ltd 半導体集積回路装置の端子間接続試験方法
US5391993A (en) * 1994-01-27 1995-02-21 Genrad, Inc. Capacitive open-circuit test employing threshold determination
US5457380A (en) * 1994-05-11 1995-10-10 Genrad, Inc. Circuit-test fixture that includes shorted-together probes
US5811980A (en) * 1995-08-21 1998-09-22 Genrad, Inc. Test system for determining the orientation of components on a circuit board
US5787098A (en) * 1996-07-29 1998-07-28 International Business Machines Corporation Complete chip I/O test through low contact testing using enhanced boundary scan
US5818252A (en) * 1996-09-19 1998-10-06 Vivid Semiconductor, Inc. Reduced output test configuration for tape automated bonding
US6199182B1 (en) * 1997-03-27 2001-03-06 Texas Instruments Incorporated Probeless testing of pad buffers on wafer
US6362015B1 (en) * 1998-10-30 2002-03-26 Texas Instruments Incorporated Process of making an integrated circuit using parallel scan paths
US6405335B1 (en) 1998-02-25 2002-06-11 Texas Instruments Incorporated Position independent testing of circuits
US6728915B2 (en) 2000-01-10 2004-04-27 Texas Instruments Incorporated IC with shared scan cells selectively connected in scan path
US6769080B2 (en) 2000-03-09 2004-07-27 Texas Instruments Incorporated Scan circuit low power adapter with counter
US6505317B1 (en) * 2000-03-24 2003-01-07 Sun Microsystems, Inc. System and method for testing signal interconnections using built-in self test
US6965648B1 (en) 2000-05-04 2005-11-15 Sun Microsystems, Inc. Source synchronous link integrity validation

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4386389A (en) * 1981-09-08 1983-05-31 Mostek Corporation Single layer burn-in tape for integrated circuit
DE3235119A1 (de) * 1982-09-22 1984-03-22 Siemens AG, 1000 Berlin und 8000 München Anordnung fuer die pruefung von mikroverdrahtungen und verfahren zu ihrem betrieb
EP0130974A1 (de) * 1982-12-27 1985-01-16 Storage Technology Partners Vlsi chip mit eingebauter testschaltung
US4772936A (en) * 1984-09-24 1988-09-20 United Technologies Corporation Pretestable double-sided tab design
JPS62150728A (ja) * 1985-12-25 1987-07-04 Hitachi Ltd テ−プキヤリアおよびそれを用いた半導体装置
US4806409A (en) * 1987-05-20 1989-02-21 Olin Corporation Process for providing an improved electroplated tape automated bonding tape and the product produced thereby
JPS63306633A (ja) * 1987-06-08 1988-12-14 Toshiba Corp フイルムキヤリア
US4894605A (en) * 1988-02-24 1990-01-16 Digital Equipment Corporation Method and on-chip apparatus for continuity testing
EP0364536A1 (de) * 1988-03-28 1990-04-25 Digital Equipment Corporation Burn-in-anschlussfläche für automatische bandmontagestrukturen
US5008614A (en) * 1988-10-11 1991-04-16 Hewlett-Packard Company TAB frame and process of testing same

Also Published As

Publication number Publication date
EP0414378A3 (en) 1991-09-18
DE69019436D1 (de) 1995-06-22
EP0414378A2 (de) 1991-02-27
US5150047A (en) 1992-09-22
EP0414378B1 (de) 1995-05-17

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee