WO2004059268A1 - 光検出装置 - Google Patents
光検出装置 Download PDFInfo
- Publication number
- WO2004059268A1 WO2004059268A1 PCT/JP2003/016802 JP0316802W WO2004059268A1 WO 2004059268 A1 WO2004059268 A1 WO 2004059268A1 JP 0316802 W JP0316802 W JP 0316802W WO 2004059268 A1 WO2004059268 A1 WO 2004059268A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- circuit
- charge
- level
- capacitance
- integration
- Prior art date
Links
- 230000003287 optical effect Effects 0.000 title abstract description 5
- 230000010354 integration Effects 0.000 claims abstract description 73
- 239000000758 substrate Substances 0.000 claims description 80
- 238000006243 chemical reaction Methods 0.000 claims description 24
- 238000001514 detection method Methods 0.000 claims description 14
- 239000003990 capacitor Substances 0.000 abstract description 8
- 238000005259 measurement Methods 0.000 abstract 2
- 238000010586 diagram Methods 0.000 description 10
- 239000004065 semiconductor Substances 0.000 description 6
- 230000035945 sensitivity Effects 0.000 description 6
- 239000010410 layer Substances 0.000 description 4
- 239000011241 protective layer Substances 0.000 description 4
- 230000000149 penetrating effect Effects 0.000 description 3
- 238000009825 accumulation Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 238000003384 imaging method Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 125000002346 iodo group Chemical group I* 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000013139 quantization Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 238000009738 saturating Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- 238000000844 transformation Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
- G01J1/00—Photometry, e.g. photographic exposure meter
- G01J1/42—Photometry, e.g. photographic exposure meter using electric radiation detectors
- G01J1/44—Electric circuits
- G01J1/46—Electric circuits using a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14634—Assemblies, i.e. Hybrid structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
- H01L27/14658—X-ray, gamma-ray or corpuscular radiation imagers
- H01L27/14663—Indirect radiation imagers, e.g. using luminescent members
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
- H04N23/70—Circuitry for compensating brightness variation in the scene
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
Definitions
- the present invention relates to a photodetector including a plurality of photodiodes arranged.
- the photodetector is a device including a plurality of photodiodes arranged one-dimensionally or two-dimensionally, and an integrating circuit including a pump and an integrating capacitance unit. In some cases.
- an amount of electric charge corresponding to the intensity of light incident on each photodiode is output from the photodiode, and the electric charge is accumulated in the integration capacitance portion.
- the corresponding voltage value is output from the integration circuit.
- Light incident on a photodetection surface on which a plurality of photodiodes are arranged is detected based on a voltage value output from an integration circuit in accordance with the amount of charge generated in each of the plurality of photodiodes.
- the light detection device may further include an AZD conversion circuit that converts a voltage value (analog value) output from the integration circuit into a digital value, and in this case, the intensity of the incident light is set to a digital value. And can be further processed by a computer or the like.
- Such a photodetector can be manufactured by the CMOS technology, and the incident light intensity detection can be performed by changing the capacitance value of the integration capacitance section included in the integration circuit.
- the dynamic range can be expanded. For example, the document ⁇ S.L.
- the integration circuit has an integration capacitance section having a variable capacitance value between the input and output terminals of the amplifier, and accumulates the charge output from the photodiode in the integration capacitance section. A voltage value corresponding to the amount of the stored electric charge is output.
- the dynamic range for detecting the intensity of the incident light is expanded by appropriately setting the capacitance value of the integration capacitance section by external control.
- the detection sensitivity is increased even when the incident light intensity is low, while increasing the capacitance value of the integration capacitance unit.
- the saturation of the output signal is avoided.
- this photodetection device expands the dynamic range of the incident light intensity detection by appropriately setting the capacitance value of the integration capacitance unit every time an image is captured, but the incident light of each pixel in one screen is increased. This does not increase the dynamic range of intensity detection.
- the photodetector disclosed in this International Publication includes an integration circuit having an integration capacitance section having a variable capacitance value, and a charge level determination for determining a level of a charge generated in each photodiode. And a circuit. Then, one of the plurality of photodiodes is selected, the level of the amount of charge generated by the selected photodiode is determined by a charge level determination circuit, and the determined charge is determined.
- the capacitance value of the integration capacitance section is set based on the quantity level, and thereafter, the operation of accumulating the charges generated by the selected photodiode is started in the integration circuit.
- the present invention has been made in order to solve the above problems, and has a wide dynamic range of incident light intensity detection, and a light detection method capable of detecting incident light intensity at high speed. It is intended to provide a device.
- the photodetector comprises: (1) N (N is an integer of 2 or more) photodiodes each generating an amount of electric charge according to the intensity of incident light; and ( 2 ) N N charge amount level determination circuits that are provided for each of the photodiodes, determine the level of the amount of charge generated in each photodiode, and output a level signal indicating the level determination result; 3) It has an integral capacitance section whose capacitance value is variable and the capacitance value is set based on the level signal, and accumulates the electric charge inputted to the input terminal in the integral capacitance section, and the amount of this accumulated electric charge And (4) a first switch provided corresponding to each of the N photodiodes and provided between each photodiode and an input terminal of the integration circuit. And (5) N charge level judgment circuits respectively And a second switch provided between each charge level determination circuit and the integration capacitance section.
- an amount of charge is generated according to the intensity of light incident on the photodiode, and the level of this charge is determined by the charge level determination circuit. Then, based on the determined charge amount level, the integration circuit The capacitance value of the integral capacitance section is set. Thereafter, in the integration circuit, the charge generated by the photodiode is accumulated in the integration capacitance section, and a voltage signal having a value corresponding to the amount of the accumulated charge is output.
- the capacitance value of the variable capacitance section of the integrating circuit is set to a relatively large value, and even if the incident light intensity is large, the incident light intensity is detected without saturation.
- the capacitance value of the variable capacitance section of the integrating circuit is set to a relatively small value, and the incident light intensity is detected with high sensitivity even when the incident light intensity is small. Also, in this photodetector, since the charge level determination circuit is provided for each photodiode in a one-to-one manner, the capacitance value of the integration capacitance part of the integration circuit is set quickly, and the incident light can be quickly detected. The intensity can be detected.
- the photodetector according to the present invention receives a voltage value output from an output terminal of an integration circuit, converts the voltage value into an AZD, and outputs a digital value corresponding to the voltage value. It is preferable to further include an A / D conversion circuit. In this case, the voltage value output from the integration circuit is input to the AZD conversion circuit and converted to a digital value, and this digital value is output from the A / D conversion circuit.
- the photodetector according to the present invention receives the digital value output from the AZD conversion circuit, shifts the bit of the digital value according to the level signal, and shifts this bit. It is preferable to further include a shift circuit that outputs a digital value. In this case, the digital value output from the A / D conversion circuit is output after the bit is shifted by the shift circuit according to the charge level determined by the charge level determination circuit.
- the integration capacitance section can be set to the first capacitance value or the second capacitance value, and the first capacitance value is 2P times the second capacitance value ( p is an integer of 1 or more), and it is preferable that the A / D conversion circuit outputs the digital of the number of bits of p or more, and the shift circuit shifts the digital value by p bits according to the level signal. .
- the digital value output from the AZD conversion circuit is shifted by p bits as necessary, so that the obtained digital value can be reduced by the incident light intensity. JP2003 / 016802
- the photodetector according to the present invention further includes a control circuit that controls opening and closing of each of the first switch and the second switch, wherein the control circuit is configured to control each of the N photodiodes.
- the second switch corresponding to the photodiode is closed, and after the capacitance value of the integration capacitance section is set based on the level signal output from the charge level determination circuit corresponding to the photodiode, the second switch corresponding to the photodiode is set.
- the first switch is closed. In this case, the capacitance value of the integration capacitance section of the integration circuit is quickly set, and the incident light intensity is detected at high speed.
- the photodetector according to the present invention includes N photodiodes, N charge level determination circuits, and an integration circuit as one set, and M sets (M is an integer of 2 or more). Preferably it is provided. In this case, since MXN photodiodes are arranged, the number of pixels can be further increased.
- the photodetector according to the present invention includes: (1) N photodiodes are provided on a first substrate, and (2) N charge amount level determination circuits and integration circuits are provided on a second substrate. A first switch and a second switch are provided. (3) The first substrate and the second substrate are bump-connected to each other, and the corresponding photodiode and the first switch are electrically connected to each other. It is preferable that the photodiodes and the charge level determination circuit corresponding to each other are electrically connected to each other. In this case, each of the first substrate and the second substrate can be manufactured by an optimal manufacturing process, which is preferable in improving the integration.
- FIG. 1 is an overall configuration diagram of the photodetector 1 according to the present embodiment.
- FIG. 2 is a partial configuration diagram of the photodetector 1 according to the present embodiment.
- Figure 3 is a circuit diagram of the electric charge amount level implementation included in the optical detection apparatus 1 according to the decision circuit 1 0 m, n and integrating circuit 2 0 m.
- FIG. 4 is a timing chart for explaining the operation of the photodetector 1 according to the present embodiment. It is Ngiyatto.
- FIG. 5 is a perspective view showing an arrangement relationship between the first substrate 100 and the second substrate 200 in the photodetector 1 according to the present embodiment.
- FIG. 6 is a diagram illustrating an example of a cross section of the first substrate 100 and the second substrate 200 in the photodetector 1 according to the present embodiment.
- FIG. 7 is a diagram illustrating another example of a cross section of the first substrate 100 and the second substrate 200 in the photodetector 1 according to the present embodiment.
- FIG. 1 is an overall configuration diagram of a photodetector 1 according to the present embodiment.
- FIG. 2 is a partial configuration diagram of the photodetector 1 according to the present embodiment.
- FIG. 2 shows details of the blocks X ⁇ to XM within the range Y indicated by the dotted line in FIG.
- Photodetector 1 shown in Fig of these is provided with a set of M units Ui ⁇ U M, A / D conversion circuit 30, a shift circuit 40 and control circuit 50.
- Each unit U m has a similar configuration to each other, and has N photodiodes.
- Each of the photodiodes PD m and n generates an electric charge Q in an amount corresponding to the intensity of incident light.
- Switch SWl m, n is provided a photodiode PD m, corresponding to the n between the input terminal of the photodiode PD m, n and integrating circuit 20 ⁇ , it is electrically opened and closed.
- the electric charge amount level determining circuit 10 m, n is Fotodaiodo PD m, provided with corresponds to n, the Fotodaiodo PD m, level of the amount of charge Q generated in the n And outputs a level signal Level indicating the level determination result.
- the level signal Level is a digital signal of one bit or a plurality of bits, and the switches SW2 m and n include switches corresponding to the number of bits.
- the integrating circuit 20 m has an integral capacitor unit capacitance value is variable, Fotodaiodo PD m, n and Suitsuchi SWl m, is input through the n are connected. Then, the integrating circuit 20 m, these switches SWl m, i ⁇ SWl m, Fotodaiodo PD m successively opened and closed with the N of N, I ⁇ PD m, N are sequentially outputted from each said input accumulated charge Q entered to the end of the integration capacitor unit, and outputs from the output terminal a voltage value [nu 20 corresponding to the amount of the accumulated electric charge Q.
- the integral capacitance part, the charge amount level-format Teikairo 10 m, n and Suitsuchi SW2 ⁇ , are connected via the n, with the sequential opening and closing of these Suitsuchi SW2 m> 1 ⁇ SW2 m, N N Charge level judgment circuit 10 m , i ⁇
- the capacitance value is set based on the level signal Level that is sequentially output from each of 10 m and N.
- the A / D conversion circuit 30 inputs the voltage V20, which are sequentially outputted through the Suitsuchi S W3 m from the output terminal of the integrating circuit 20 m, the voltage value V 20 and AZD Transformations, this and outputs a digital value corresponding to the voltage value V 20.
- Shift circuit 40 inputs the digital values output from the A Bruno D conversion circuit 30, a charge amount leveled Honoré decision circuit 1 O m, i ⁇ l 0 m, N Suitsuchi SW2 m from each, n Oyo the Pi Suitsuchi SW4 level signal level outputted through m are sequentially input, it shifts the bits of the digital value according to the level signal level, and outputs the digital value obtained by shifting the bit.
- the control circuit 50 controls the overall operation of the photodetector 1. You. In particular, the control circuit 50 controls the switch SWl m, n and the switch SW2 ⁇ , the opening and closing of n their respective. Specifically, for each photodiode PD m , n , the control circuit 50 closes the corresponding switch SW2 m , n and sets the level signal Level output from the corresponding charge amount level determination circuit 1 O m , n. after the capacitance value of the integral capacitance part in the integrating circuit 2 O m is set based, corresponding Suitsuchi SWl m, it closes the n, and starts the integrating operation of the integrating circuit 2 O m.
- control circuit 50 also controls the operation timing of each of the integration circuit 20 m , the switch SW3 m , the switch SW4 m , the AZD conversion circuit 30 and the shift circuit 40. This operation timing will be described later in detail. In FIG. 1, illustration of control signals sent from the control circuit 50 to other element circuits is omitted.
- FIG. 3 is a circuit diagram of the charge level determination circuits 10 m and n and the integration circuit 20 m included in the photodetector 1 according to the present embodiment. In this figure, only the portion corresponding to the n-th photodiode PD m , n in the m- th unit U m is shown.
- the charge level determination circuits 10 m and n have three comparators 11 to 13 and a control unit 14. Each of the non-inverting input terminals of the comparators 11 to 13 is connected to a connection point between the cathode terminal of the photodiode PD m , n and the switch SW 1 m , n .
- To the inverting input terminal of the comparator 11 is input the reference voltage value V refl, comparator 12 inputs the reference voltage value V ref2 to the inverting input terminal of the comparator reference voltage to the inverting input terminal of the 13 V ref3 Is entered.
- each of the comparators 11 to 13 compares the voltage values input to the non-inverting input terminal and the inverting input terminal with each other, and outputs a signal representing the comparison result to the control unit 14.
- the control unit 14 receives the signals output from the comparators 11 to 13 and outputs a 3-bit level signal Level for setting the capacitance value of the integration capacitance unit of the integration circuit 20 m .
- Vrefl V sa t / 2 ⁇ (la)
- V SAT / 8 VPD ⁇ V SAT / 4
- Level signal Level that will be output from the control unit 14 shows how potential V PD is in any range of the expression (2a) ⁇ (2d) equation.
- the integrating circuit 2 O m has an amplifier A, capacitive element C 0 -C 3 and switch SW 0 to SW 3.
- Input terminal of the amplifier A is Suitsuchi SWl m, through n, are connected Fotodaiodo PD m, to the cathode terminal of the n.
- An output terminal of the amplifier A is connected to the A / D converter circuit 30 via the switch SW3 m.
- Switch SWi and capacitor Ci connected in series with each other, Switch SW 2 and capacitor C 2 connected in series with each other, switch SW 3 and capacitor C 3 connected in series with each other, capacitor C 0 , and switch SWo are provided in parallel between the input and output terminals of the amplifier A.
- Capacitance element C. -C 3 and switch SWi ⁇ SW 3, the capacitance value constitutes a variable integral capacitance part 21. That is, the Suitsuchi SWi ⁇ SW 3 respectively, to open and close the charge amount level determining circuit 10 m, is output from the control section 14 of the n switches SW2 m, based on the level signal Level input through n, depending on the open or closed state Thus, the capacitance value of the integral capacitance unit 21 is determined.
- the capacitance value of each of the capacitive elements C 0 to C 3 is
- Ci C ⁇ (3b)
- C 2 2 C-(3 (;)
- a / D converter circuit 30 by entering the are outputted from the output voltage value V 20 obtained by sequentially reach through the switch SW3 m of the integrating circuit 20 m of each Yunitto U m, the voltage the values V 20 and AZD conversion, and outputs a digital value corresponding to the voltage value V 20.
- the voltage value V 20 input to AZD conversion circuit 30 is always in the range of equation (4),
- a / D conversion circuit 30, the voltage value V 20 in converting A / D the output All bits of the digital value to be used can be used effectively.
- the shift circuit 40 inputs the digital value output from AZD conversion circuit 30, output from the charge level determination circuit 1 Omj l 0 m, N respectively
- the input level signals Level are sequentially input, the bits of the digital / level value are shifted according to the level signal Level, and the digital / level values obtained by shifting the bits are output. That is, the digital value output from the AZD conversion circuit 30 is a digital value of K bits (K is an integer of 2 or more) (DE ⁇ DKA- ,
- the shift circuit 40 outputs a digital value of (K + 3) bits. If the level signal Level indicates that the potential VPD is within the range of the above equation (2a), the shift circuit 40 does not shift the input digital value, but shifts the digital value of (K + 3) bits.
- potential VPD indicates the level signal level that is in the range of the (2c) formula Shifts the input digital value upward by 2 bits and outputs the (K + 3) -bit digital value ( ⁇ , ⁇ - ⁇ ⁇ . ⁇ ' ⁇ , ⁇ , ⁇ , ⁇ ).
- the input digital value is shifted upward by three bits, and the (K + 3) -bit digital value ( DK-I, DK-2; - "D 1, DO, 0,0,0) and outputs a.
- FIG. 4 is a timing chart illustrating the operation of the photodetector 1 according to the present embodiment.
- the switches corresponding to the photodiode PDn ⁇ .i are shown in order from the top.
- N switches SW2 m> 1 to SW2 m , N (n — Only the 1) th switch SW 2 m , n -i is closed and the (n-1) th charge level determination circuit 1
- the level signal output from the control unit 14 of ⁇ ⁇ is integrated by the integration circuit enter the 2 O m, the capacitance value of the integral capacitance part 21 in the integrating circuit 2 O m is set based on Konorebe Honoré signal.
- the level signal at this time is determined by the three comparators 11 to 13 of the charge level determination circuits 1 O m and n at the time t tt -i, 2 and the photodiode held by the control unit 14. It indicates the level of the potential V at the cathode terminals of PD m and n . Further, it switches SWo of the integrating circuit 2 0 ⁇ is closed at time, the voltage value v 20 outputted from the integrating circuit 2 O m is initialized.
- each Fotoda Iodo PD ⁇ , charge amount level determining circuits against n 1 O m, n is provided, the photo Since an appropriate capacitance value according to the amount of charge output from the diodes PD m and n is set in the integration capacitance unit 21 of the integration circuit 2 O m , each photodiode (ie, a pixel in one screen) In each case, the dynamic range of incident light intensity detection can be expanded.
- the charge level determination circuit 1 O m , n is provided for each photodiode PD m , n on a one-to-one basis, the capacitance value of the integration capacitance part 21 of the integration circuit 2 O m is obtained. Is set quickly, and the incident light intensity can be detected at high speed. Further, the individual charge level determination circuits 1 O m , n do not require high-speed processing when determining the charge level, so that the power consumption is small.
- FIG. 5 is a perspective view showing an arrangement relationship between the first substrate 100 and the second substrate 200 in the photodetector 1 according to the present embodiment.
- the photodetector 1 is divided on two substrates, a first substrate 100 and a second substrate 200.
- MxN photodiodes PDI, I to PDM, N are arranged in M rows and N columns.
- FIG. 6 is a diagram illustrating an example of a cross section of the first substrate 100 and the second substrate 200 in the photodetector 1 according to the present embodiment.
- the basic patterns are repeated in the left and right directions, only one basic pattern will be described below.
- the first substrate 100 is provided on the first surface (the upper surface in the figure) of the n-type semiconductor substrate together with the n-type substrate! A p + region 111 forming an n-junction to form a photodiode PD and an n + region 112 serving as an isolation region are formed.
- the first substrate 100 is formed on the second surface (the lower surface in the figure) of the n-type semiconductor substrate with an n + -type impurity layer 121 forming an ohmic connection with the bonding pad 124.
- An insulating protective layer 122 for protecting the surface and a bonding pad 124 penetrating through the protective layer 122 and electrically connected to the n + -type impurity layer 122 are formed. ing.
- the first substrate 100 is provided with a through-hole penetrating between the first surface and the second surface, and in the through-hole, a through-electrode 1 is formed via an insulator layer formed on the inner wall. 31 is provided. Then, on the first surface side of the first substrate 100, a metal wiring 1 13 electrically connecting the p + region 1 1 1 and the through electrode 1 3 1 is formed on the insulating film 1 1 4; On the second surface side, a bonding pad 123 electrically connected to the through electrode 131 is formed.
- the second substrate 200 is provided on the first surface (the upper surface in the figure) of the semiconductor substrate with bonding pads 2 2 3 electrically connected to the first end of the switch SW1. Further, a bonding pad 224 electrically connected to the ground potential is formed. Then, the bonding pads 123 of the first substrate 100 and the bonding pads 222 of the second substrate 200 are connected to each other by bumps 423. The bonding pads 124 of the plate 100 and the bonding pads 222 of the second substrate 200 are connected to each other by bumps 424. The gap between the first substrate 100 and the second substrate 200 is filled with resin.
- a scintillator 5100 and a shielding member 5200 are arranged on the side of the first surface of the first substrate 100.
- the scintillator 5100 is provided above the p + region 11 of the first substrate 100, and generates scintillation light when an energy ray such as an X-ray is incident.
- the shielding plate 520 is provided above the n + region 112 of the first substrate 100, and blocks transmission of energy rays such as X-rays and fixes the scintillator 510.
- the scintillator 510 when an energy ray such as an X-ray is incident on the scintillator 510, the scintillator 510 generates scintillation light. Further, when the scintillation light enters the p + region 111 of the first substrate 100, electric charges are generated at the pn junction. The electric charge is transferred to the second substrate 200 through the metal wiring 1 13, the penetrating electrode 13 1, the bonding pad 1 2 3, the bump 4 2 3, and the bonding pad 2 2 3 of the second substrate 200. The signal is input to the input terminal of the integration circuit 20 via the switch SW1 formed in the circuit.
- FIG. 7 is a diagram illustrating another example of a cross section of the first substrate 100 and the second substrate 200 in the photodetector 1 according to the present embodiment. Note that, also in this figure, since the basic pattern is repeated in the left-right direction, only one basic pattern will be described below.
- the first substrate 100 is formed on the first surface (the upper surface in the figure) of the n-type semiconductor substrate, with an n + -type accumulation layer 151 for preventing charge recombination, An insulating protective layer 152 for protecting the surface is formed.
- the first substrate 100 is formed on the second surface (lower surface in the figure) of the n-type semiconductor substrate by forming an i> n junction with the n-type substrate to form a photodiode PD. 161 are formed, an ⁇ + region 162 as an isolation region is formed, and a protective layer 163 is formed thereon. Have been.
- a bonding pad 164 electrically connected to the + region 161, and a bonding pad electrically connected to the n + region 162. 1 and 6 are formed.
- the second substrate 200 is provided on the first surface (the upper surface in the figure) of the semiconductor substrate with bonding pads 2664 electrically connected to the first end of the switch SW1 and Bonding pads 265 are formed. Then, the bonding pad 164 of the first substrate 100 and the bonding pad 264 of the second substrate 200 are connected to each other by a bump 464. The bonding pads 165 of the first substrate 100 and the bonding pads 265 of the second substrate 200 are connected to each other by bumps 465. The gap between the first substrate 100 and the second substrate 200 is filled with resin.
- a scintillator 5100 and a shielding material 5200 are arranged on the side of the first surface of the first substrate 100.
- the scintillator 5100 is provided above the p + region 161 of the first substrate 100, and generates scintillation light when an energy ray such as an X-ray is incident.
- the shielding plate 5200 is provided above the n + region 162 of the first substrate 100, and blocks transmission of energy rays such as X-rays and fixes the scintillator 510.
- the first substrate 100 has its thickness reduced by grinding the first surface side in the portion where the p + region 161 is formed. In the configuration shown in FIG.
- the photodetector 1 configured as described above has the following configuration. The following effects can be obtained. That is, the charge transfer path from each photodiode PD m , n to the input terminal of the integration circuit 2 O m is shortened, and the parasitic capacitance in the wiring on the path is reduced, and therefore, the integration circuit 2 O m The noise included in the voltage value output from the device is small, and accurate light detection can be performed.
- the first substrate 1 0 0 Ino circuit for signal processing such as integrating circuit 2 O m is such provided, it is possible to increase or density of the number of pixels.
- each of the first substrates 100 provided with the photodiodes is provided.
- the zeros can be arranged very close or in contact.
- a second substrate 2 0 0 the signal processing circuit such as the integrating circuit 1 O m is formed, it is possible to adopt an optimum manufacturing process So it is also good in this regard.
- the present invention is not limited to the above-described embodiment, and various modifications are possible.
- the cross-sectional structures of the first substrate 100 and the second substrate 200 are not limited to those shown in FIGS. 6 and 7, respectively.
- another circuit may be provided on the second substrate 200.
- the number of thresholds for determining the charge level in the charge level determination circuit 1 O m , n is arbitrary, and according to this number, the capacitance that the integration capacitance section of the integration circuit 2 O m can have The number of values is determined.
- an amount of charge is generated according to the intensity of light incident on the photodiode, and the level of this charge is The determination is made by the quantity level determination circuit. Then, the capacitance value of the integration capacitance section of the integration circuit is set based on the determined charge amount level. Thereafter, in the integration circuit, the charge generated by the photodiode is accumulated in the integration capacitance section, and a voltage signal having a value corresponding to the accumulated charge is output.
- the capacitance value of the variable capacitance section of the integrating circuit is set to a relatively large value, and the incident light intensity is detected without saturation even if the incident light intensity is large.
- the capacitance value of the variable capacitance section of the integrating circuit is set to a relatively small value, and the incident light intensity is detected with high sensitivity even when the incident light intensity is small.
- the capacitance value of the integration capacitance part of the integration circuit is set quickly, and the speed is high. The incident light intensity can be detected.
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Spectroscopy & Molecular Physics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Photometry And Measurement Of Optical Pulse Characteristics (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
- Light Receiving Elements (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
Description
Claims
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE60336077T DE60336077D1 (de) | 2002-12-25 | 2003-12-25 | Optischer sensor |
EP03786322A EP1577652B1 (en) | 2002-12-25 | 2003-12-25 | Optical sensor |
US10/540,476 US7642496B2 (en) | 2002-12-25 | 2003-12-25 | Photodetector including a plurality of photodiodes |
AU2003296124A AU2003296124A1 (en) | 2002-12-25 | 2003-12-25 | Optical sensor |
US12/382,290 US20090184237A1 (en) | 2002-12-25 | 2009-03-12 | Photodetector |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002-375115 | 2002-12-25 | ||
JP2002375115A JP4663956B2 (ja) | 2002-12-25 | 2002-12-25 | 光検出装置 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/382,290 Continuation US20090184237A1 (en) | 2002-12-25 | 2009-03-12 | Photodetector |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2004059268A1 true WO2004059268A1 (ja) | 2004-07-15 |
Family
ID=32677325
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2003/016802 WO2004059268A1 (ja) | 2002-12-25 | 2003-12-25 | 光検出装置 |
Country Status (7)
Country | Link |
---|---|
US (2) | US7642496B2 (ja) |
EP (1) | EP1577652B1 (ja) |
JP (1) | JP4663956B2 (ja) |
CN (1) | CN100501355C (ja) |
AU (1) | AU2003296124A1 (ja) |
DE (1) | DE60336077D1 (ja) |
WO (1) | WO2004059268A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8912499B2 (en) | 2010-03-16 | 2014-12-16 | Kabushiki Kaisha Toshiba | Radioactive ray detecting apparatus, method of manufacturing the same, and imaging system |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FI121724B (fi) * | 2005-04-12 | 2011-03-15 | Planmeca Oy | CCD-sensorijärjestely ja menetelmä panoraama- ja/tai kalloröntgenkuvausta varten |
JP4931367B2 (ja) * | 2005-04-28 | 2012-05-16 | シャープ株式会社 | 検出装置及びそれを備えた表示装置 |
JP4825116B2 (ja) * | 2006-11-22 | 2011-11-30 | 浜松ホトニクス株式会社 | 固体撮像装置及び撮像方法 |
JP5475057B2 (ja) * | 2012-04-20 | 2014-04-16 | 株式会社 オフィス・カラーサイエンス | 変角分光イメージング測定方法およびその装置 |
US9945774B2 (en) | 2012-04-24 | 2018-04-17 | Siemens Healthcare Diagnostics Inc. | Channel light measurement apparatus having reduced signal-to-noise ratio |
JP5878444B2 (ja) * | 2012-09-04 | 2016-03-08 | 富士フイルム株式会社 | 放射線画像検出装置 |
US9106336B1 (en) * | 2012-09-14 | 2015-08-11 | Google Inc. | Photo-sensor array to adjust alignment of optical receiver |
FR3006500B1 (fr) * | 2013-06-04 | 2016-10-28 | Centre Nat De La Rech Scient - Cnrs - | Capteur cmos a photosites standard |
CN106289333B (zh) * | 2015-05-29 | 2019-01-25 | 苏州坤元微电子有限公司 | 电容充放电控制模块以及电流频率转换电路 |
EP3685131B1 (en) | 2017-09-19 | 2022-09-07 | Beckman Coulter, Inc. | Analog light measuring and photon counting in chemiluminescence measurements |
JP2019057873A (ja) * | 2017-09-22 | 2019-04-11 | ソニーセミコンダクタソリューションズ株式会社 | 固体撮像素子及び電子機器 |
CN111786659A (zh) * | 2020-06-22 | 2020-10-16 | 西安交通大学 | 一种宽范围高精度电荷脉冲生成电路及工作方法 |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63204131A (ja) * | 1987-02-19 | 1988-08-23 | Olympus Optical Co Ltd | 光電変換素子アレイの蓄積時間制御装置 |
JPS63205527A (ja) * | 1987-02-20 | 1988-08-25 | Sanyo Electric Co Ltd | 測光回路 |
JPH10142051A (ja) * | 1996-11-13 | 1998-05-29 | Nec Corp | 撮像装置 |
JP2000310561A (ja) | 1999-04-27 | 2000-11-07 | Hamamatsu Photonics Kk | 光検出装置 |
JP2001054020A (ja) * | 1999-08-10 | 2001-02-23 | Minolta Co Ltd | 固体撮像装置 |
JP2001141562A (ja) * | 1999-11-15 | 2001-05-25 | Hamamatsu Photonics Kk | 光検出装置 |
JP2001291877A (ja) * | 2000-04-05 | 2001-10-19 | Hamamatsu Photonics Kk | 固体撮像装置 |
EP1154483A1 (en) | 1998-07-08 | 2001-11-14 | Hamamatsu Photonics K.K. | Solid-state imaging device |
WO2002012845A1 (fr) | 2000-08-03 | 2002-02-14 | Hamamatsu Photonics K.K. | Detecteur optique |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH082165B2 (ja) | 1986-02-28 | 1996-01-10 | 本田技研工業株式会社 | 携帯用エンジン発電機 |
JPS62203531U (ja) * | 1986-06-18 | 1987-12-25 | ||
JPH03262932A (ja) * | 1990-03-14 | 1991-11-22 | Fuji Electric Co Ltd | 電荷蓄積形光センサ回路 |
JPH0754823Y2 (ja) * | 1990-04-18 | 1995-12-18 | 株式会社アドバンテスト | 光強度測定装置 |
JPH0530431A (ja) * | 1991-07-18 | 1993-02-05 | Konica Corp | 固体撮像装置の露光時間制御回路 |
JPH07333348A (ja) * | 1994-06-03 | 1995-12-22 | Toshiba Corp | 放射線検出器およびこれを用いたx線ct装置 |
JPH0933979A (ja) * | 1995-07-19 | 1997-02-07 | Olympus Optical Co Ltd | 露出測光装置 |
JP3957803B2 (ja) * | 1996-02-22 | 2007-08-15 | キヤノン株式会社 | 光電変換装置 |
DE19959539A1 (de) * | 1999-12-09 | 2001-06-13 | Thomson Brandt Gmbh | Bildaufnehmer |
JP4054168B2 (ja) * | 2000-08-10 | 2008-02-27 | 日本放送協会 | 撮像デバイス及びその動作方法 |
JP4628586B2 (ja) | 2001-05-14 | 2011-02-09 | 浜松ホトニクス株式会社 | 光検出装置 |
JP3977735B2 (ja) * | 2002-12-25 | 2007-09-19 | 浜松ホトニクス株式会社 | 光検出装置 |
-
2002
- 2002-12-25 JP JP2002375115A patent/JP4663956B2/ja not_active Expired - Fee Related
-
2003
- 2003-12-25 US US10/540,476 patent/US7642496B2/en not_active Expired - Fee Related
- 2003-12-25 AU AU2003296124A patent/AU2003296124A1/en not_active Abandoned
- 2003-12-25 CN CNB2003801077797A patent/CN100501355C/zh not_active Expired - Fee Related
- 2003-12-25 EP EP03786322A patent/EP1577652B1/en not_active Expired - Lifetime
- 2003-12-25 DE DE60336077T patent/DE60336077D1/de not_active Expired - Lifetime
- 2003-12-25 WO PCT/JP2003/016802 patent/WO2004059268A1/ja active Application Filing
-
2009
- 2009-03-12 US US12/382,290 patent/US20090184237A1/en not_active Abandoned
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63204131A (ja) * | 1987-02-19 | 1988-08-23 | Olympus Optical Co Ltd | 光電変換素子アレイの蓄積時間制御装置 |
JPS63205527A (ja) * | 1987-02-20 | 1988-08-25 | Sanyo Electric Co Ltd | 測光回路 |
JPH10142051A (ja) * | 1996-11-13 | 1998-05-29 | Nec Corp | 撮像装置 |
EP1154483A1 (en) | 1998-07-08 | 2001-11-14 | Hamamatsu Photonics K.K. | Solid-state imaging device |
JP2000310561A (ja) | 1999-04-27 | 2000-11-07 | Hamamatsu Photonics Kk | 光検出装置 |
JP2001054020A (ja) * | 1999-08-10 | 2001-02-23 | Minolta Co Ltd | 固体撮像装置 |
JP2001141562A (ja) * | 1999-11-15 | 2001-05-25 | Hamamatsu Photonics Kk | 光検出装置 |
JP2001291877A (ja) * | 2000-04-05 | 2001-10-19 | Hamamatsu Photonics Kk | 固体撮像装置 |
WO2002012845A1 (fr) | 2000-08-03 | 2002-02-14 | Hamamatsu Photonics K.K. | Detecteur optique |
Non-Patent Citations (1)
Title |
---|
See also references of EP1577652A4 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8912499B2 (en) | 2010-03-16 | 2014-12-16 | Kabushiki Kaisha Toshiba | Radioactive ray detecting apparatus, method of manufacturing the same, and imaging system |
Also Published As
Publication number | Publication date |
---|---|
EP1577652B1 (en) | 2011-02-16 |
JP2004205359A (ja) | 2004-07-22 |
US20060197083A1 (en) | 2006-09-07 |
CN100501355C (zh) | 2009-06-17 |
US20090184237A1 (en) | 2009-07-23 |
AU2003296124A1 (en) | 2004-07-22 |
CN1732377A (zh) | 2006-02-08 |
JP4663956B2 (ja) | 2011-04-06 |
EP1577652A4 (en) | 2009-11-18 |
US7642496B2 (en) | 2010-01-05 |
DE60336077D1 (de) | 2011-03-31 |
EP1577652A1 (en) | 2005-09-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10257452B2 (en) | Solid-state image pickup apparatus, signal processing method for a solid-state image pickup apparatus, and electronic apparatus | |
US20090184237A1 (en) | Photodetector | |
US8097904B2 (en) | Method and apparatus for backside illuminated image sensors using capacitively coupled readout integrated circuits | |
US10812729B2 (en) | Solid-state imaging device | |
JP6796777B2 (ja) | 固体撮像素子、及び撮像装置 | |
KR100801181B1 (ko) | 디지털 이미지 센서 및 그 설계 방법 | |
KR20060130547A (ko) | 수광부 및 고체 촬상 장치 | |
US7800667B2 (en) | Photo-detecting apparatus | |
WO2004059748A1 (ja) | 光検出装置 | |
WO2006022163A1 (ja) | 光検出装置 | |
KR100962470B1 (ko) | 고체 촬상 소자의 픽셀 회로 | |
US20200059612A1 (en) | Pixel apparatus and cmos image sensor using the same | |
CN108848327A (zh) | 硅基混成cmos-apd图像传感器系统 | |
JP2021150742A (ja) | イメージセンサ | |
Karasik et al. | Large CMOS imager using Hadamard transform based multiplexing |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A1 Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW |
|
AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): BW GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
WWE | Wipo information: entry into national phase |
Ref document number: 2003786322 Country of ref document: EP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 20038A77797 Country of ref document: CN |
|
WWP | Wipo information: published in national office |
Ref document number: 2003786322 Country of ref document: EP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 10540476 Country of ref document: US |
|
WWP | Wipo information: published in national office |
Ref document number: 10540476 Country of ref document: US |