Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D48/00—Individual devices not covered by groups H10D1/00 - H10D44/00
  • H10D48/30—Devices controlled by electric currents or voltages
  • H10D48/32—Devices controlled by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
  • H10D48/36—Unipolar devices
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
  • H10D30/65—Lateral DMOS [LDMOS] FETs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
  • H10D30/0281—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of lateral DMOS [LDMOS] FETs
  • H10D30/0285—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of lateral DMOS [LDMOS] FETs using formation of insulating sidewall spacers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
  • H10D62/393—Body regions of DMOS transistors or IGBTs 
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
  • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/60—Electrodes characterised by their materials
  • H10D64/62—Electrodes ohmically coupled to a semiconductor
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/60—Electrodes characterised by their materials
  • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
  • H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
  • H10D64/662—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures
  • H10D64/663—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates

Definitions

• This invention relates to semiconductor circuitry and, more particularly, to circuitry which integrates digital and power functions and methods for fabricating such devices.
• Performance demands require a growing array of peripheral functions, most commonly including display drivers, RF interfacing, and battery operation.
• peripheral functions most commonly including display drivers, RF interfacing, and battery operation.
• the portable designs must perform energy management and power conversion functions with increased efficiency.
• Power integrated circuitry such as used in portable power supplies typically incorporates high voltage transistors with low voltage circuitry to efficiently manage battery usage and energy conversion. Due to performance requirements of the power device (e.g., fast switching speed, low "on” resistance and low power consumption during switching operations) the power device of choice for many power integrated circuits is the Lateral Double Diffused MOS transistor (LDMOS). When compared to bipolar transistor devices the LDMOS can provide relatively low on-resistance and high breakdown voltage. However, with the drive to further reduce device sizes and improve operational efficiencies, there remain limited means for sustaining or improving these device characteristics.
• LDMOS Lateral Double Diffused MOS transistor
• a semiconductor device includes a semiconductor layer with a pair of spaced-apart field effect gate structures on a surface of the semiconductor layer.
• Each gate structure includes a first end portion facing the other gate structure.
• First and second spaced-apart source regions of a first conductivity type are formed in a portion of the layer between the pair of gate structures. The portion of the surface between the first end portions is characterized by a first area dimension.
• Each source region is self-aligned with respect- to one of the first end portions.
• a lightly doped body region of a second conductivity type is formed in the semiconductor layer and extends from below the source regions to below the gate structures.
• a more heavily doped region of the second conductivity type extends into the portion of the surface between the first end portions, the region having an area dimension along the surface less than the first area dimension.
• a semiconductor integrated circuit including an LDMOS device structure comprising a semiconductor layer with a pair of spaced-apart field effect gate structures over an upper surface of the semiconductor layer.
• First and second spaced-apart source regions of a first conductivity type are formed in a portion of the layer between the pair of gate structures with a first region of a second conductivity type formed there between.
• a lightly doped body region of a second conductivity type is formed in the semiconductor layer, extending from below the source regions to below the gate structures and extending a variable depth into the semiconductor layer. This body region is characterized by an inflection in depth in that portion of the body region extending below the first region.
• a method of forming a semiconductor device includes forming with a first mask level a pair of spaced-apart field effect gate structures on a surface of a semiconductor layer. Each gate structure includes a first end portion facing the other gate structure. With a second mask level first and second spaced-apart source regions of a first conductivity type are formed in the layer and between the pair of gate structures with a resulting region of the surface between the first and second spaced-apart source regions having a first area dimension. A lightly doped body region of a second conductivity type, also defined with the second mask level, is formed in the semiconductor layer, extending below the source regions. A more heavily doped region of the second conductivity type is formed in a portion of the semiconductor layer having a surface with the first area dimension. The portion corresponding to the more heavily doped region has a surface with an area dimension smaller than the first area dimension.
• Figure 1 is a partial view of a prior art semiconductor device
• Figure 1A is a further view of the contacts made to a prior art device
• Figures 2A through 2E provide partial views, in cross section, of a semiconductor device in various stages of fabrication according to the invention.
• a width or lateral dimension is intended to mean a distance along a horizontal dimension of the view, while a height or depth is intended to mean a distance taken along a vertical dimension of the view.
• a feature size i.e., line width geometry, of 0.35 micron.
• references to a dopant implantation or resulting diffusion there from as being self-aligned with respect to a feature or an associated structure means that the implantation or diffusion is one resulting from using that structure as a mask element such that, for example, implanted dopant, both before and after heat-activated diffusion, will exhibit a characteristic profile in relation to the structure or an associated feature.
• implanted dopants associated with the invention undergo various heat-activated diffusions during the fabrication process in order to acquire predictable post-diffusion profile characteristics. It is also to be understood that when a layer is been described or illustrated as positioned on or over another layer, there may be another intervening layer (not illustrated) associated with the same or an alternate embodiment of the invention.
• a conventional prior art lateral device design shown in Figure 1, is formed in an N- upper layer of semiconductor material.
• the figure illustrates a pair of spaced- apart gate electrodes 2 each formed over a thermal oxide layer 4 and on the surface of the N- layer. Spacing between the gate electrodes is more than three microns.
• a P- type body 6 is formed by implantation through the surface of the N- layer and between the gate electrodes. Insulating sidewall spacer elements are formed on each side of each gate electrode 2.
• a pair of drain-side spacers 7 is illustrated.
• a pair of source spacers (not illustrated) is formed on facing sides of the different gate electrode 2 such that high dopant concentration source regions 8 are implanted in an offset relation to the gate electrodes 2.
• N+ drains 10 are defined in spaced-apart relation to the gate electrodes 2 and through patterned photoresist openings.
• the source spacers are typically removed (as illustrated) and a lower concentration N-type implant establishes lightly doped source extension regions 14 in self-alignment with the gate electrodes 2.
• the N-type implant lowers the resistivity in a portion of each drift region, i.e., in the volume of the N-upper layer between each gate electrode 2 and an associated drain 10. This modification in material resistivity contributes to establishment of a greater uniformity in electric field across the drift region (i.e., the current path from gate to drain).
• the regions implanted into the device of Figure 1 are later contacted by three separate contacts as shown in Figure 1 A.
• the N+ source region is outside the limits of the sidewall spacers.
• the prior art device uses three separate contacts. Each contact area has a minimum dimension that is limited by the process parameters. The contact area for each contact has to be wide enough to provide for insulating material, such as silicon dioxide, that will isolate one contact form another. As such, the prior art device has at least three minimum contact areas between opposite sidewall spacers of its gates. The relatively large source contact areas add to the leakage and the p-body resistance underneath the N+ source area of the device.
• the invention overcomes the disadvantages of the prior art by reducing the number of contact areas for the sources and body tie from three to one. This reduces the spacing between gate structures, reduces the size of the source regions and thereby reduces leakage and p-body resistance underneath. As a result, devices that use the invention have a larger safe operating area.
• Fabrication of an LDMOS pair 20 is shown in the partial cross sectional views of an integrated circuit structure 25 shown in Figures 2A - 2F.
• the example sequentially illustrates relevant steps in an N-channel LDMOS based on a 0.35 micron line width geometry, beginning with a P- type semiconductor layer 30 having an upper surface 32 with a plurality of N-wells 34 formed in the upper surface.
• This illustration contemplates a CMOS integrated circuit having both N-channel and P-channel LDMOS devices formed along the surface 32, but for purposes of illustration only, fabrication of the pair of N-channel devices 20 is described in detail. Accordingly, it will be understood that while N-channel devices 20 are formed in N-wells, the complimentary P-channel devices are formed in the P-type region of the layer 30.
• the layer 30 may be epitaxially grown on an underlying substrate (not illustrated).
• each electrode 38 includes an end portion 40a which faces the other electrode 38, and each electrode further includes an end portion 40b which faces away from the other electrode 38. See Figure 2B.
• a preferred width between the end portions 40a is about one micron.
• An implant mask level of photoresist 44 is deposited and patterned over the surface 32 of the layer 30, with an element 48 spaced between the end portions 40a of the illustrated electrodes 38 to create two spaced-apart openings 52, each approximately 0.3 micron in width, suitable for receiving source implants.
• the resist element 48 preferably having a width on the order of 0.4 micron, is intended to isolate a sufficient region 50 of the surface 32 between the openings 52 from receiving implantation in order to assure separation of doped regions after lateral diffusion.
• a hetero-doping implant is performed to provide a shallow N-type source dopant along the surface 32 and a deeper P-type dopant within the N-well to form a body region.
• the photoresist 44 is then removed. See Figure 2B, which illustrates formation of sources 56 and body region 58 after diffusion.
• the source implant is on the order of 3xl0 15 cm “2 (Arsenic) at 30 KeV while the body region implant is on the order of 5xl0 13 cm “2 to lxl0 14 cm “2 (Boron) at 60 KeV.
• Conventional N-type drains 60 formed with separate photomask and implant steps, are also illustrated. The drains 60 may be formed in conjunction with formation of other CMOS devices along other portions of the surface 32.
• sidewall spacer elements 64 are formed on the gate end portions 40a and may, as illustrated in Figure 2C, also be formed on the gate end portions 40b.
• the spacer elements 64 may be formed by deposit of insulating material, such as a silicon oxide or silicon nitride, followed by an anisotropic etch.
• this arrangement allows a lateral offset of the source implants with respect to the body tie implant such that the resulting sources 56 are offset with respect to the body tie 70.
• each source is in self-alignment with an adjacent gate end portion 40a while the body tie is in self-alignment with each adjacent spacer element 64.
• the implant 68 is used to simultaneously form CMOS P+ source/drain diffusions for digital circuitry on the integrated circuit structure 25.
• the fully formed body tie 70 reaches into the semiconductor layer 30, i.e., into the well 34 and body 58, below the source regions 56.
• a feature of this structure is that a significant portion of each source 56 positioned beneath an overlying spacer element 64 retains a relatively heavy net dopant concentration while the nested body tie is also of low resistivity and small lateral dimension.
• metal such as tungsten, titanium or cobalt is deposited and reacted to form gate silicide 74 and source/body tie suicide 76.
• Figure 2E illustrates the structure 25 after the silicidation process.
• a feature of the invention is the heterodoping implant of Figures 2A and 2B which provides the source regions 56 and the body region 58 with one mask level, thus reducing the number of masks required to form an LDMOS having improved performance characteristics.
• the heterodoping feature results in the combination of spaced-apart source regions 56 about the region 50 and an inflection 76 in the depth of the portion of the body region under the region 50, both of these features being attributable to the presence of the mask element 48 during the heterodoping process.
• the depth of the body region into the semiconductor layer is relatively deep under the gate electrodes compared to the depth under the first region.
• Another feature of the invention is the provision of source regions characterized by a relatively constant lateral dopant profile between the heavily doped region of the second conductivity type and the portion of the semiconductor layer underlying an adjacent gate structure, e.g., an electrode 38. That is, the source regions may be formed with a single dopant implant of the net conductivity type, whereas in the past the source structures have required a combination of heavily doped regions (e.g., regions 8 of Figure 1) and more lightly doped regions (e.g., extension regions 14 of Figure 1) to effect lower device on-resistance.
• the low specific on-resistance of devices constructed according to the invention results from the reduced device unit size, e.g., achievable with self-aligned formations such as illustrated in the figures.
• An improved safe operating area of operation results from reduced body resistance, small source space area, a shallow source junction and the retrograde doping profile of the body region, e.g., region 58.
• spacer elements e.g., the spacers 64 adjacent the gate electrode end portions 40a and 40b, provide a fine line geometry mask to enable small source areas.
• the self-aligned salicidation (salicide) process enables low contact resistances due to no heavy dopant compensation in critical contact areas such as the body tie region and source regions.
• Both the body tie 70 and the associated salicide layer 76 are self-aligned with respect to the source regions 56.
• the invention recognizes that the N+ source implants do not have to be the same size and the drain implants.
• the invention uses the sidewall oxide spacers on the gates to mask the N+ source implants from the P+ tie implant. With the invention, the N+ source implants are made before the sidewall spacers.
• the process of the invention uses one masking step for implanting the N+ sources and the P- body.
• the invention eliminates the separate P- body masking step required by the prior art.
• the invention provides a single, silicide contact that is self-aligned to the two N+ sources, the P+ body tie, and the overlap of the N+ sources and P+ body tie. The number of contacts are reduced from three (prior art) to one.
• the single contact between the gates provides a denser device and the device has a wider safe operating area because its small sources have less leakage and p-body resistance underneath than the larger sources of prior art devices.

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• Insulated Gate Type Field-Effect Transistor (AREA)
• Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

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• 2002
  • 2002-12-10 US US10/315,517 patent/US6870218B2/en not_active Expired - Fee Related
• 2003
  • 2003-12-09 AU AU2003296321A patent/AU2003296321A1/en not_active Abandoned
  • 2003-12-09 CN CNB2003801057172A patent/CN100524812C/zh not_active Expired - Fee Related
  • 2003-12-09 KR KR1020057010197A patent/KR101030178B1/ko not_active Expired - Fee Related
  • 2003-12-09 JP JP2004559410A patent/JP2006510206A/ja active Pending
  • 2003-12-09 TW TW092134753A patent/TWI355074B/zh not_active IP Right Cessation
  • 2003-12-09 DE DE10393858T patent/DE10393858T5/de not_active Withdrawn
  • 2003-12-09 WO PCT/US2003/038931 patent/WO2004053939A2/en not_active Ceased
• 2005
  • 2005-03-01 US US11/069,900 patent/US7220646B2/en not_active Expired - Lifetime
• 2007
  • 2007-02-16 US US11/675,759 patent/US7608512B2/en not_active Expired - Fee Related

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