WO2004040326A1 - 半導体集積回路の不良解析装置、システムおよび検出方法 - Google Patents
半導体集積回路の不良解析装置、システムおよび検出方法 Download PDFInfo
- Publication number
- WO2004040326A1 WO2004040326A1 PCT/JP2003/013869 JP0313869W WO2004040326A1 WO 2004040326 A1 WO2004040326 A1 WO 2004040326A1 JP 0313869 W JP0313869 W JP 0313869W WO 2004040326 A1 WO2004040326 A1 WO 2004040326A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- semiconductor integrated
- integrated circuit
- failure
- probe
- failure analysis
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/302—Contactless testing
- G01R31/308—Contactless testing using non-ionising electromagnetic radiation, e.g. optical radiation
- G01R31/311—Contactless testing using non-ionising electromagnetic radiation, e.g. optical radiation of integrated circuits
Definitions
- the present invention relates to a semiconductor failure analysis device, a system, and a semiconductor failure analysis method for supporting a semiconductor failure analysis.
- the present invention also relates to a method for manufacturing a semiconductor device.
- LSI semiconductor integrated circuit
- an EB tester is used to irradiate an electron beam to an arbitrary disconnected wiring portion to change the potential of a defective portion between an intermediate potential and a low potential or between an intermediate potential and a high potential, thereby causing a disconnection.
- a failure location is specified by obtaining a potential image in which only the circuit connected to the wiring portion or the disconnected wiring portion changes (see Japanese Patent Application Laid-Open No. 10-10208).
- a magnetic field generation head is used instead of electron beam irradiation, a magnetic field is locally applied to the sample, a potential change is generated by the generated electromotive force, and this is acquired as a potential image. Then, the presence or absence of a defect is detected (see JP-A-2001-14776).
- the EB tester used in Japanese Patent Application Laid-Open No. 10-10208 requires a device to maintain a vacuum state because an electron beam is used to supply a potential change to the disconnected wiring and to acquire a potential image, The whole device is very large.
- an EB tester is a general term for an electron beam tester analyzer that irradiates an electron beam onto an observation point and measures the amount of secondary electrons generated to obtain a potential image of the observation point.
- the size of the area requires several square meters. Therefore, there is a problem that failure analysis of a semiconductor device or a wiring board cannot be performed in a small space. Another problem is that the EB tester itself is very expensive.
- the electron beam irradiation should be performed with high precision so that such a problem does not occur, that is, irreversible charge-up does not occur, and a clear displacement (flashing) potential image can be obtained with high accuracy in the disconnected wiring portion. It is very difficult to control each time.
- an electron beam is radiated to a gate circuit inverter portion connected to the defective wiring portion such as a disconnection and the gate circuit inverter is illuminated. If a potential image displaced at the portion is obtained, a clearer potential image can be obtained.
- very precise control of the electron beam irradiation is required. It is required, but it is very difficult to achieve.
- An object of the present invention is to provide a semiconductor or wiring failure analysis apparatus capable of accurately specifying a defective portion and having a reduced size. Further, with respect to a method for manufacturing a semiconductor device or a wiring board, the object is to improve the manufacturing efficiency and the yield.
- a defect in a semiconductor integrated circuit characterized by detecting the presence or absence of a defect by irradiating an electromagnetic field with a probe and detecting a power supply current fluctuation or an electric characteristic fluctuation in the semiconductor integrated circuit.
- a defect analysis device for a semiconductor integrated circuit characterized by detecting the presence or absence of a defect.
- a failure analysis device for a semiconductor integrated circuit which measures heat generation and emission radiation generated by a power supply current fluctuation in the semiconductor integrated circuit, and detects the presence or absence of a defective portion.
- a process of designing a wiring pattern of the semiconductor device a manufacturing process of manufacturing the semiconductor device based on the design information; a testing process of testing the manufactured or in the middle of the manufacturing process;
- a failure analysis is performed to generate and detect a current fluctuation and identify a defective portion. If the analysis result clears a predetermined condition, the semiconductor device is manufactured.If the predetermined condition cannot be cleared, the analysis result is obtained.
- Semiconductors characterized by improving the performance of semiconductor devices or improving manufacturing efficiency by identifying the cause of failure based on the information and providing feedback to the manufacturing process.
- Device is a method of manufacturing.
- FIG. 1 is a schematic diagram of a failure analysis device.
- FIG. 2 is a schematic diagram of a disconnection failure of the inverter circuit.
- FIG. 3 is a schematic diagram of a failure analysis device.
- 4A and 4B are diagrams showing waveforms in the present embodiment.
- FIG. 5 is a schematic diagram of a failure analysis device.
- FIG. 6 is a schematic diagram of a failure analysis device.
- 7A and 7B are schematic diagrams of electric or magnetic field excitation by the substrate side.
- FIG. 8 is a schematic diagram of the linkage with the CAD navigation system.
- 9A and 9B are schematic diagrams of the failure analysis screen.
- FIG. 10 is a diagram showing the power supply current fluctuation characteristics of the inverter circuit.
- FIG 11 is a process construction flowchart.
- FIG. 12 is a schematic diagram of a semiconductor manufacturing process flow 1.
- FIG. 13 is a schematic diagram of a semiconductor manufacturing process flow 2.
- FIG. 1 shows a failure analysis device for a semiconductor integrated circuit according to a first embodiment which is an example of the present invention.
- the failure analyzer according to the present embodiment includes a probe 101, an LSI 102, a signal generator 103, a fluctuation detection unit 104, a pattern generation unit 105 for setting an LSI to a desired state, and a probe control unit 106.
- the semiconductor failure analysis apparatus includes: (a) changing the intermediate potential of the open gate by irradiating an electric field or a magnetic field generated from the probe 101; A current 203 is generated, (c) the power supply current of the circuit is varied, and (d) the fluctuation of the power supply current is measured by the fluctuation detection unit 104 to determine the presence or absence of a defect.
- the probe 101 is excited by the power supplied from the signal generator 103, and an electric field or a magnetic field is generated from the probe 101.
- This electric or magnetic field A desired position is locally irradiated, and an electromotive force corresponding to the electric or magnetic field strength is generated in the wiring on the LSI.
- This probe can irradiate an electric or magnetic field arbitrarily from a small area of about 0.1 / ⁇ 1 to a wide area of several tens of ⁇ . Considering that the minimum wiring width is about 0.1 to 0.3 ⁇ , this probe can irradiate an electric field or a magnetic field to a desired position of the wiring, for example, a specific circuit element.
- the Goutt potential of the connected jumper circuit or the like is driven to an arbitrary logic state. Therefore, even if a normal wiring portion is irradiated with an electric field or a magnetic field, the potential of the wiring portion hardly changes.
- the gate potential of the door 0S202 connected to the disconnection wiring is not driven to a predetermined logic state, and the gate potential between the low level and the high level is low.
- an intermediate potential this is called an open gate.
- the open circuit portion is activated by a change in potential, the image OS and PM0S are both turned on to generate a through current, and the power supply current of a normal circuit changes.
- the change in the power supply current due to the through current of the gate circuit alone varies depending on the activation level, but is about 1/10000 to 1/10 of the magnitude of the power supply current. To detect.
- FIG. 10 shows a simulation result of the power supply current fluctuation characteristics in the inverter circuit shown in FIG.
- the power supply current fluctuation occurs in proportion to the open-gut intermediate potential fluctuation. Therefore, it is desirable to apply a large potential change to the disconnection defective portion in order to easily identify the disconnection defective portion.
- the probe 101 in order to apply a large potential change to the disconnection defective portion, it is necessary to apply a larger electric field strength or magnetic field strength to the wiring on the LSI 102, and the probe 101 must be It is preferable to drive with a higher frequency excitation wave.
- a higher frequency excitation wave By exciting to high frequency, high density and energy can be supplied to the probe 101, a large electric and / or magnetic field intensity can be supplied to the irradiated part by the probe 101, and a large electric potential change is given to a broken wire defective part. Because you can do it.
- the failure analysis method when an electric field or a magnetic field is generated using a current (excitation wave) having a frequency in the range of several tens of kHz to several hundreds of MHz, Failure analysis can be performed on a semiconductor device having a high operating frequency.
- the electric field or the magnetic field generated from the probe is used instead of the electron beam to change the potential of the defective wiring portion (to activate), which is irreversible. It is possible to obtain a clear and accurate displacement potential of the disconnection wiring portion without causing a significant charge-up.
- the size of the failure analysis device (failure analysis system) can be reduced.
- the power supply system inside the LSI 102 and the test board on which the LSI is mounted are provided with a bypass capacitor.
- the power supply current fluctuation caused by the activation of the gate circuit also becomes high frequency, so that the fluctuation is suppressed by the above-mentioned bypass capacitor, and it becomes difficult for the fluctuation detection unit 104 to detect the fluctuation.
- the failure analysis apparatus according to the present embodiment improves the above problem.
- the failure analyzer modulates an excitation wave for supplying electric power to the electric or magnetic field probe 101, the fluctuation detecting unit 104, the pattern generating unit 105 for setting the LSI to a desired state, the probe control unit 106, and the probe 101.
- the signal generator 301 generates two signals having different frequencies, for example, an excitation wave having a high frequency and a modulated wave having a lower frequency than the excitation wave. Then, a modulated excitation wave is generated by switching the excitation wave shown in FIGS. 4A and 4B with the modulated wave.
- the high frequency is in the range of several tens of MHz to GHz
- the low frequency is in the range of several hundred Hz to several tens of kHz.
- FIG. 4A shows the state of the excitation wave, the modulation wave, and the power supply current fluctuation of the first embodiment
- the excitation wave is modulated, it is possible to suppress a reduction in the power supply current fluctuation level due to the bypass capacitor. That is, the influence of the bypass capacitor existing inside the LSI can be reduced, and the disconnection failure analysis of the LSI including the bypass capacitor can be accurately performed.
- the power supply current fluctuation level can be easily detected.
- the modulation in the embodiment of the present invention is not limited to the above-described modulation method, and can be variously changed without departing from the gist thereof, such as AM modulation.
- FIG. 5 shows a schematic diagram of a failure analysis device as a third embodiment.
- the failure analyzer includes a probe 101, an LSI 102, a signal generator 103, a pattern generator 105 for setting an LSI to a desired state, a probe controller 106, heat generation, an emission analyzer 501, and a detector 502. Have.
- the electric potential of the open gate is varied by irradiating the probe 101 with an electric or magnetic field, thereby activating the gate circuit and varying the power supply current.
- heat generation and emission radiation generated in the gate circuit and its peripheral portion when the open gate or the gate potential is activated. The presence or absence of a defective part is detected by capturing the physical phenomena of the above.
- FIG. 6 shows a schematic diagram of a disconnection failure analysis device as a fourth embodiment of the present invention.
- the failure analyzer includes a probe 101, an LSI 102, a signal generator 103, a pattern generator 105 for setting an LSI to a desired state, a probe controller 106, a detection probe 601 and a detector 602.
- the electric potential of the open gate fluctuates due to the electric field or magnetic field excitation by the probe unit 101, and the gate circuit is activated.
- the power supply current fluctuates due to the activation of the gate circuit, causing a change in the electric field or magnetic field near the gate circuit.
- the vicinity electric field or magnetic field is measured by the detection probe 601 and the detector 602 to detect the presence or absence of a defective portion.
- the arithmetic processing unit 603 is provided, and the current distribution can be calculated and displayed on the display unit 604 by arithmetically processing the measured electric or magnetic field distribution. From this current distribution, the power supply current fluctuation due to the activation of the gate circuit or the Goutt potential can be detected, and the presence or absence of a defective portion can be detected.
- the electric field and magnetic field distribution of the non-defective LSI 102 is measured or the current distribution is calculated in advance, and the presence or absence of a defect can be detected from the difference information between the non-defective and defective products.
- the extraction of the difference information is performed by the arithmetic processing unit 603 and displayed on the display unit 604.
- FIGS. 7A and 7B show schematic diagrams of electric or magnetic field excitation from the substrate side of the LSI 102.
- FIG. 7A and 7B show schematic diagrams of electric or magnetic field excitation from the substrate side of the LSI 102.
- an insulating film 703 provided in an upper wiring layer, a metal wiring 702, a protective film 704 such as a PIQ, etc. Becomes a shielding region, and it becomes difficult to activate the relay gate 707 or the gate potential as the wiring becomes lower.
- an electric or magnetic field irradiation and excitation are performed on a defective portion from the substrate side (lower layer side) to the lower layer wiring of the multilayer wiring board.
- the substrate 706 on the substrate side of the LSI may be polished.
- an electric field or a magnetic field may be irradiated from both the upper layer and the lower layer of the multilayer wiring board to specify the defective portion with higher accuracy.
- LSI failure can be detected as power supply current fluctuation, light emission, heat radiation, and electric or magnetic field or current distribution. Also perform local excitation For this reason, it is possible to specify a defective area as a primary extraction within a certain area, and the area can be reduced by performing multiple analyzes, such as changing excitation conditions and changing the excitation area. is there.
- FIG. 8 is a schematic diagram of an embodiment of the failure analysis using the CAD navigation system 815.
- the probe coordinate data 801 extracted from the probe control unit 106 passes through a coordinate / region information generation unit 813, a coordinate / region information data conversion unit 812, and a user layer database 811 that can be handled as the same index as the LSI design layout data. Output and accumulated.
- the probe coordinate data 801 can generate an area area arbitrarily set by the user as an analysis area by designating the coordinates and the barycentric coordinate in the area information generation unit 813.
- the coordinate / region information data conversion unit 812 can convert this region into polygon data, convert it into the user layer layout data 907 shown in FIG. 9, and store it in the user layer database 811.
- the user layer database 811 can input various data from an external device in an arbitrary file format 814. Examples of input include net cell information of the DUT obtained from various analyzers such as an electron beam tester and IDDQ analyzer, information on layout patterns with severe process margins, and weighting conditions for analysis obtained from past failure analysis. The input data varies widely.
- the layout data 802, the layout-to-netlist correspondence information data 803, and the netlist data 804 are input to the system.
- Each data is a data
- the data is stored in a rate database 806, a rate-to-netlist correspondence information database 807, and a netlist database 808 through a data converter 805.
- the databases are linked to each other, and the design layout and netlist information corresponding to the probe coordinate data must be output and displayed in the layout display section 809 and the netlist display section 810 while maintaining mutual correspondence. Can be done.
- FIGA and 9B are schematic diagrams of an analysis screen 901 in the CAD navigation system 815 of the present embodiment.
- the probe coordinates 902 input to the user layer 903 and the design layout information for each LSI wiring layer corresponding to the coordinates are output and displayed in the design layer 904.
- a net 905 and a cell 906 that match or approach the probe coordinates 902 can be displayed and extracted for each distribution layer.
- the layout data 907 created using the probe coordinates 902 as the barycenter coordinates can be similarly displayed, and the user can set conditions on the screen and arbitrarily enlarge or reduce the area.
- the analysis screen 901 can handle a plurality of both probe coordinates 902 and layout data 907, and the analyst can visually distinguish by designating or changing the display color.
- the use of the CAD navigation system enables accurate identification at the wiring level in a short time in the failure analysis of semiconductor integrated circuits.
- analysis between multiple analyzers such as light emission analysis and 0BIRCH analysis, it is possible to narrow down suspected failure candidates, increase the efficiency of identification work, and shorten the analysis time.
- the process construction flowchart will be described with reference to FIG.
- the TEG manufacturing process is set and the Si wafer is input to the manufacturing line for manufacturing (STEP2).
- a wafer appearance inspection such as inspection of foreign matter after film formation, appearance inspection after etching and CMP, and SEM review after inspection
- An electrical test is performed using a tester or a properr to determine the quality of the TEG (STEP4).
- failure analysis is performed based on the results of the electrical inspection electrical test and the failure location is specified (STEP5).
- SEM and TEM are used to observe the surface and cross section and analyze the material (STEP 6), estimate the failure mechanism, and formulate a countermeasure (STEP 7).
- Figure 12 shows a schematic diagram of the manufacturing process flow for semiconductor products. Failure analysis is an indispensable flow for process construction and changing design conditions in the design stage, and for improving yield and implementing countermeasures for defects in the mass production stage.
- the effects produced by the embodiment of the present invention are not limited to the simplification of the failure analysis apparatus and the simplification of the analysis work, but are very wide-ranging, such as a semiconductor manufacturing process, a semiconductor manufacturing method, and a manufacturing process. It is.
- the mass production process includes a process of forming circuit elements on a wafer, a process of detecting wafer-like semiconductor devices, a process of dicing a wafer, and a process of forming leads and bumps on a semiconductor chip.
- FIG. 13 shows a manufacturing flowchart of the semiconductor device.
- the product wafer manufactured in the step S1 is subjected to initial defect selection by a P inspection (Pe11et inspection) in a step S2.
- the selected non-defective wafer proceeds to step S3 or S5.
- the selection of whether to proceed to step S3 or to step S5 is selected based on the relationship between the manufacturing equipment and the like.
- step S3 the product wafer is diced, and only non-defective chips are individually packaged in step S4, such as CSP (Chip Size Package) or BGA (Ball Grid Array). . Then, the process proceeds to step S7.
- CSP Chip Size Package
- BGA Ball Grid Array
- step S5 a wiring pattern and a protective film are further collectively formed on the wafer, and further, soldering is performed. Subsequently, in step S6, The wafer on which the wiring patterns and the like are formed is individually divided by dicing. Then, the process proceeds to step S7.
- step S7 a semiconductor device detection method using the semiconductor element detection socket is performed.
- the products of the final shape divided individually are subjected to the burn-in test by the IC inspection socket and are finally sorted.
- the finally good product is shipped in step S8.
- a wafer-level chip size package has emerged in which semiconductor elements are detected, re-wired, and external connection terminals are formed at a wafer level, and then a wafer is diced to form a semiconductor device.
- the manufacturing of the semiconductor device described above is performed based on design, which is the first step of the semiconductor manufacturing process. Therefore, performing unnecessary analysis based on the information obtained in the evaluation / inspection process, grasping the cause of the failure, and taking appropriate measures such as changing the manufacturing process in the design process are difficult in the subsequent mass production process. Very important. In other words, the failure analysis has an effect on all devices, such as improving the yield in the mass production stage.
- a failure analysis device for a semiconductor integrated circuit wherein a failure is detected by irradiating an electromagnetic field from a probe and detecting a power supply current fluctuation to detect the presence or absence of a failure.
- a failure analysis system for a semiconductor integrated circuit which irradiates an electromagnetic field from a probe and detects a voltage variation, an impedance variation, or an electrical characteristic variation to detect the presence or absence of a failure. Failure analysis device.
- the failure analysis device for a semiconductor integrated circuit according to the above (1) or (2) by activating open gut or gut potential, the power supply current fluctuation, the voltage fluctuation, or the impedance fluctuation can be reduced.
- a defect analysis device for a semiconductor integrated circuit characterized by detecting.
- the probe is excited and modulated, and the synchronization is performed with a signal applied to the probe.
- a failure analysis device for a semiconductor integrated circuit which detects a power supply current variation, the voltage variation, or the impedance variation.
- failure analysis device for a semiconductor integrated circuit according to any one of (1) to (4) above, wherein the heat generation and emission radiation caused by the power supply current fluctuation, the voltage fluctuation, or the impedance fluctuation are measured.
- a failure analysis device for a semiconductor integrated circuit which is characterized by detecting a failure by using the method.
- a failure analysis system for a semiconductor integrated circuit characterized by detecting electrical characteristic fluctuations in the semiconductor integrated circuit by activating an open gate or a gate potential. apparatus.
- the probe is excited and modulated, and the electrical characteristic fluctuation is detected while synchronizing with a signal applied to the probe.
- a failure analysis device for a semiconductor integrated circuit In the failure analysis device for a semiconductor integrated circuit according to the above (8), the probe is excited and modulated, and the electrical characteristic fluctuation is detected while synchronizing with a signal applied to the probe.
- the probe may be configured to irradiate an electromagnetic field from the probe or activate the open gate or the gate potential.
- the defect information is obtained by cross-referencing the position information of the probe and the design information of the chip.
- a failure analysis device for a semiconductor integrated circuit, wherein the failure is determined.
- (14) a process of designing a wiring pattern of a semiconductor device, a manufacturing process of manufacturing a semiconductor device based on the design information, a testing process of testing the manufactured or in the middle of the manufacturing process, An analysis method for analyzing or evaluating a test result.
- an electromagnetic field is radiated from the probe to the wiring of the semiconductor device, and a power supply current fluctuation is detected to detect a defective portion. If the defective result clears a predetermined condition, the semiconductor device is evaluated.
- a method of manufacturing a semiconductor device comprising: performing a production, and, if a predetermined condition cannot be cleared, identifying a cause of a defect based on the analysis result and feeding the result to a manufacturing process.
- a power supply current fluctuation can be generated and detected by activating an open gate or a gate potential, and the presence or absence of a defective portion can be detected.
- probe position information and chip design information can be cross-referenced by linkage with the CAD napige system, enabling accurate identification of fault locations and shortening of analysis time, and prompt failure. Take preventive measures. This effect shortens the process construction period and has a very significant effect on the early launch of the process line.
- the present invention it is possible to provide a miniaturized semiconductor or wiring defect analysis apparatus capable of accurately specifying a defective portion and having a reduced size.
Abstract
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/533,127 US20060164115A1 (en) | 2002-10-29 | 2003-10-29 | Defect analyzing device for semiconductor integrated circuits, system therefor, and detection method |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002313618A JP2004150840A (ja) | 2002-10-29 | 2002-10-29 | 半導体集積回路の不良解析装置、システムおよび検出方法 |
JP2002-313618 | 2002-10-29 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2004040326A1 true WO2004040326A1 (ja) | 2004-05-13 |
Family
ID=32211588
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2003/013869 WO2004040326A1 (ja) | 2002-10-29 | 2003-10-29 | 半導体集積回路の不良解析装置、システムおよび検出方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US20060164115A1 (ja) |
JP (1) | JP2004150840A (ja) |
WO (1) | WO2004040326A1 (ja) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006003135A (ja) * | 2004-06-16 | 2006-01-05 | Hitachi Ltd | 半導体集積回路の不良診断方法 |
WO2006095791A1 (en) | 2005-03-07 | 2006-09-14 | Semiconductor Energy Laboratory Co., Ltd. | Element substrate, inspecting method, and manufacturing method of semiconductor device |
JP4989158B2 (ja) * | 2005-09-07 | 2012-08-01 | 株式会社ニューフレアテクノロジー | 荷電粒子線描画データの作成方法及び荷電粒子線描画データの変換方法 |
US7860398B2 (en) | 2005-09-15 | 2010-12-28 | Finisar Corporation | Laser drivers for closed path optical cables |
US8083417B2 (en) * | 2006-04-10 | 2011-12-27 | Finisar Corporation | Active optical cable electrical adaptor |
US7719295B2 (en) * | 2007-01-31 | 2010-05-18 | International Business Machines Corporation | Method and apparatus for implementing IC device testing with improved SPQL, reliability and yield performance |
KR100807218B1 (ko) * | 2007-02-02 | 2008-02-28 | 삼성전자주식회사 | 웨이퍼 검사 장치 및 방법 |
US8769171B2 (en) * | 2007-04-06 | 2014-07-01 | Finisar Corporation | Electrical device with electrical interface that is compatible with integrated optical cable receptacle |
US8244124B2 (en) | 2007-04-30 | 2012-08-14 | Finisar Corporation | Eye safety mechanism for use in optical cable with electrical interfaces |
US8558567B2 (en) | 2010-05-14 | 2013-10-15 | International Business Machines Corporation | Identifying a signal on a printed circuit board under test |
US8901946B2 (en) | 2010-05-24 | 2014-12-02 | International Business Machines Corporation | Identifying a signal on a printed circuit board under test |
JP5780498B2 (ja) * | 2011-01-25 | 2015-09-16 | 独立行政法人国立高等専門学校機構 | Cmos論理icパッケージの検査方法および検査装置 |
CN102901471B (zh) * | 2011-07-26 | 2015-06-03 | 中国科学院物理研究所 | 纳米图形化和超宽频电磁特性测量系统 |
US9523729B2 (en) * | 2013-09-13 | 2016-12-20 | Infineon Technologies Ag | Apparatus and method for testing electric conductors |
US9268938B1 (en) | 2015-05-22 | 2016-02-23 | Power Fingerprinting Inc. | Systems, methods, and apparatuses for intrusion detection and analytics using power characteristics such as side-channel information collection |
US10859609B2 (en) | 2016-07-06 | 2020-12-08 | Power Fingerprinting Inc. | Methods and apparatuses for characteristic management with side-channel signature analysis |
US10890618B2 (en) * | 2017-02-21 | 2021-01-12 | The Government Of The United States, As Represented By The Secretary Of The Army | Terahertz plasmonics for testing very large-scale integrated circuits under bias |
CN117321429A (zh) * | 2021-05-21 | 2023-12-29 | 三菱电机株式会社 | Ic的噪声耐量检测装置、ic的噪声耐量检测方法及ic的内部阻抗测定方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01277781A (ja) * | 1988-04-30 | 1989-11-08 | Nippon Telegr & Teleph Corp <Ntt> | 集積回路試験装置 |
US5514971A (en) * | 1993-05-24 | 1996-05-07 | Nec Corporation | Method and apparatus for testing an immunity to electromagnetic interference and apparatus for irradiating radio wave for immunity test |
JPH0992701A (ja) * | 1995-09-28 | 1997-04-04 | Nippon Telegr & Teleph Corp <Ntt> | データベースを用いたlsiの故障解析支援装置 |
JP2001166012A (ja) * | 1999-12-14 | 2001-06-22 | Advantest Corp | 回路試験装置 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001272430A (ja) * | 2000-03-24 | 2001-10-05 | Oht Inc | 検査装置及び検査方法 |
US6729922B2 (en) * | 2000-06-05 | 2004-05-04 | Semiconductor Energy Laboratory Co., Ltd. | Device for inspecting element substrates and method of inspection using this device |
-
2002
- 2002-10-29 JP JP2002313618A patent/JP2004150840A/ja active Pending
-
2003
- 2003-10-29 US US10/533,127 patent/US20060164115A1/en not_active Abandoned
- 2003-10-29 WO PCT/JP2003/013869 patent/WO2004040326A1/ja active Application Filing
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01277781A (ja) * | 1988-04-30 | 1989-11-08 | Nippon Telegr & Teleph Corp <Ntt> | 集積回路試験装置 |
US5514971A (en) * | 1993-05-24 | 1996-05-07 | Nec Corporation | Method and apparatus for testing an immunity to electromagnetic interference and apparatus for irradiating radio wave for immunity test |
JPH0992701A (ja) * | 1995-09-28 | 1997-04-04 | Nippon Telegr & Teleph Corp <Ntt> | データベースを用いたlsiの故障解析支援装置 |
JP2001166012A (ja) * | 1999-12-14 | 2001-06-22 | Advantest Corp | 回路試験装置 |
Also Published As
Publication number | Publication date |
---|---|
US20060164115A1 (en) | 2006-07-27 |
JP2004150840A (ja) | 2004-05-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2004040326A1 (ja) | 半導体集積回路の不良解析装置、システムおよび検出方法 | |
US11669957B2 (en) | Semiconductor wafer measurement method and system | |
Satya | Microelectronic test structures for rapid automated contactless inline defect inspection | |
US9689923B2 (en) | Adaptive electrical testing of wafers | |
US20100021049A1 (en) | Method and apparatus for failure analysis of semiconductor integrated circuit devices | |
US7617427B2 (en) | Method and apparatus for detecting defects in integrated circuit die from stimulation of statistical outlier signatures | |
KR20240018407A (ko) | 반도체 신뢰성 불량의 z-pat 결함 유도 통계적 이상치 검출을 위한 시스템 및 방법 | |
US7715997B2 (en) | Intelligent inspection based on test chip probe failure maps | |
US6137295A (en) | Method of detecting defect of integrated circuit and apparatus thereof | |
Schmidt et al. | Localization of electrical active defects caused by reliability-related failure mechanism by the application of Lock-in Thermography | |
JP4131918B2 (ja) | 半導体集積回路の故障解析装置及び故障解析方法 | |
JP2003282665A (ja) | 半導体不良解析ツール、システム、不要解析方法および半導体装置の製造方法 | |
Coyette et al. | Latent defect screening with visually-enhanced dynamic part average testing | |
Erb et al. | Yield enhancement through fast statistical scan test analysis for digital logic | |
JP2008041757A (ja) | 半導体検査装置および半導体検査方法 | |
US6549868B2 (en) | Semiconductor device test system and test method | |
JP3287332B2 (ja) | 半導体集積回路の断線故障検出装置及びその断線故障検出方法 | |
US11899065B2 (en) | System and method to weight defects with co-located modeled faults | |
JP2008089359A (ja) | 半導体集積回路の故障解析方法および故障解析装置 | |
Matsui et al. | Fault localization of IDDQ failure using External trigger Synchronous LIT technique | |
JP2003057308A (ja) | 電子装置及び電子装置の良否の検査方法 | |
Haehn et al. | Failure Analysis of VLSI by I DDQ Testing | |
JP2001319955A (ja) | 発光解析方法およびその装置 | |
WO2023193890A1 (en) | Method and apparatus for testing a packaging substrate | |
JP2004233171A (ja) | 半導体装置の組立不良解析装置およびその不良解析方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A1 Designated state(s): CN KR US |
|
AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PT RO SE SI SK TR |
|
DFPE | Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101) | ||
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
ENP | Entry into the national phase |
Ref document number: 2006164115 Country of ref document: US Kind code of ref document: A1 |
|
WWE | Wipo information: entry into national phase |
Ref document number: 10533127 Country of ref document: US |
|
122 | Ep: pct application non-entry in european phase | ||
WWP | Wipo information: published in national office |
Ref document number: 10533127 Country of ref document: US |