WO2004030092A1 - Puces a semiconducteur dans laquelle des pistes conductrices sur un plan cristallin (1,0,0) forment un angle d'au moins 10 degres avec les plans cristallins (0,1,0) et (0,0,1), de façon a augmenter la resistance a la rupture - Google Patents

Puces a semiconducteur dans laquelle des pistes conductrices sur un plan cristallin (1,0,0) forment un angle d'au moins 10 degres avec les plans cristallins (0,1,0) et (0,0,1), de façon a augmenter la resistance a la rupture Download PDF

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Publication number
WO2004030092A1
WO2004030092A1 PCT/DE2003/003057 DE0303057W WO2004030092A1 WO 2004030092 A1 WO2004030092 A1 WO 2004030092A1 DE 0303057 W DE0303057 W DE 0303057W WO 2004030092 A1 WO2004030092 A1 WO 2004030092A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor
planes
semiconductor chip
crystal
conductor tracks
Prior art date
Application number
PCT/DE2003/003057
Other languages
German (de)
English (en)
Inventor
Holger HÜBNER
Original Assignee
Infineon Technologies Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag filed Critical Infineon Technologies Ag
Publication of WO2004030092A1 publication Critical patent/WO2004030092A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49855—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers for flat-cards, e.g. credit cards
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a semiconductor chip stack with an integrated circuit which is provided for use in a chip card.
  • the IC chips are exposed to sharp bends.
  • the mechanical stability of many chips is not sufficient for this. If the chips are installed in a stabilizing housing, this inevitably involves an increase in the overall thickness.
  • the thickness of the chips is limited to 185 ⁇ m.
  • the chip area is limited to a maximum of 25 m 2 to reduce the risk of breakage.
  • the smaller chip must be thinned down to 60 ⁇ in order to install two-layer chip stacks in chip cards.
  • chip stacks with more than two layers will be used, the chips of which are even thinned to less than 20 ⁇ m.
  • Such heavily thinned chips have a much lower mechanical stability than thick chips and tend to break at the edge of the chip, which can spread over the entire chip.
  • the main reason for this problem is that the crystalline silicon of the chip substrate is most easily broken along the main planes of the crystal lattice.
  • the position of the main planes in the crystal lattice of silicon (diamond structure) is indicated with the Miller indices of the relevant equivalence classes ⁇ 1,0,0 ⁇ , ⁇ 0,1,0 ⁇ and ⁇ 0,0,1 ⁇ .
  • an upper main side of the wafer is a (1, 0, 0) plane.
  • the main planes of the other equivalence classes, which run perpendicular to it, are thus perpendicular to each other and on the upper main side of the wafer. This fact is used for predetermined breaking points to prepare the wafer.
  • a small scratch is created on the edge of the silicon wafer, which acts as a disturbance and causes a notch break.
  • the break runs through the entire wafer from this point. The wafer can thus be separated into individual semiconductor chips.
  • the chips in each case surrounded by scratch frames are usually arranged on the wafer in such a way that the internal semiconductor structures of the integrated circuits, the trenches for electrical insulation or for the formation of memory cell transistors, the conductor tracks applied on the top and the like are each aligned along the main directions of the crystal. These structural elements therefore additionally increase the risk of breakage of the semiconductor chip. This is especially true in the case of heavily thinned semiconductor chips.
  • the object of the present invention is to specify how the risk of breakage of thinned chips, in particular with vertical integration, can be reduced for use in the chip card area.
  • a substrate made of crystalline silicon with a (1, 0, 0) plane can still be used as the top side.
  • the metallic interconnects provided for the integrated circuit on the upper side are essentially aligned along two mutually perpendicular directions, which include angles of at least 10 ° with the ⁇ 0, 1, 0 ⁇ planes and the ⁇ 0, 0, 1 ⁇ planes , If the conductor tracks run obliquely over the main crystal planes, they have a mechanically stabilizing effect.
  • the metallic conductor tracks are also polycrystalline or amorphous and can therefore be deformed or stretched within certain limits. They also have a mechanically reinforcing effect, for example comparable to the fibers in a fabric-reinforced composite material.
  • rectilinear and planar structures of components of the integrated circuit in the crystal can also include angles of at least 10 ° with the ⁇ 0, 1, 0 ⁇ planes and the ⁇ 0, 0, 1 ⁇ planes.
  • the components on the wafer are aligned at an angle, preferably between 15 ° and 45 °, to a main crystal plane which runs perpendicular to the top of the wafer. Because of this alignment, the edges created during the structuring cannot break.
  • the semiconductor chips which form the individual circuit planes are aligned with one another in such a way that the main crystal planes of successive semiconductor chips which are perpendicular to the circuit planes include angles different from 0 ° and 90 °, and preferably in each case different angles. Since two successively arranged circuit levels are connected to one another via a common metallization as an interface, it is sufficient if the metallization of at least one of two successive semiconductor chips at angles different from 0 ° and 90 ° to the perpendicular to the top of the semiconductor chip Main crystal planes is structured.
  • the semiconductor chips configured in this way form a stack of semiconductor chips and are electrically connected to one another via the metallization, the main crystal planes perpendicular to the circuit planes come to lie at angles other than 0 ° and 90 ° without further measures.
  • only semiconductor chips are connected to one another in the semiconductor chip stack, which are each already designed to be break-proof by the alignment of the conductor tracks described above.
  • the conductor tracks of at least some of the semiconductor chips of the semiconductor chip stack are oriented obliquely to the main crystal planes, but the side faces of the chips, the chip edges, are sawn parallel to the conductor track sections in all semiconductor chips, then these side faces can be aligned coplanar with one another.
  • a just delimited chip stack is obtained, in which the positions of the main crystal planes perpendicular to the circuit planes are nevertheless located in the individual circuit planes are different from each other.
  • the main crystal planes, which are perpendicular to the layer planes can therefore be aligned from chip to chip at angles different from 0 ° and from 90 ° to one another, even in the case of just delimited semiconductor chip stacks.
  • FIGS. 1 and 2 A more detailed description of examples of the semiconductor chips or semiconductor chip stacks follows with the aid of FIGS. 1 and 2.
  • Figure 1 shows a schematic of a semiconductor chip in supervision.
  • FIG. 2 shows a schematic of a semiconductor chip stack in cross section.
  • FIG. 1 shows a top view of a semiconductor chip 1 with conductor tracks 2 applied to an upper side.
  • the conductor tracks are essentially aligned along two mutually perpendicular directions.
  • the sections of the conductor tracks are each arranged in the direction A or in the direction B, which are drawn vertically or horizontally in FIG. 1.
  • the upper side of the semiconductor chip shown in FIG. 1 is coplanar with the ⁇ 1, 0, 0 ⁇ planes of the substrate or semiconductor crystal in question.
  • the chip edges 4, 5 are a ⁇ 0, 1, 0 ⁇ plane and a ⁇ 0, 0, 1 ⁇ plane. Instead, the ⁇ 0, 1, 0 ⁇ planes or the ⁇ 0, 0, 1 ⁇ planes each run in one of the directions indicated by the two arrows.
  • the chip edges 4, 5 can be sawn parallel to the conductor tracks. Instead, it is also possible to arrange the lateral chip edges in a direction shown by the arrows and in the direction perpendicular to them. The conductor tracks then run obliquely with respect to the chip edges.
  • the angle 6 shown in FIG. 1 between the direction B of the horizontal conductor track sections in FIG. 1 and the direction of the one main crystal plane or the supplement angle 7 belonging to the angle 6 indicated by the arrow shown on the right is between 10 ° and 80 °, preferably between 15 ° and 75 °. In the example shown in FIG. 1, the angle 6 is 67.5 °.
  • the two directions, which are indicated by the arrows, form an angle of 45 degrees to one another.
  • the main crystal planes of the semiconductor crystals or substrates are at an angle of, in this example, 45 ° to one another, if the conductor track sections of both semiconductor chips are aligned along directions A and B, the
  • semiconductor chips with their respective metallizations aligned parallel to one another are connected to one another in such a way that the main crystal planes of the chips are aligned at an angle of 45 ° to one another and thus stabilize one another.
  • the chip edges 4, 5 are parallel to the sections of the conductor tracks 2, while the main crystal planes of the chips, which are perpendicular to the circuit planes, enclose an angle of 45 degrees with one another and an angle of 22.5 with the relevant metallization of the respective chip ° or 67.5 °.
  • FIG. 2 shows an example of a semiconductor chip stack in cross section, in which a first further semiconductor chip 11 and a second further semiconductor chip 12 are arranged on a lower semiconductor chip 1.
  • the semiconductor chips are each connected to one another by their top sides 3, which are coplanar with the ⁇ 1, 0, 0 ⁇ planes of the substrate or semiconductor crystal.
  • the structured metallizations between the semiconductor chips are omitted.
  • the chip edges 4, 5 on the sides of the cross section shown in FIG. 2 or within the plane of the drawing do not coincide with the other main crystal planes ⁇ 0,1,0 ⁇ and ⁇ 0,0,1 ⁇ . Rather, the chip edges are oriented at different angles to these main crystal planes.
  • the chips in the stack can therefore be placed on top of one another in an edge-conforming manner, while the main crystal planes perpendicular to the top sides 3 are each aligned with two successive semiconductor chips, preferably in pairs with two semiconductor chips, in each case at angles different from 0 ° and 90 °.
  • a main crystal plane perpendicular to the top 3 of the semiconductor chip 1 can form an angle of 55 °, for example, with a main crystal plane perpendicular to the top 3 of the first further semiconductor chip 11.
  • This main crystal plane, which is perpendicular to the upper side 3 of the first further semiconductor chip 11, can, for example, form an angle of 17 ° with a main crystal plane which is perpendicular to the upper side 3 of the second further semiconductor chip 12.
  • angles between the relevant main crystal planes are not only different from each other not only two successive but also any two pairs of semiconductor chips.
  • the conductor tracks of the chips of the semiconductor chip stack are each oriented at different angles to the main crystal planes. This already ensures a certain level of break resistance.
  • the structures of the semiconductor components of the integrated circuit itself can then, with their rectilinear or planar structures, be parallel or coplanar with the main crystal planes of the semiconductor crystal or substrate be aligned. In a preferred embodiment, however, these structures of the components themselves are oriented at an angle of more than 0 ° and less than 90 ° with respect to the main crystal planes.
  • the conductor tracks with their two essential directions lie outside the vertical main crystal planes, but can still be aligned parallel to the structures of the semiconductor components.
  • the semiconductor chips of the semiconductor chip stack can be aligned with one another in such a way that the conductor tracks of the different semiconductor chips are arranged at angles of 0 ° or 90 ° to one another, as is also the case with conventional chip stacks.
  • the semiconductor chip stack Perpendicular to the tops of the chips, ie perpendicular to the ⁇ 1, 0, 0 ⁇ planes, there is therefore no uniform main crystal plane passing through the entire semiconductor chip stack. This significantly increases the break resistance of the semiconductor chip stack.
  • Such a semiconductor chip stack can therefore also be brought to a thickness of at most 185 ⁇ m with three and more semiconductor chips, which allows use in standardized chip cards.
  • the semiconductor chip 1 is, for example, 130 ⁇ m thick
  • the first further semiconductor chip 11 is 30 ⁇ m thick
  • the second further semiconductor chip 12 is 20 ⁇ m thick.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

Selon la présente invention, des puces à semiconducteur (1) ou piles de puces à semiconducteur amincies, destinées à être utilisées dans des cartes à puce, présentent des sections de pistes conductrices (2) agencées dans les sens (A, B) sur une face supérieure (1,0,0) et formant des angles (6, 7) d'au moins 10° avec les plans {0,1,0}- et {0,0,1}- du cristal de silicium, de façon à augmenter la résistance à la rupture.
PCT/DE2003/003057 2002-09-24 2003-09-15 Puces a semiconducteur dans laquelle des pistes conductrices sur un plan cristallin (1,0,0) forment un angle d'au moins 10 degres avec les plans cristallins (0,1,0) et (0,0,1), de façon a augmenter la resistance a la rupture WO2004030092A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE2002144446 DE10244446B4 (de) 2002-09-24 2002-09-24 Halbleiterchipstapel
DE10244446.3 2002-09-24

Publications (1)

Publication Number Publication Date
WO2004030092A1 true WO2004030092A1 (fr) 2004-04-08

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PCT/DE2003/003057 WO2004030092A1 (fr) 2002-09-24 2003-09-15 Puces a semiconducteur dans laquelle des pistes conductrices sur un plan cristallin (1,0,0) forment un angle d'au moins 10 degres avec les plans cristallins (0,1,0) et (0,0,1), de façon a augmenter la resistance a la rupture

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DE (1) DE10244446B4 (fr)
TW (1) TWI242280B (fr)
WO (1) WO2004030092A1 (fr)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5289346A (en) * 1991-02-26 1994-02-22 Microelectronics And Computer Technology Corporation Peripheral to area adapter with protective bumper for an integrated circuit chip
US5773882A (en) * 1994-04-28 1998-06-30 Kabushiki Kaisha Toshiba Seminconductor package
JPH1131787A (ja) * 1997-07-14 1999-02-02 Hitachi Ltd 半導体集積回路装置
FR2794570A1 (fr) * 1999-06-04 2000-12-08 Gemplus Card Int Procede de fabrication de dispositif portable a circuit integre avec chemins de conduction electrique
WO2001052184A2 (fr) * 2000-01-11 2001-07-19 Infineon Technologies Ag Ensemble carte a puce

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5783477A (en) * 1996-09-20 1998-07-21 Hewlett-Packard Company Method for bonding compounds semiconductor wafers to create an ohmic interface
US6262487B1 (en) * 1998-06-23 2001-07-17 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device, semiconductor integrated circuit wiring method, and cell arranging method

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5289346A (en) * 1991-02-26 1994-02-22 Microelectronics And Computer Technology Corporation Peripheral to area adapter with protective bumper for an integrated circuit chip
US5773882A (en) * 1994-04-28 1998-06-30 Kabushiki Kaisha Toshiba Seminconductor package
JPH1131787A (ja) * 1997-07-14 1999-02-02 Hitachi Ltd 半導体集積回路装置
FR2794570A1 (fr) * 1999-06-04 2000-12-08 Gemplus Card Int Procede de fabrication de dispositif portable a circuit integre avec chemins de conduction electrique
WO2001052184A2 (fr) * 2000-01-11 2001-07-19 Infineon Technologies Ag Ensemble carte a puce

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 1999, no. 05 31 May 1999 (1999-05-31) *

Also Published As

Publication number Publication date
TW200405538A (en) 2004-04-01
DE10244446A1 (de) 2004-04-01
TWI242280B (en) 2005-10-21
DE10244446B4 (de) 2004-08-19

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