WO2004030092A1 - Semiconductor chip on which conductor tracks on a (1,0,0) crystal plane form an angle of at least ten degrees with the (0,1,0) and (0,0,1) crystal planes in order to increase the fracture resistance - Google Patents

Semiconductor chip on which conductor tracks on a (1,0,0) crystal plane form an angle of at least ten degrees with the (0,1,0) and (0,0,1) crystal planes in order to increase the fracture resistance Download PDF

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Publication number
WO2004030092A1
WO2004030092A1 PCT/DE2003/003057 DE0303057W WO2004030092A1 WO 2004030092 A1 WO2004030092 A1 WO 2004030092A1 DE 0303057 W DE0303057 W DE 0303057W WO 2004030092 A1 WO2004030092 A1 WO 2004030092A1
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semiconductor
planes
semiconductor chip
crystal
conductor tracks
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PCT/DE2003/003057
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German (de)
French (fr)
Inventor
Holger HÜBNER
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Infineon Technologies Ag
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Publication of WO2004030092A1 publication Critical patent/WO2004030092A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49855—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers for flat-cards, e.g. credit cards
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a semiconductor chip stack with an integrated circuit which is provided for use in a chip card.
  • the IC chips are exposed to sharp bends.
  • the mechanical stability of many chips is not sufficient for this. If the chips are installed in a stabilizing housing, this inevitably involves an increase in the overall thickness.
  • the thickness of the chips is limited to 185 ⁇ m.
  • the chip area is limited to a maximum of 25 m 2 to reduce the risk of breakage.
  • the smaller chip must be thinned down to 60 ⁇ in order to install two-layer chip stacks in chip cards.
  • chip stacks with more than two layers will be used, the chips of which are even thinned to less than 20 ⁇ m.
  • Such heavily thinned chips have a much lower mechanical stability than thick chips and tend to break at the edge of the chip, which can spread over the entire chip.
  • the main reason for this problem is that the crystalline silicon of the chip substrate is most easily broken along the main planes of the crystal lattice.
  • the position of the main planes in the crystal lattice of silicon (diamond structure) is indicated with the Miller indices of the relevant equivalence classes ⁇ 1,0,0 ⁇ , ⁇ 0,1,0 ⁇ and ⁇ 0,0,1 ⁇ .
  • an upper main side of the wafer is a (1, 0, 0) plane.
  • the main planes of the other equivalence classes, which run perpendicular to it, are thus perpendicular to each other and on the upper main side of the wafer. This fact is used for predetermined breaking points to prepare the wafer.
  • a small scratch is created on the edge of the silicon wafer, which acts as a disturbance and causes a notch break.
  • the break runs through the entire wafer from this point. The wafer can thus be separated into individual semiconductor chips.
  • the chips in each case surrounded by scratch frames are usually arranged on the wafer in such a way that the internal semiconductor structures of the integrated circuits, the trenches for electrical insulation or for the formation of memory cell transistors, the conductor tracks applied on the top and the like are each aligned along the main directions of the crystal. These structural elements therefore additionally increase the risk of breakage of the semiconductor chip. This is especially true in the case of heavily thinned semiconductor chips.
  • the object of the present invention is to specify how the risk of breakage of thinned chips, in particular with vertical integration, can be reduced for use in the chip card area.
  • a substrate made of crystalline silicon with a (1, 0, 0) plane can still be used as the top side.
  • the metallic interconnects provided for the integrated circuit on the upper side are essentially aligned along two mutually perpendicular directions, which include angles of at least 10 ° with the ⁇ 0, 1, 0 ⁇ planes and the ⁇ 0, 0, 1 ⁇ planes , If the conductor tracks run obliquely over the main crystal planes, they have a mechanically stabilizing effect.
  • the metallic conductor tracks are also polycrystalline or amorphous and can therefore be deformed or stretched within certain limits. They also have a mechanically reinforcing effect, for example comparable to the fibers in a fabric-reinforced composite material.
  • rectilinear and planar structures of components of the integrated circuit in the crystal can also include angles of at least 10 ° with the ⁇ 0, 1, 0 ⁇ planes and the ⁇ 0, 0, 1 ⁇ planes.
  • the components on the wafer are aligned at an angle, preferably between 15 ° and 45 °, to a main crystal plane which runs perpendicular to the top of the wafer. Because of this alignment, the edges created during the structuring cannot break.
  • the semiconductor chips which form the individual circuit planes are aligned with one another in such a way that the main crystal planes of successive semiconductor chips which are perpendicular to the circuit planes include angles different from 0 ° and 90 °, and preferably in each case different angles. Since two successively arranged circuit levels are connected to one another via a common metallization as an interface, it is sufficient if the metallization of at least one of two successive semiconductor chips at angles different from 0 ° and 90 ° to the perpendicular to the top of the semiconductor chip Main crystal planes is structured.
  • the semiconductor chips configured in this way form a stack of semiconductor chips and are electrically connected to one another via the metallization, the main crystal planes perpendicular to the circuit planes come to lie at angles other than 0 ° and 90 ° without further measures.
  • only semiconductor chips are connected to one another in the semiconductor chip stack, which are each already designed to be break-proof by the alignment of the conductor tracks described above.
  • the conductor tracks of at least some of the semiconductor chips of the semiconductor chip stack are oriented obliquely to the main crystal planes, but the side faces of the chips, the chip edges, are sawn parallel to the conductor track sections in all semiconductor chips, then these side faces can be aligned coplanar with one another.
  • a just delimited chip stack is obtained, in which the positions of the main crystal planes perpendicular to the circuit planes are nevertheless located in the individual circuit planes are different from each other.
  • the main crystal planes, which are perpendicular to the layer planes can therefore be aligned from chip to chip at angles different from 0 ° and from 90 ° to one another, even in the case of just delimited semiconductor chip stacks.
  • FIGS. 1 and 2 A more detailed description of examples of the semiconductor chips or semiconductor chip stacks follows with the aid of FIGS. 1 and 2.
  • Figure 1 shows a schematic of a semiconductor chip in supervision.
  • FIG. 2 shows a schematic of a semiconductor chip stack in cross section.
  • FIG. 1 shows a top view of a semiconductor chip 1 with conductor tracks 2 applied to an upper side.
  • the conductor tracks are essentially aligned along two mutually perpendicular directions.
  • the sections of the conductor tracks are each arranged in the direction A or in the direction B, which are drawn vertically or horizontally in FIG. 1.
  • the upper side of the semiconductor chip shown in FIG. 1 is coplanar with the ⁇ 1, 0, 0 ⁇ planes of the substrate or semiconductor crystal in question.
  • the chip edges 4, 5 are a ⁇ 0, 1, 0 ⁇ plane and a ⁇ 0, 0, 1 ⁇ plane. Instead, the ⁇ 0, 1, 0 ⁇ planes or the ⁇ 0, 0, 1 ⁇ planes each run in one of the directions indicated by the two arrows.
  • the chip edges 4, 5 can be sawn parallel to the conductor tracks. Instead, it is also possible to arrange the lateral chip edges in a direction shown by the arrows and in the direction perpendicular to them. The conductor tracks then run obliquely with respect to the chip edges.
  • the angle 6 shown in FIG. 1 between the direction B of the horizontal conductor track sections in FIG. 1 and the direction of the one main crystal plane or the supplement angle 7 belonging to the angle 6 indicated by the arrow shown on the right is between 10 ° and 80 °, preferably between 15 ° and 75 °. In the example shown in FIG. 1, the angle 6 is 67.5 °.
  • the two directions, which are indicated by the arrows, form an angle of 45 degrees to one another.
  • the main crystal planes of the semiconductor crystals or substrates are at an angle of, in this example, 45 ° to one another, if the conductor track sections of both semiconductor chips are aligned along directions A and B, the
  • semiconductor chips with their respective metallizations aligned parallel to one another are connected to one another in such a way that the main crystal planes of the chips are aligned at an angle of 45 ° to one another and thus stabilize one another.
  • the chip edges 4, 5 are parallel to the sections of the conductor tracks 2, while the main crystal planes of the chips, which are perpendicular to the circuit planes, enclose an angle of 45 degrees with one another and an angle of 22.5 with the relevant metallization of the respective chip ° or 67.5 °.
  • FIG. 2 shows an example of a semiconductor chip stack in cross section, in which a first further semiconductor chip 11 and a second further semiconductor chip 12 are arranged on a lower semiconductor chip 1.
  • the semiconductor chips are each connected to one another by their top sides 3, which are coplanar with the ⁇ 1, 0, 0 ⁇ planes of the substrate or semiconductor crystal.
  • the structured metallizations between the semiconductor chips are omitted.
  • the chip edges 4, 5 on the sides of the cross section shown in FIG. 2 or within the plane of the drawing do not coincide with the other main crystal planes ⁇ 0,1,0 ⁇ and ⁇ 0,0,1 ⁇ . Rather, the chip edges are oriented at different angles to these main crystal planes.
  • the chips in the stack can therefore be placed on top of one another in an edge-conforming manner, while the main crystal planes perpendicular to the top sides 3 are each aligned with two successive semiconductor chips, preferably in pairs with two semiconductor chips, in each case at angles different from 0 ° and 90 °.
  • a main crystal plane perpendicular to the top 3 of the semiconductor chip 1 can form an angle of 55 °, for example, with a main crystal plane perpendicular to the top 3 of the first further semiconductor chip 11.
  • This main crystal plane, which is perpendicular to the upper side 3 of the first further semiconductor chip 11, can, for example, form an angle of 17 ° with a main crystal plane which is perpendicular to the upper side 3 of the second further semiconductor chip 12.
  • angles between the relevant main crystal planes are not only different from each other not only two successive but also any two pairs of semiconductor chips.
  • the conductor tracks of the chips of the semiconductor chip stack are each oriented at different angles to the main crystal planes. This already ensures a certain level of break resistance.
  • the structures of the semiconductor components of the integrated circuit itself can then, with their rectilinear or planar structures, be parallel or coplanar with the main crystal planes of the semiconductor crystal or substrate be aligned. In a preferred embodiment, however, these structures of the components themselves are oriented at an angle of more than 0 ° and less than 90 ° with respect to the main crystal planes.
  • the conductor tracks with their two essential directions lie outside the vertical main crystal planes, but can still be aligned parallel to the structures of the semiconductor components.
  • the semiconductor chips of the semiconductor chip stack can be aligned with one another in such a way that the conductor tracks of the different semiconductor chips are arranged at angles of 0 ° or 90 ° to one another, as is also the case with conventional chip stacks.
  • the semiconductor chip stack Perpendicular to the tops of the chips, ie perpendicular to the ⁇ 1, 0, 0 ⁇ planes, there is therefore no uniform main crystal plane passing through the entire semiconductor chip stack. This significantly increases the break resistance of the semiconductor chip stack.
  • Such a semiconductor chip stack can therefore also be brought to a thickness of at most 185 ⁇ m with three and more semiconductor chips, which allows use in standardized chip cards.
  • the semiconductor chip 1 is, for example, 130 ⁇ m thick
  • the first further semiconductor chip 11 is 30 ⁇ m thick
  • the second further semiconductor chip 12 is 20 ⁇ m thick.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

Thinned semiconductor chips (1) or semiconductor chip stacks, for application in chipcards, have arrangements of sections of conductor tracks (2) in the (A, B) directions on an (1,0,0) upper surface, which include an angle (6, 7) of at least 10 DEG with the {0,1,0} planes and the {0,0,1} planes of the silicon crystal to increase fracture resistance.

Description

HALBLEITERCHIP, WOBEI LEITERBAHNEN AUF EINER (1,0,0) KRISTALLEBENE EINEN WINKEL VON MINDESTENS ZEHN GRAD MIT DEN (0,1,0) UND (0,0,1) KRISTALLEBENEN BILDEN, UM DIE BRUCHSICHERHEIT ZU ERHÖHENSEMICONDUCTOR CHIP, WOBE LEAD PATHS ON A (1,0,0) CRYSTAL LIFE AN ANGLE OF AT LEAST TEN DEGREE WITH THE (0,1,0) AND (0,0,1) CRYSTAL LIVES TO INCREASE THE BREAKAGE SAFETY
Die vorliegende Erfindung betrifft einen Halbleiterchipstapel mit einer integrierten Schaltung, die zum Einsatz in einer Chipkarte vorgesehen ist.The present invention relates to a semiconductor chip stack with an integrated circuit which is provided for use in a chip card.
In Chipkarten, aber beispielsweise auch in elektronischen Briefsortieranlagen, werden die IC-Chips starken Biegungen ausgesetzt. Die mechanische Stabilität vieler Chips ist dafür nicht ausreichend. Wenn die Chips in ein stabilisierendes Gehäuse eingebaut werden, ist das zwangsläufig mit einer Erhöhung der Gesamtdicke verbunden. Im Chipkartenbereich ist die Dicke der Chips auf 185 um begrenzt. Die Chipfläche wird hier zur Verminderung der Bruchgefahr auf maximal 25 m2 begrenzt.In chip cards, but also in electronic letter sorting systems, for example, the IC chips are exposed to sharp bends. The mechanical stability of many chips is not sufficient for this. If the chips are installed in a stabilizing housing, this inevitably involves an increase in the overall thickness. In the chip card area the thickness of the chips is limited to 185 µm. The chip area is limited to a maximum of 25 m 2 to reduce the risk of breakage.
Wegen der Beschränkung der maximal zulässigen Dicke muss zum Einbau zweilagiger Chipstapel in Chipkarten der kleinere Chip bis auf 60 μ gedünnt werden. In Zukunft werden Chipstapel mit mehr als zwei Lagen verwendet, deren Chips sogar bis auf unter 20 μm gedünnt werden. Derart stark gedünnte Chips haben eine wesentlich geringere mechanische Stabilität als dicke Chips und neigen zu Kerbbrüchen am Chiprand, die sich über den gesamten Chip ausbreiten können.Due to the limitation of the maximum permissible thickness, the smaller chip must be thinned down to 60 μ in order to install two-layer chip stacks in chip cards. In the future, chip stacks with more than two layers will be used, the chips of which are even thinned to less than 20 μm. Such heavily thinned chips have a much lower mechanical stability than thick chips and tend to break at the edge of the chip, which can spread over the entire chip.
Dieses Problem hat seine Ursache vor allem darin, dass das kristalline Silizium des Chipsubstrates am leichtesten entlang der Hauptebenen des Kristallgitters bricht. Die Lage der Hauptebenen in dem Kristallgitter des Siliziums (Diamantstruktur) wird mit den Miller-Indizes der betreffenden Äquivalenzklassen {1,0,0}, {0,1,0} und {0,0,1} angegeben. Bei Sechs-Zoll-Wafern aus (1, 0, 0) -Material ist eine obere Hauptseite des Wafers eine (1, 0, 0) -Ebene. Die senkrecht dazu ver- laufenden Hauptebenen der anderen Äquivalenzklassen stehen somit senkrecht aufeinander und auf der oberen Hauptseite des Wafers. Diese Tatsache wird dazu benutzt, Sollbruchstellen des Wafers zu präparieren. Zu diesem Zweck wird am Rand der Siliziumscheibe ein kleiner Kratzer erzeugt, der als Störung wirkt und einen Kerbbruch hervorruft. Beim Verbiegen des Wafers läuft von dieser Stelle ausgehend der Bruch durch den ganzen Wafer. Der Wafer kann so in einzelne Halbleiterchips vereinzelt werden.The main reason for this problem is that the crystalline silicon of the chip substrate is most easily broken along the main planes of the crystal lattice. The position of the main planes in the crystal lattice of silicon (diamond structure) is indicated with the Miller indices of the relevant equivalence classes {1,0,0}, {0,1,0} and {0,0,1}. For six-inch wafers made of (1, 0, 0) material, an upper main side of the wafer is a (1, 0, 0) plane. The main planes of the other equivalence classes, which run perpendicular to it, are thus perpendicular to each other and on the upper main side of the wafer. This fact is used for predetermined breaking points to prepare the wafer. For this purpose, a small scratch is created on the edge of the silicon wafer, which acts as a disturbance and causes a notch break. When the wafer is bent, the break runs through the entire wafer from this point. The wafer can thus be separated into individual semiconductor chips.
Die jeweils von Ritzrahmen umgebenen Chips werden üblicherweise so auf dem Wafer angeordnet, dass die internen Halblei- terstrukturen der integrierten Schaltungen, die Gräben zur elektrischen Isolation oder zur Ausbildung von Speicherzellentransistoren, die oberseitig aufgebrachten Leiterbahnen und dergleichen jeweils entlang der Hauptrichtungen des Kristalls ausgerichtet sind. Diese Strukturelemente verstärken daher die Bruchgefahr des Halbleiterchips zusätzlich. Das gilt insbesondere im Fall stark gedünnter Halbleiterchips.The chips in each case surrounded by scratch frames are usually arranged on the wafer in such a way that the internal semiconductor structures of the integrated circuits, the trenches for electrical insulation or for the formation of memory cell transistors, the conductor tracks applied on the top and the like are each aligned along the main directions of the crystal. These structural elements therefore additionally increase the risk of breakage of the semiconductor chip. This is especially true in the case of heavily thinned semiconductor chips.
Dieses Problem tritt verstärkt auf, wenn mehrere Halbleiterchips im Zuge der vertikalen oder kubischen Integration zu Halbleiterchipstapeln, so genannten Stacks, verbunden werden. Bei der vertikalen Integration müssen die Chips besonders dünn geschliffen werden, insbesondere wenn ein Einsatz in einer Chipkarte vorgesehen ist. Wenn die Chips der vertikalen Integration wie herkömmlich hergestellt werden, setzt sich die Bruchneigung durch den gesamten Chipstapel verstärkt fort.This problem becomes more pronounced when several semiconductor chips are connected to form semiconductor stacks in the course of vertical or cubic integration. In the case of vertical integration, the chips must be ground particularly thinly, in particular if they are to be used in a chip card. If the chips of vertical integration are manufactured in the conventional way, the tendency to breakage continues throughout the entire chip stack.
Aufgabe der vorliegenden Erfindung ist es, anzugeben, wie zum Einsatz im Chipkartenbereich die Bruchgefahr gedünnter Chips, insbesondere bei vertikaler Integration, verringert werden kann.The object of the present invention is to specify how the risk of breakage of thinned chips, in particular with vertical integration, can be reduced for use in the chip card area.
Diese Aufgabe wird mit dem Halbleiterchip oder dem Halbleiterchipstapel mit den Merkmalen des Anspruches 1 oder 3 ge- löst. Ausgestaltungen ergeben sich aus den abhängigen Ansprüchen. Es kann nach wie vor ein Substrat aus kristallinem Silizium mit einer (1, 0, 0) -Ebene als Oberseite verwendet werden. Die für die integrierte Schaltung vorgesehenen metallischen Leiterbahnen auf der Oberseite werden im Wesentlichen längs zweier zueinander senkrechter Richtungen ausgerichtet, die mit den { 0, 1, 0} -Ebenen und den { 0, 0, 1} -Ebenen Winkel von mindestens 10° einschließen. Wenn die Leiterbahnen daher schräg über die Hauptkristallebenen verlaufen, wirken sie mechanisch stabilisierend. Die metallischen Leiterbahnen sind außerdem polykristallin oder amorph und können daher in gewissen Grenzen verformt oder gedehnt werden. Sie wirken so zusätzlich mechanisch verstärkend, etwa vergleichbar den Fasern in einem gewebeverstärkten Verbundwerkstoff .This object is achieved with the semiconductor chip or the semiconductor chip stack with the features of claim 1 or 3. Refinements result from the dependent claims. A substrate made of crystalline silicon with a (1, 0, 0) plane can still be used as the top side. The metallic interconnects provided for the integrated circuit on the upper side are essentially aligned along two mutually perpendicular directions, which include angles of at least 10 ° with the {0, 1, 0} planes and the {0, 0, 1} planes , If the conductor tracks run obliquely over the main crystal planes, they have a mechanically stabilizing effect. The metallic conductor tracks are also polycrystalline or amorphous and can therefore be deformed or stretched within certain limits. They also have a mechanically reinforcing effect, for example comparable to the fibers in a fabric-reinforced composite material.
Zusätzlich hierzu können geradlinige und ebene Strukturen von Bauelementen der integrierten Schaltung in dem Kristall ebenfalls Winkel von mindestens 10° mit den {0, 1, 0}-Ebenen und den {0, 0, 1} -Ebenen einschließen. Zu diesem Zweck werden bei der Herstellung der Halbleiterchips die Bauelemente auf dem Wafer in einem Winkel, vorzugsweise zwischen 15° und 45°, zu einer Hauptkristallebene ausgerichtet, die senkrecht auf der Oberseite des Wafers verläuft. Wegen dieser Ausrichtung können sich die bei der Strukturierung erzeugten Kanten nicht bruchauslösend auswirken.In addition to this, rectilinear and planar structures of components of the integrated circuit in the crystal can also include angles of at least 10 ° with the {0, 1, 0} planes and the {0, 0, 1} planes. For this purpose, in the manufacture of the semiconductor chips, the components on the wafer are aligned at an angle, preferably between 15 ° and 45 °, to a main crystal plane which runs perpendicular to the top of the wafer. Because of this alignment, the edges created during the structuring cannot break.
Da die Strukturen der Halbleiterbauelemente durch die bei der Herstellung eingesetzte Fotolithographie definiert werden, genügt es zur Herstellung eines erfindungsgemäßen Halbleiterchips im Prinzip, den Wafer bei den Belichtungsprozessen um den angegebenen Winkel verdreht in den Stepper einzulegenSince the structures of the semiconductor components are defined by the photolithography used in the production, it is in principle sufficient to produce a semiconductor chip according to the invention by inserting the wafer into the stepper rotated by the specified angle during the exposure processes
(d. h. Fiat oder Notch nicht unten oder seitlich, sondern um 15° bis 45° verdreht) . Alle anderen Prozessschritte können im Wesentlichen unverändert bleiben. Die Anordnung der Chips auf dem Wafer ist auf diese Weise gegenüber der herkömmlichen Fertigung gedreht und die Sägestraßen werden schräg zu der Apparatur ausgerichtet. Für das Design und die Leitungsführung im Halbleiterchip selbst ergeben sich keine Änderungen, die internen Strukturen der Halbleiterbauelemente können insbesondere nach wie vor parallel zur Chipkante verlaufen, die ja nicht parallel zu einer Hauptkristallebene gesägt zu werden braucht .(ie Fiat or Notch not at the bottom or at the side, but rotated by 15 ° to 45 °). All other process steps can remain essentially unchanged. In this way, the arrangement of the chips on the wafer is rotated compared to conventional production and the sawing lines are aligned at an angle to the apparatus. There are no changes for the design and the wiring in the semiconductor chip itself, The internal structures of the semiconductor components can in particular still run parallel to the chip edge, which does not need to be sawn parallel to a main crystal plane.
Bei einem erfindungsgemäßen Halbleiterchipstapel sind die Halbleiterchips, die die einzelnen Schaltungsebenen bilden, so zueinander ausgerichtet, dass die auf den Schaltungsebenen senkrecht stehenden Hauptkristallebenen aufeinanderfolgender Halbleiterchips von 0° und 90° verschiedene Winkel einschließen, und zwar vorzugsweise jeweils unterschiedlich große Winkel. Da jeweils zwei aufeinanderfolgend übereinander angeordnete Schaltungsebenen über eine gemeinsame Metallisierung als Interface miteinander verbunden sind, genügt es, wenn die Me- tallisierung zumindest des einen von zwei aufeinanderfolgenden Halbleiterchips in von 0° und 90° verschiedenen Winkeln zu den auf der Oberseite des Halbleiterchips senkrecht stehenden Hauptkristallebenen strukturiert ist. Wenn die so ausgestalteten Halbleiterchips zum Halbleiterchipstapel überein- ander gesetzt und über die Metallisierung elektrisch miteinander verbunden werden, kommen die senkrecht zu den Schaltungsebenen verlaufenden Hauptkristallebenen ohne weitere Maßnahmen in von 0° und 90° verschiedenen Winkeln zueinander zu liegen. In einem anderen Ausführungsbeispiel sind in dem Halbleiterchipstapel nur Halbleiterchips miteinander verbunden, die bereits jeder für sich durch die oben beschriebene Ausrichtung der Leiterbahnen bruchsicher ausgestaltet sind.In a semiconductor chip stack according to the invention, the semiconductor chips which form the individual circuit planes are aligned with one another in such a way that the main crystal planes of successive semiconductor chips which are perpendicular to the circuit planes include angles different from 0 ° and 90 °, and preferably in each case different angles. Since two successively arranged circuit levels are connected to one another via a common metallization as an interface, it is sufficient if the metallization of at least one of two successive semiconductor chips at angles different from 0 ° and 90 ° to the perpendicular to the top of the semiconductor chip Main crystal planes is structured. If the semiconductor chips configured in this way form a stack of semiconductor chips and are electrically connected to one another via the metallization, the main crystal planes perpendicular to the circuit planes come to lie at angles other than 0 ° and 90 ° without further measures. In another exemplary embodiment, only semiconductor chips are connected to one another in the semiconductor chip stack, which are each already designed to be break-proof by the alignment of the conductor tracks described above.
Wenn die Leiterbahnen zumindest eines Teils der Halbleiter- chips des Halbleiterchipstapels schräg zu den Hauptkristallebenen ausgerichtet sind, aber die Seitenflächen der Chips, die Chipkanten, bei allen Halbleiterchips parallel zu den Leiterbahnabschnitten gesägt sind, dann können diese Seitenflächen coplanar zueinander ausgerichtet werden. Man erhält auf diese Weise einen eben begrenzten Chipstapel, in dem dennoch in den einzelnen Schaltungsebenen die Lagen der senkrecht zu den Schaltungsebenen liegenden Hauptkristallebenen untereinander verschieden sind. Die Hauptkristallebenen, die senkrecht auf den Schichtebenen stehen, können daher auch bei eben begrenzten Halbleiterchipstapeln von Chip zu Chip in von 0° und von 90° verschiedenen Winkeln zueinander ausgerichtet sein.If the conductor tracks of at least some of the semiconductor chips of the semiconductor chip stack are oriented obliquely to the main crystal planes, but the side faces of the chips, the chip edges, are sawn parallel to the conductor track sections in all semiconductor chips, then these side faces can be aligned coplanar with one another. In this way, a just delimited chip stack is obtained, in which the positions of the main crystal planes perpendicular to the circuit planes are nevertheless located in the individual circuit planes are different from each other. The main crystal planes, which are perpendicular to the layer planes, can therefore be aligned from chip to chip at angles different from 0 ° and from 90 ° to one another, even in the case of just delimited semiconductor chip stacks.
Es folgt eine genauere Beschreibung von Beispielen der Halbleiterchips oder Halbleiterchipstapel anhand der Figuren 1 und 2.A more detailed description of examples of the semiconductor chips or semiconductor chip stacks follows with the aid of FIGS. 1 and 2.
Die Figur 1 zeigt ein Schema eines Halbleiterchips in Aufsicht .Figure 1 shows a schematic of a semiconductor chip in supervision.
Die Figur 2 zeigt ein Schema eines Halbleiterchipstapels im Querschnitt.FIG. 2 shows a schematic of a semiconductor chip stack in cross section.
In der Figur 1 ist in Aufsicht ein Halbleiterchip 1 mit auf einer Oberseite aufgebrachten Leiterbahnen 2 dargestellt. Die Leiterbahnen sind hier im Wesentlichen längs zweier zueinan- der senkrechter Richtungen ausgerichtet. Die Abschnitte der Leiterbahnen sind so jeweils in der Richtung A oder in der Richtung B angeordnet, die in der Figur 1 senkrecht beziehungsweise waagrecht gezeichnet sind. Die in der Figur 1 dargestellte Oberseite des Halbleiterchips ist coplanar zu den {1, 0, 0} -Ebenen des betreffenden Substrats oder Halbleiterkristalls. Bei herkömmlichen Halbleiterchips sind die Chipkanten 4, 5 eine { 0, 1, 0}-Ebene und eine {0, 0, 1 }-Ebene. Statt dessen verlaufen hier die { 0, 1, 0} -Ebenen oder die { 0, 0, 1}-Ebenen zum Beispiel jeweils in einer der durch die beiden eingezeichne- ten Pfeile angegebenen Richtungen. Die Chipkanten 4, 5 können jedoch parallel zu den Leiterbahnen gesägt sein. Statt dessen ist es auch möglich, die seitlichen Chipkanten in einer durch die Pfeile dargestellten Richtung und in der senkrecht dazu verlaufenden Richtung anzuordnen. Die Leiterbahnen verlaufen dann schräg bezüglich der Chipkanten. Der in der Figur 1 eingezeichnete Winkel 6 zwischen der Richtung B der in der Figur 1 waagrechten Leiterbahnabschnitte und der durch den rechts eingezeichneten Pfeil angegebenen Richtung der einen Hauptkristallebene oder der zu dem Winkel 6 gehörende Supplementwinkel 7 liegt zwischen 10° und 80°, vorzugsweise zwischen 15° und 75°. Der Winkel 6 beträgt in dem in der Figur 1 dargestellten Beispiel 67,5°. Die beiden Richtungen, die durch die eingezeichneten Pfeile angegeben sind, bilden einen Winkel von 45 Grad zueinander.1 shows a top view of a semiconductor chip 1 with conductor tracks 2 applied to an upper side. The conductor tracks are essentially aligned along two mutually perpendicular directions. The sections of the conductor tracks are each arranged in the direction A or in the direction B, which are drawn vertically or horizontally in FIG. 1. The upper side of the semiconductor chip shown in FIG. 1 is coplanar with the {1, 0, 0} planes of the substrate or semiconductor crystal in question. In conventional semiconductor chips, the chip edges 4, 5 are a {0, 1, 0} plane and a {0, 0, 1} plane. Instead, the {0, 1, 0} planes or the {0, 0, 1} planes each run in one of the directions indicated by the two arrows. However, the chip edges 4, 5 can be sawn parallel to the conductor tracks. Instead, it is also possible to arrange the lateral chip edges in a direction shown by the arrows and in the direction perpendicular to them. The conductor tracks then run obliquely with respect to the chip edges. The angle 6 shown in FIG. 1 between the direction B of the horizontal conductor track sections in FIG. 1 and the direction of the one main crystal plane or the supplement angle 7 belonging to the angle 6 indicated by the arrow shown on the right is between 10 ° and 80 °, preferably between 15 ° and 75 °. In the example shown in FIG. 1, the angle 6 is 67.5 °. The two directions, which are indicated by the arrows, form an angle of 45 degrees to one another.
Wenn bei einem Halbleiterchipstapel aus zwei Halbleiterchips die Hauptkristallebenen der Halbleiterkristalle oder Substrate zueinander einen Winkel von, in diesem Beispiel, 45° einnehmen, falls die Leiterbahnabschnitte beider Halbleiterchips längs der Richtungen A und B ausgerichtet sind, werden dieIf, in a semiconductor chip stack comprising two semiconductor chips, the main crystal planes of the semiconductor crystals or substrates are at an angle of, in this example, 45 ° to one another, if the conductor track sections of both semiconductor chips are aligned along directions A and B, the
Halbleiterchips bei der vertikalen Integration mit ihren parallel zueinander ausgerichteten jeweiligen Metallisierungen so miteinander verbunden, dass die Hauptkristallebenen der Chips in einem Winkel von 45° zueinander ausgerichtet sind und sich auf diese Weise gegenseitig stabilisieren. Die Chipkanten 4, 5 sind in diesem Beispiel parallel zu den Abschnitten der Leiterbahnen 2, während die senkrecht zu den Schaltungsebenen liegenden Hauptkristallebenen der Chips miteinander einen Winkel von 45 Grad einschließen und mit der betref- fenden Metallisierung des jeweiligen Chips einen Winkel von 22,5° bzw. von 67,5°.In vertical integration, semiconductor chips with their respective metallizations aligned parallel to one another are connected to one another in such a way that the main crystal planes of the chips are aligned at an angle of 45 ° to one another and thus stabilize one another. In this example, the chip edges 4, 5 are parallel to the sections of the conductor tracks 2, while the main crystal planes of the chips, which are perpendicular to the circuit planes, enclose an angle of 45 degrees with one another and an angle of 22.5 with the relevant metallization of the respective chip ° or 67.5 °.
Die Figur 2 zeigt ein Beispiel eines Halbleiterchipstapels im Querschnitt, bei dem auf einem unteren Halbleiterchip 1 ein erster weiterer Halbleiterchip 11 und ein zweiter weiterer Halbleiterchip 12 angeordnet sind. Die Halbleiterchips sind jeweils mit ihren Oberseiten 3 miteinander verbunden, die coplanar zu den {1, 0, 0}-Ebenen des Substrates oder Halbleiterkristalls sind. In der verein achten Darstellung der Figur 2 sind die strukturierten Metallisierungen zwischen den Halbleiterchips weggelassen. Die Chipkanten 4, 5 an den Seiten des in der Figur 2 dargestellten Querschnitts bzw. innerhalb der Zeichenebene fallen erfindungsgemäß nicht mit den übrigen Hauptkristallebenen {0,1,0} und {0,0,1} zusammen. Die Chipkanten sind vielmehr in unterschiedlichen Winkeln zu diesen Hauptkristallebenen ausgerichtet. Die Chips können in dem Stapel daher kantenkonform übereinander gesetzt sein, während die senkrecht auf den Oberseiten 3 stehenden Hauptkristallebenen je zweier aufeinanderfolgender Halbleiterchips, vorzugsweise paarweise je zweier Halbleiterchips, jeweils in von 0° und 90° verschiedenen Winkeln zueinander ausgerichtet sind.FIG. 2 shows an example of a semiconductor chip stack in cross section, in which a first further semiconductor chip 11 and a second further semiconductor chip 12 are arranged on a lower semiconductor chip 1. The semiconductor chips are each connected to one another by their top sides 3, which are coplanar with the {1, 0, 0} planes of the substrate or semiconductor crystal. In the eighth representation of FIG. 2, the structured metallizations between the semiconductor chips are omitted. According to the invention, the chip edges 4, 5 on the sides of the cross section shown in FIG. 2 or within the plane of the drawing do not coincide with the other main crystal planes {0,1,0} and {0,0,1}. Rather, the chip edges are oriented at different angles to these main crystal planes. The chips in the stack can therefore be placed on top of one another in an edge-conforming manner, while the main crystal planes perpendicular to the top sides 3 are each aligned with two successive semiconductor chips, preferably in pairs with two semiconductor chips, in each case at angles different from 0 ° and 90 °.
Eine senkrecht auf der Oberseite 3 des Halbleiterchips 1 stehende Hauptkristallebene kann mit einer senkrecht auf der Oberseite 3 des ersten weiteren Halbleiterchips 11 stehenden Hauptkristallebene zum Beispiel einen Winkel von 55° bilden. Diese senkrecht auf der Oberseite 3 des ersten weiteren Halbleiterchips 11 stehende Hauptkristallebene kann mit einer senkrecht auf der Oberseite 3 des zweiten weiteren Halblei- terchips 12 stehenden Hauptkristallebene zum Beispiel einen Winkel von 17° bilden. Damit ist auch erreicht, dass zwischen den betreffenden Hauptkristallebenen des unteren Halbleiterchips 1 und des zweiten weiteren Halbleiterchips 12 ein Winkel von 55° - 17° = 38° oder 55° + 17° = 72° vorhanden ist, der also von den anderen Winkeln 55° und 17° verschieden ist.A main crystal plane perpendicular to the top 3 of the semiconductor chip 1 can form an angle of 55 °, for example, with a main crystal plane perpendicular to the top 3 of the first further semiconductor chip 11. This main crystal plane, which is perpendicular to the upper side 3 of the first further semiconductor chip 11, can, for example, form an angle of 17 ° with a main crystal plane which is perpendicular to the upper side 3 of the second further semiconductor chip 12. This also means that an angle of 55 ° -17 ° = 38 ° or 55 ° + 17 ° = 72 ° is present between the relevant main crystal planes of the lower semiconductor chip 1 and the second further semiconductor chip 12, that is to say of the other angles 55 ° and 17 ° is different.
Hier sind somit die Winkel zwischen den betreffenden Hauptkristallebenen nicht nur je zweier aufeinanderfolgender, sondern je zweier beliebiger Paare von Halbleiterchips voneinander verschieden.Here, the angles between the relevant main crystal planes are not only different from each other not only two successive but also any two pairs of semiconductor chips.
Die Leiterbahnen der Chips des Halbleiterchipstapels sind jeweils in unterschiedlichen Winkeln zu den Hauptkristallebenen ausgerichtet. Damit ist bereits eine gewisse Bruchsicherheit gewährleistet. Die Strukturen der Halbleiterbauelemente der integrierten Schaltung selbst können dann mit ihren geradlinigen oder ebenen Strukturen parallel bzw. coplanar zu den Hauptkristallebenen des Halbleiterkristalls oder Substrates ausgerichtet sein. Bei einer bevorzugten Ausgestaltung sind jedoch auch diese Strukturen der Bauelemente selbst gegenüber den Hauptkristallebenen in einem Winkel von mehr als 0° und weniger als 90° ausgerichtet.The conductor tracks of the chips of the semiconductor chip stack are each oriented at different angles to the main crystal planes. This already ensures a certain level of break resistance. The structures of the semiconductor components of the integrated circuit itself can then, with their rectilinear or planar structures, be parallel or coplanar with the main crystal planes of the semiconductor crystal or substrate be aligned. In a preferred embodiment, however, these structures of the components themselves are oriented at an angle of more than 0 ° and less than 90 ° with respect to the main crystal planes.
Das hat insbesondere den Vorteil, dass in diesem Fall die Leiterbahnen mit ihren beiden wesentlichen Richtungen außerhalb der senkrechten Hauptkristallebenen liegen, aber nach wie vor parallel zu den Strukturen der Halbleiterbauelemente ausgerichtet sein können. Bei einer speziellen und bevorzugten Ausgestaltung des Halbleiterchipstapels können die Halbleiterchips des Halbleiterchipstapels untereinander so ausgerichtet sein, dass die Leiterbahnen der verschiedenen Halbleiterchips in Winkeln von 0° bzw. 90° zueinander angeordnet sind, wie das auch bei herkömmlichen Chipstapeln der Fall ist.This has the particular advantage that in this case the conductor tracks with their two essential directions lie outside the vertical main crystal planes, but can still be aligned parallel to the structures of the semiconductor components. In a special and preferred embodiment of the semiconductor chip stack, the semiconductor chips of the semiconductor chip stack can be aligned with one another in such a way that the conductor tracks of the different semiconductor chips are arranged at angles of 0 ° or 90 ° to one another, as is also the case with conventional chip stacks.
Wegen der jeweils unterschiedlichen Ausrichtung der Leiterbahnen zu den Hauptkristallebenen der einzelnen Substrate sind innerhalb des Halbleiterchipstapels von Chip zu Chip wechselnde Ausrichtungen der Hauptkristallebenen vorhanden. Senkrecht zu den Oberseiten der Chips, d. h. senkrecht zu den {1, 0, 0}-Ebenen, ist daher keine durch den gesamten Halbleiterchipstapel hindurchgehende einheitliche Hauptkristallebene vorhanden. Dadurch wird die Bruchsicherheit des Halbleiterchipstapels deutlich erhöht. Ein solcher Halbleiterchipstapel kann daher auch mit drei und mehr Halbleiterchips auf eine Dicke von höchstens 185 μm gebracht werden, was den Einsatz in standardisierten Chipkarten erlaubt. In dem Ausführungs- beispiel der Figur 2 ist der Halbleiterchip 1 zum Beispiel 130 μm dick, der erste weitere Halbleiterchip 11 ist 30 μm dick, und der zweite weitere Halbleiterchip 12 ist 20 μm dick. BezugszeichenlisteBecause of the different orientation of the conductor tracks to the main crystal planes of the individual substrates, orientations of the main crystal planes which change from chip to chip are present within the semiconductor chip stack. Perpendicular to the tops of the chips, ie perpendicular to the {1, 0, 0} planes, there is therefore no uniform main crystal plane passing through the entire semiconductor chip stack. This significantly increases the break resistance of the semiconductor chip stack. Such a semiconductor chip stack can therefore also be brought to a thickness of at most 185 μm with three and more semiconductor chips, which allows use in standardized chip cards. In the exemplary embodiment in FIG. 2, the semiconductor chip 1 is, for example, 130 μm thick, the first further semiconductor chip 11 is 30 μm thick, and the second further semiconductor chip 12 is 20 μm thick. LIST OF REFERENCE NUMBERS
1 Halbleiterchip 2 Leiterbahn1 semiconductor chip 2 conductor track
3 Oberseite3 top
4 Chipkante4 chip edge
5 Chipkante5 chip edge
6 Winkel 7 Supplementwinkel6 angles 7 supplement angles
11 erster weiterer Halbleiterchip11 first further semiconductor chip
12 zweiter weiterer Halbleiterchip A Richtung12 second further semiconductor chip A direction
B Richtung B direction

Claims

Patentansprüche claims
1. Halbleiterchipstapel mit mindestens einem Halbleiterkristall oder einem Substrat aus kristallinem Silizium mit Äquivalenzklassen von Hauptebenen des Kristalls, die mit den Miller-Indizes {1,0,0}, {0,1,0} und {0,0,1} bezeichnet werden, wobei eine Oberseite des Halbleiterkristalls oder Substrates durch eine (1,0,0)- Ebene gebildet wird, mit einer integrierten Schaltung und mit metallischen Leiterbahnen, die an der durch die (1,0,0)- Ebene gebildeten Oberseite im Wesentlichen längs zweier zueinander senkrechter Richtungen ausgerichtet sind, d a d u r c h g e k e n n z e i c h n e t , dass die Richtungen der Leiterbahnen eines betreffenden Halbleiterkristalls oder Substrates mit den { 0, 1, 0}-Ebenen und den {0, 0, 1}-Ebenen Winkel von mindestens 10° einschließen.1. Semiconductor chip stack with at least one semiconductor crystal or a substrate made of crystalline silicon with equivalent classes of main planes of the crystal, which are denoted by the Miller indices {1,0,0}, {0,1,0} and {0,0,1} , wherein an upper side of the semiconductor crystal or substrate is formed by a (1,0,0) plane, with an integrated circuit and with metallic conductor tracks, which are essentially on the upper side formed by the (1,0,0) plane are aligned along two mutually perpendicular directions, characterized in that the directions of the conductor tracks of a relevant semiconductor crystal or substrate with the {0, 1, 0} planes and the {0, 0, 1} planes include angles of at least 10 °.
2. Halbleiterchipstapel nach Anspruch 1, bei dem geradlinige und ebene Strukturen von Bauelementen der integrierten Schaltung in dem betreffenden Halbleiterkristall oder Substrat ebenfalls Winkel von mindestens 10° mit den {0, 1, 0}-Ebenen und den {0, 0, 1}-Ebenen einschließen.2. The semiconductor chip stack as claimed in claim 1, in which straight-line and planar structures of components of the integrated circuit in the semiconductor crystal or substrate in question likewise have angles of at least 10 ° with the {0, 1, 0} planes and the {0, 0, 1} - Include layers.
3. Halbleiterchipstapel, bei dem3. Semiconductor chip stack, in which
Halbleiterchips mit einem Halbleiterkristall oder Substrat aus kristallinem Silizium mit Äquivalenzklassen von Hauptebenen des Kristalls, die mit den Miller-Indizes {1,0,0}, {0,1,0} und {0,0,1} bezeichnet werden, mit Oberseiten, die jeweils coplanar zu den {1, 0, 0}-Ebenen des Halbleiterkristalls oder Substrates sind, dauerhaft aneinander befestigt sind und die Halbleiterkristalle beziehungsweise Substrate so zueinander ausgerichtet sind, dass die { 0, 1, 0} -Ebenen beZiehungswei- se die { 0, 0, 1 } -Ebenen der Halbleiterkristalle beziehungsweise der Substrate aufeinanderfolgender Halbleiterchips jeweils in einem von 0° und 90° verschiedenen Winkel zueinander angeordnet sind.Semiconductor chips with a semiconductor crystal or substrate made of crystalline silicon with equivalent classes of main planes of the crystal, which are denoted by the Miller indices {1,0,0}, {0,1,0} and {0,0,1}, with top sides , which are each coplanar with the {1, 0, 0} planes of the semiconductor crystal or substrate, are permanently attached to one another and the semiconductor crystals or substrates are aligned with one another in such a way that the {0, 1, 0} planes relate to the {0, 0, 1} planes of the semiconductor crystals or the substrates of successive semiconductor chips in each case in are arranged at an angle different from 0 ° and 90 ° to one another.
4. Halbleiterchipstapel nach Anspruch 1 oder 2, bei dem mindestens ein weiterer Halbleiterkristall oder ein weiteres Substrat aus kristallinem Silizium vorhanden ist mit metallischen Leiterbahnen, die an einer durch eine (1, 0, 0) -Ebene gebildeten Oberseite im Wesentlichen längs zweier zueinander senkrechter Richtungen ausgerichtet sind, die mit den { 0, 1, 0} -Ebenen und den { 0, 0, 1 }-Ebenen des weiteren Halbleiterkristalls beziehungsweise Substrates Winkel von mindestens 10° einschließen, mit den Halbleiterkristallen beziehungsweise Substraten gebildete Halbleiterchips mit Oberseiten, die jeweils coplanar zu den {1, 0, 0}-Ebenen der Halbleiterkristalle beziehungsweise Substrate liegen, dauerhaft aneinander befestigt sind, die Halbleiterkristalle beziehungsweise Substrate so zueinander ausgerichtet sind, dass die Richtungen von Abschnitten der Leiterbahnen der verschiedenen Halbleiterkristalle bezie- hungsweise Substrate jeweils in einem Winkel von 0° oder 90° zueinander angeordnet sind, und die Winkel zwischen den Richtungen von Abschnitten der Leiterbahnen und den {0, 1, 0}-Ebenen bzw. den {0, 0, 1 }-Ebenen des betreffenden Halbleiterkristalls beziehungsweise Substrates für die vorhandenen Halbleiterkristalle beziehungsweise Substrate jeweils verschieden sind.4. The semiconductor chip stack as claimed in claim 1 or 2, in which at least one further semiconductor crystal or a further substrate made of crystalline silicon is present with metallic conductor tracks which on an upper side formed by a (1, 0, 0) plane essentially along two perpendicular to one another Directions are aligned which include angles of at least 10 ° with the {0, 1, 0} planes and the {0, 0, 1} planes of the further semiconductor crystal or substrate, with semiconductor chips formed with the semiconductor crystals or substrates with top sides which are each coplanar to the {1, 0, 0} planes of the semiconductor crystals or substrates, are permanently attached to one another, the semiconductor crystals or substrates are aligned with respect to one another such that the directions of sections of the conductor tracks of the different semiconductor crystals or substrates are each in one Angle of 0 ° or 90 ° to each other rdnet, and the angles between the directions of sections of the conductor tracks and the {0, 1, 0} planes or the {0, 0, 1} planes of the relevant semiconductor crystal or substrate are each different for the semiconductor crystals or substrates present ,
5. Halbleiterchipstapel nach einem der Ansprüche 1 bis 4, bei dem die gesamte Dicke höchstens 185 μm beträgt.5. Semiconductor chip stack according to one of claims 1 to 4, wherein the total thickness is at most 185 microns.
6. Halbleiterchipstapel nach Anspruch 5, der mehr als zwei Halbleiterchips enthält, wobei mindestens ein Halbleiterchip höchstens 20 μm dick ist. 6. The semiconductor chip stack according to claim 5, which contains more than two semiconductor chips, at least one semiconductor chip being at most 20 μm thick.
PCT/DE2003/003057 2002-09-24 2003-09-15 Semiconductor chip on which conductor tracks on a (1,0,0) crystal plane form an angle of at least ten degrees with the (0,1,0) and (0,0,1) crystal planes in order to increase the fracture resistance WO2004030092A1 (en)

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TWI242280B (en) 2005-10-21
TW200405538A (en) 2004-04-01
DE10244446B4 (en) 2004-08-19

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