TW200405538A - Semiconductor chip stack - Google Patents

Abstract

Semiconductor chips 1 or semiconductor chip stacks which have been thinned for use in chip cards have arrangements of the directions (A, B) of sections of the interconnects (2) on a (1, 0, 0) top side which include angles (6, 7) of at least 10 DEG with the {0, 1, 0} planes and the {0, 0, 1} planes of the silicon crystal, in order to increase the resistance to breaking.

Description

200405538 V. Description of the invention (1) The present invention relates to a semiconductor wafer stack with integrated circuits used in a chip card. Within wafer cards, and e.g. electronic mail sorting systems, IC wafers are subject to considerable bending. Many wafers have sufficient mechanical stability values for these loads. If these wafers are incorporated in a stable housing, this will inevitably result in an increase in overall thickness. In the field of chip cards, the thickness of the chip is limited to 1 8 5 // m. The surface of this wafer is limited to a maximum of 25 mm2 in this case to reduce the risk of breakage. Due to the limitation of the maximum allowable thickness, in order to combine two layers of wafers and stack them in a chip card, the smaller wafers must be thinned to 60 / m. In the future, wafer stacks with more than two layers will be used, and their wafers must even be thinner than 20 / z m. Wafers that have been thinned to such an extent have far lower mechanical stability than thicker wafers, and the edges of the wafers are susceptible to groove breaks, and these breaks may spread throughout the wafer. This problem is mainly due to the fact that the crystalline silicon of the wafer substrate features must lie exactly along the main plane of the crystal lattice. The position of the main plane of the silicon lattice (diamond structure) is determined by the corresponding equivalent classification of the Miller index (M i 1 1 er indices) {l, 0, 0}, {0, 1,}, {0, 0,1} given. In the case of a 6-inch wafer made of (1,0,0) material, the upper main surface of the wafer is a (1,0,0) surface. Other major surfaces of the same kind perpendicular to it are therefore perpendicular to each other and perpendicular to the upper major sides of the wafer. This fact is used to prepare the desired break point in the wafer. For this purpose, small scratches are generated at the edges of the silicon wafer that are treated as a crack and thus cause a groove break. When the wafer is bent, the fracture passes through the entire wafer from this position. In this way, crystal

Page 4 200405538 V. Description of the invention (2) The circle can be divided into independent semiconductor wafers. The wafer surrounded by the scratch line is usually the main point on the wafer that is applied to the upper intersection or similar with the semiconductor structure inside the integrated circuit, the groove for the electrical character separation or the formation of the memory cell transistor, or the like. The way is set. These structural elements therefore increase the risk of semiconductor wafer breakage. This is especially true in the case of semiconductor wafers that are thinned to the south. This problem occurs more if a plurality of semiconductor wafers are stacked vertically or cubely to form a semiconductor wafer stack. In the case of vertical accumulation, the chips must be grounded until they are particularly thin, especially if they are intended to be used in thin chip cards. If this vertically integrated crystal wafer is produced in a conventional manner, the tendency to fracture continues to increase to the extent that it passes through the entire wafer stack. It is an object of the present invention to describe thinned wafers, especially vertical accumulations, and fractures can be reduced so that they can be used in the field of wafer cards. This object is achieved by a semiconductor wafer or a stack of semiconductor wafers having the features of the scope of claims 1 or 3 of the patent application. The structure will be generated from the scope of the patent application. As in the past, it is still possible to use a substrate from a crystalline silicon having a (1,0,0) crystal plane as the upper side. The integrated circuit is connected to each other by the metal on the upper side. The Φ connection is substantially perpendicular to each other and includes two directions at least 10 ° from the {0, 1, 0} plane and the {0, 0, 1} plane. Therefore, if the interconnections are inclined across the main crystal plane, they have a mechanically stable action. In addition, the metal interconnects are polycrystalline silicon or amorphous, and therefore can be within certain limits

Page 5 200405538 V. Description of the invention (3) Deformed or stretched. They therefore have an additional mechanical strengthening performance, comparable to the fibers in textile-reinforced synthetics. In addition, the straight and plane structures of the integrated circuit elements in the crystal may also include an angle of at least 10 ° with the {0, 1, 0} plane and the {0, 0, 1} plane. For this purpose, during the manufacture of a semiconductor wafer, the components on the wafer are oriented at an angle, preferably between 15 ° and 45 °, relative to the main crystal plane on the vertical side of the wafer. Due to this orientation, the edges created during structuring do not have the effect of a crack initiation. Because the structure of the semiconductor element is defined by the optical lithography used during the manufacturing process, in order to produce a semiconductor wafer of the present invention, in principle, during the exposure process, the wafer is rotated in a position rotated through a predetermined angle. It is sufficient to insert into the stepper (that is, to be flat or the grooves do not face downward or to the side, but are rotated through 15 ° to 45 °). All other process steps can remain essentially the same. In this way, the wafer arrangement on the wafer is rotated compared to conventional processes and the sawtooth table is inclined relative to the device. This does not cause any changes in the design and conduction of the semiconductor wafer itself, and the internal structure of the semiconductor element can be especially parallel to the edge of the wafer as before, because there is no need to saw the latter parallel to a main crystal plane. In a semiconductor wafer stack according to the present invention, the main crystals that form the individual circuit planes that are perpendicular to the circuit planes of the consecutive semiconductor wafers are oriented in a direction that includes angles other than 0 ° and 90 °. Set, and preferably, include a different angle in each case. Because in each case the successively arranged circuit planes of one on top of the other are connected together by common metallization as one of the interfaces. This is sufficient if two

Page 6 200405538 5. Description of the invention (4) At least one of the continuous semiconductor wafers forms an angle other than 0 ° and 90 ° with respect to the main crystal plane of the vertical semiconductor wafer. If a semiconductor wafer formed in this manner is placed over the other to form a semiconductor wafer stack and is electrically connected to each other via metallization, the main crystal plane of the vertical circuit plane becomes at an angle other than 0 ° and 90 °, and No further measurements are required. In another embodiment, only semiconductor wafers that are substantially resistant to fracture due to the above directions of interconnection are connected to each other. If the interconnections of at least some of the semiconductor wafers of the semiconductor stack are inclined with respect to the main crystal plane, but the sides of the wafer and the wafer edges are sawed in all semiconductor wafers parallel to the interconnection cross-section, these sides may correspond to each other on the same plane. Oriented in the way. This results in a wafer stack with a planar boundary, in which the layers of the main crystal plane perpendicular to the circuit plane are different from each other in the individual circuit planes. The main crystal planes located on the plane of the vertical layer mutually form angles other than 0 ° and 90 ° on each wafer, even in the case of a semiconductor wafer having a plane boundary. A detailed description of an embodiment of a semiconductor wafer or semiconductor wafer stack will now be made with reference to Figs. Fig. 1 shows a plan view of a semiconductor wafer having interconnects 2 applied to the upper side. These interconnections are essentially oriented in two perpendicular directions in this example. The interconnected sections are arranged in direction A or B, which are located at mutually perpendicular angles in FIG. The {1,0,0} plane of the upper side of the semiconductor wafer shown in Fig. 1 with respect to the corresponding substrate or semiconductor crystal is coplanar. In the conventional semiconductor wafer, the wafer edges 4, 5 are a {0,1,0} plane or a {0,0,1} plane. Conversely, in this example, the {0,1,0} plane or the {0,0,1} plane

Page 7 200405538 V. Description of the invention (5) In each case it extends, for example, in the direction indicated by one of the two arrows shown. However, the wafer edges 4, 5 are mined parallel to the interconnections. Alternatively, the edge of the side wafer may be set in a direction indicated by an arrow and a direction perpendicular to the edge. In this example, these interconnects are inclined relative to the wafer edge. The angle 6 shown in Figure 1 between the direction B of the horizontal interconnected section of Figure 1 and one of the main crystal directions indicated by the arrow on the right, or the supplementary angle 7 related to angle 6, is between 10 ° and 80 °. Between, preferably between 15 ° and 75 °. In the embodiment shown in FIG. 1, the angle 6 is 67.5 °. The two directions indicated by the arrows shown form a 45 ° angle with each other. If, in the case of a semiconductor wafer stack including two semiconductor wafers, the main crystal plane of the semiconductor crystal or substrate is at an angle of 45 ° relative to one another in this example, Directions A and B. In the case of vertical accumulation, the semiconductor wafers are connected to each other by their individual parallel metallizations in such a way that the main crystal plane of the wafer is oriented relative to each other, and in this way, Mutual stability. In this example, the wafer edges 4, 5 are parallel to each other, and the cross-section of the wafer 2 is vertical. The main crystal plane of the vertical circuit plane of the wafer includes an angle of 4 5 ° with each other and the corresponding metallization of the corresponding wafer 2. 5 or 6 7.5 ° angle. Fig. 2 shows a cross section of an embodiment of a semiconductor wafer stack, in which a first other wafer 11 and a second other wafer 12 are arranged in a lower semiconductor wafer 1. These semiconductor wafers are interconnected by their upper sides 3, which are coplanar with the {1, 0, 0} plane of the substrate or semiconductor crystal. In the simplified description shown in Figure 2, the metallization of the structures between the semiconductor wafers is omitted.

Page 8 200405538 5. Description of the invention (6) According to the present invention, the wafer edges 4, 5 are not on the side of the cross section shown in FIG. 2 or in the plane of the figure with other main crystal planes {0, 1, 0} Consistent with {0,0,1}. Conversely, the wafer edges face different angles with respect to these main crystal faces. Therefore, the wafers can be overlapped with each other under the edge conformation. Therefore, two continuous semiconductor wafers, preferably paired semiconductor wafers, which are located on the vertical upper side 3 and the main crystal planes are not at an angle of 0 ° or 9 0 to each other °. The main crystal plane perpendicular to the semiconductor wafer 1 may, for example, form an angle of 5 5 ° with one of the main crystal planes perpendicular to the upper side 3 of the first other wafer 1 1. The main crystal plane perpendicular to the upper side 3 of the first other wafer 1 1 may, for example, form an angle of 17 ° with one main crystal plane perpendicular to the upper side 3 of the second other semiconductor wafer 12. This result also caused a 55. -17 ° = 38 ° or 55 ° + 17 ° = 72 °, so different from other angles 55 ° and 17 °, it appears on the corresponding main crystal plane of the lower semiconductor wafer 1 and the second other semiconductor wafer 1 2 Between the main crystal planes. Therefore, in this example, not only the angles between the corresponding principal crystal planes of two consecutive pairs of semiconductor wafers, but also the angles between the principal planes of any two crystal pairs are different from each other. The interconnections of the stacked semiconductor wafers are oriented at different angles with respect to the main crystal plane. This has provided specific resistance to fracture. The structure of the semiconductor element itself of the integrated circuit can then be parallel to its linear or planar structure or coplanar with the main crystal plane of the semiconductor crystal or substrate. However, in a more preferred embodiment, the structure of these elements is also oriented at an angle greater than 0 ° and less than 90 ° with respect to the main crystal plane. There is a surplus in the case where the two main directions of interconnection are outside the vertical main crystal plane but still parallel to the semiconductor element as before. in

200405538 V. Description of the invention (7) In a specific and preferred semiconductor wafer stack, the direction of the semiconductor wafers of the semiconductor wafer stack can be set between 0 ° and 9 0 ° with respect to the interconnection of different conductor wafers. The settings are set as in the conventional way of stacking wafers. Because of the different directions of the interconnections with respect to the main crystal plane of the individual substrates, the direction of the main crystal plane that varies from wafer to wafer appears in a semiconductor wafer stack. Therefore, perpendicular to the upper side of the wafer and also perpendicular to the {1,0,0} plane, there is no uniform main crystal plane continuously passing through the entire semiconductor wafer stack. This greatly increases the resistance of the semiconductor wafer stack to fracture. Therefore, this type of semiconductor wafer stack can be applied up to a thickness of 1 8 5 // m, even with three or more semiconductor wafers, allowing them to be used in standard wafer cards. In the embodiment shown in FIG. 2, the semiconductor wafer 1 is, for example, 130 // m thick, the first other semiconductor wafer 11 is 30 // m thick and the second other semiconductor wafer 12 is 20 // m thick. 200405538 Brief Description of Drawings Figure 1 shows a plan view of a semiconductor wafer. The second diagram is a cross-sectional view not passing through the semiconductor wafer. Description of component symbols: 1 semiconductor wafer 2 interconnected 3 upper side 4, 5 wafer edge 6 angle 7 fillet 11 first another semiconductor wafer 12 second another semiconductor wafer A'B direction ««

Page 11

Claims (1)

200405538 VI. Application Patent Scope 1. A semiconductor wafer stack with at least one semiconductor crystal or a substrate made of crystalline silicon of the same type as the main crystal plane, and the main crystal planes are determined by Miller indices. ) {l, 0,0}, {0, 1,0}, {0 ·, 0,1} indicate that the upper side of one of the semiconductor crystals or substrates is formed by a (1,0,0) plane, It has an integrated circuit and an interconnection with a metal located on the upper side of the 0,0,0) plane formation, which substantially faces two mutually perpendicular directions, among which a corresponding semiconductor crystal or a substrate of the interconnected The direction includes an angle of at least 10 ° with the {0,1,0} plane and the {0,0,1} plane. 2. If the semiconductor wafer stack of item 1 of the patent application scope, wherein the linear and planar structures of the components corresponding to the semiconductor crystal or the integrated circuit in the substrate also include the {0,1,0} plane and the {0,0, The 1} faces form an angle of at least 10 °. 3. A semiconductor wafer stack in which semiconductor wafers are permanently bonded to each other, the semiconductor wafers have at least one semiconductor crystal or a substrate made of crystalline silicon of the same type as the main crystal plane, and the main crystal planes are As indicated by the Miller index (M i 1 1 er indices) {1, 0, 0}, {0, 1, 0}, {0, 0, 1}, the {1, The upper side of the 0,0} plane coplanar plane, and the direction between the semiconductor crystals or substrates is the {0,1,0} plane or {0,0,1} plane of the semiconductor crystal or substrate of the consecutive semiconductor wafer It is set to form an angle other than 0 ° and 90 °. 4. If the semiconductor wafer stack of the patent application scope item 1 or 2, Page 12 200405538 6. The scope of the patent application presents at least one other semiconductor crystal or another substrate made of crystalline silicon, with the upper side of one formed from a (1, 0, 0) surface substantially facing each other. Metals in two directions are connected to each other, and they include an angle of at least 10 ° relative to the {0,1,0} plane and the {0,0,1} plane with respect to the other semiconductor crystal or substrate. Permanently bonded to each other, which is formed using the semiconductor crystal or substrate and has an upper side that is coplanar with the {1,0,0} plane of the semiconductor crystal or substrate, and the direction of the semiconductor crystal or substrate is different from that of the semiconductor. The directions of the mutually connected cross sections of crystals or substrates are set in 4 ways of 0 ° or 90 °, and the directions of the cross sections of these interconnections and the {0,1 The angle between the 0} plane or the {0,0,1} plane is different in the case of different semiconductor crystals or substrates. 5. For a semiconductor wafer stack according to any of claims 1 to 4, the total thickness is at most 1 8 5 // m. 6. If the semiconductor wafer stack of item 5 of the patent application includes more than two semiconductor wafers', at least one semiconductor wafer is at most 20 // m thick.