TW445599B - Multi-chip stacked package structure - Google Patents

Abstract

This invention is about a kind of multi-chip stacked package structure. A multi-chip module substrate is provided. A first chip is adhered to the multi-chip module substrate. The bonding face of the first chip has a central region and plural bonding pads, which are located at the periphery of the central region. A second chip is adhered on the bonding face of the first chip and the bottom face of the second chip has an outer tier and a central tier, in which the central tier of the second chip has a thickness and a periphery. The periphery of the central tier is completely located and adhered inside the central region of the first chip. A plurality of first connecting wires are used to electrically connect each bonding pad of the first chip with the multi-chip module substrate. The first connecting wire defines a loop height. The central tier thickness of the second chip is larger than the loop height of the first connecting wire such that the second chip and the first connecting wire can be stacked on the bonding face of the first chip through the use of a non-contacting manner. A plurality of second connecting wires are used to electrically connect each bonding pad of the second chip with the multi-chip module substrate.

Description

445599

89in〇7 ^ Q V. Description of the invention (1)-^^ 月 日 — 条 正 _ [Field of the invention] The present invention relates to a module (MCM), a package structure for multi-day sun-chips (multi- About a chip-stacked multi-chip package structure [Previous technology]: As electronic products become more and more private — and they provide external circuits ^ = thin and short, it is used to protect semiconductors from crystallizing. The packaging structure of the connection also requires Lightweight, thin and short build m :: and the increase of high operating speed requirements, the multi-chip package structure will become more and more attractive. The multi-chip package structure can be combined in a single package structure by transporting more than your chips. In order to minimize the limitation of the system. In addition, the multi-chip package structure can reduce the length of the flail circuit and reduce the signal delay and access time. The most common multi-chip package structure is a side-by-side "丨 ^ 一心" "... Multi-chip package structure 'is the installation of two or more wafers side by side on the main women's side of a substrate. The connection between the wafer and the conductive lines on the common substrate is generally by wire bonding. wi re bond i ng). However, the disadvantage of the side-by-side multi-chip package structure is that the packaging efficiency is too low, because the area of the common substrate will increase with the increase in the number of chips. Therefore, US Patent No. 5 3 2 3 0 No. 60 discloses a multichip stacked device including a first semiconductor wafer 110 disposed on a substrate 120 and electrically connected to the substrate 120, and a second semiconductor wafer 130 stacked on the first semiconductor wafer. And is electrically connected to the substrate (see Fig. La). Features of this US Patent No. 5323060

P00 ~ 048 ~ amend.ptc Page 4 445599 _Case No. 89109786 _Year Month Date __ V. Description of the invention (2) It is to use a glue layer 1 4 〇 provided between two wafers to provide the wire arc. (The loops of the bonding wires). And the thickness of the adhesive layer 140 must be greater than the arc height of the bonding wire. This refers to the distance between the front surface of the wafer 1 1 0 and the vertex of the arc of the welding line 150-to avoid the wafer 1 3 0 from touching Line arc of welding wire 1 50. Conventionally, the wire bonding technology for forming a wire interconnection between a wafer pad and a substrate pad generally includes (a) a baU bond on a wafer bonding pad, and (b) forming a wire arc on the wafer bonding. The bonding wire connection is completed between the pad and the substrate pad and (c) a stitch bond to the substrate pad. Generally, the arc height is about 10 to 15 mils (m 丨 1). Although by adjusting the parameters, shape and type of the arc, the conventional arcing technique can reduce the arc height to about 6 mils (m i 1). However, this is already the minimum arc height available, because a lower value will damage the wire and make its tension worse. Therefore, when using conventional wire bonding technology, the thickness of the adhesive layer must be greater than 8 Å; to prevent the wafer 1 3 from contacting the wire arc of the bonding wire 1 &0; The material of the adhesive layer 140 is generally epoxy adhesive or tape. However, it is very difficult to form an epoxy adhesive layer having a thickness of 8 mils. In addition, when using a tape with a thickness of 8 mils, on the one hand, it will greatly increase the manufacturing cost; on the other hand, the thermal expansion coefficient between the adhesive layer 140 and the silicon wafer is inconsistent, and the package produced will be seriously damaged. Structural Reliability Therefore, U.S. Patent No. 6 00 5778 discloses another multichip stacked device, which includes a first semiconductor device 110 disposed on a substrate 120 and electrically connected to the substrate 120, and a The second semiconductor wafer 130 is stacked on the first semiconductor wafer and is electrically connected =

445599 V. Description of the invention (3) Case number 89109786

B Correct to the base plate (see Figure lb). The feature of this U.S. Patent No. 60005778 is to use the spacer 16 Q between the two wafers to provide the space required for the loops of the bonding wires ( clearance). In addition, a spacer 160 made of a metal conductive material can also be used as a ground plane for semiconductor wafers, and women's clothing that provides capacitors. Although the spacer of US Patent No. 6005 7 78 and (spaCer) 160 have solved the lack of the aforementioned adhesive layer 14 of US Patent No. 532 3060, an additional spacer element needs to be added in more In the chip package structure, the manufacturing cost of the multi-chip package structure is also virtually increased. [Summary]: The main purpose of the present invention is to provide a multi-chip stacked package structure, which includes two chips stacked on a multi-chip module substrate, wherein the bottom mask of the upper chip has an external step layer (〇uter Uer) and a central tier. The central tier provides the space required for the loops of the bonding wires to prevent the upper wafer from contacting the wire arcs of the lower wafer. A secondary object of the present invention is to provide a method for manufacturing a multi-chip stacked package structure, in which two chips are stacked on a multi-chip module substrate, wherein the bottom mask of the upper chip has an outer step layer (〇uter tier). ) And a central step layer (centra 1 tier), which provides the space required for the loops of the bonding wires to prevent the upper chip from contacting the wire arc of the lower chip. To achieve the above object, a multi-chip stacked package structure according to a preferred embodiment of the present invention includes a multi-chip module base and

POO-048-araend. Ptc Page 6 445599 Case No. 89109786 Λ_η Modification V. Description of Invention (4) A plate, a first wafer, having a bonding face and a base face opposite to each other, the first The bottom surface of the wafer is adhered to the multi-chip module substrate. The first wafer bonding mask has a central area and a plurality of bonding pads are located around the central area. A second wafer has opposite bonding faces and a bottom surface ( base face), the second wafer bottom surface is adhered to the first wafer bonding surface, the second wafer bonding mask has a central region and a plurality of bonding pads are located around the central region, and the second wafer bottom mask has an outer step layer ( outer tier) and a central tier. The central tier of the second chip has a thickness and a periphery. The periphery of the central tier is completely located and adhered to the central region of the first chip. A connection line electrically connects the individual bonding pads of the first chip with the multi-chip module substrate. The first connection line defines an arc height (100p he 1 ghj :) of the first chip. The distance between the surface and the apex of the connecting line line. The thickness of the central stepped layer of the second chip is greater than the arc of the first connecting line. And a plurality of second connecting wires electrically connect the individual pads of the second chip to the multi-chip module substrate. List of steps for manufacturing a multi-chip stacked package structure in a preferred embodiment: provide-a multi-chip module substrate; adhesion-a human face r: η: "Xi chip module substrate, the first chip has opposite connection and bottom surface (base face), the first-wafer encirclement · i-type connection,: f-domain and a plurality of joints Tan Ying is located in the middle of the central area and ^ sheet ^ between the substrate-the first connection line definition-arc height (10〇Ρ

445599 __Case No. 89109786_ Year, Month, and Day ___ V. Description of the invention (5) he i ght) —refers to the distance between the joint surface of the first chip and the apex of the connecting line arc; a second chip is adhered to the On the first wafer, the second wafer has opposite bonding faces and base faces. The second wafer bonding mask has a central region and a plurality of bonding pads located around the central region. The second wafer The bottom mask has an outer tier and a centra 1 tier. The central tier of the second wafer has a thickness and a periphery. The periphery of the central tier is completely located and adhered to the first wafer. In the central region, the thickness of the central stepped layer of the second wafer is greater than the arc south of the first connection line, so that the bottom surface of the second wafer and the first connection line are stacked in a non-contact manner on the bonding surface of the first wafer; The plurality of second connecting wires are connected between the individual bonding pads of the second chip and the multi-chip module substrate. According to the present invention, the second wafer is made in the following manner. First, a wafer is fixed on a workbench 'so that the back side of the wafer faces upward and the front side faces downward. The wafer is mechanically ground with a grinding wheel parallel to the back of the wafer. When grinding the second wafer, the wafer is first ground to a predetermined first thickness, which is about 4 to 20 mils. Then, the wafer is cut along a wafer cutting line of the polished wafer with a thick dicing knife to form a groove having a depth of about _mil and a width of about 6__8 mil. The slotted wafer is then cut into individual second wafers with a thin dicing knife, such as a diamond knife. Therefore, an outer tier 'and a central Uer are formed on the bottom surface of the second wafer. The central tier has a thickness T of about 8-10 mils, so that the second wafer must be connected to the first wafer. The wires are stacked on the bonding surface of the first wafer in a non-contact manner. Therefore, in the present invention, two chips can be mounted on a multi-chip module in a stacked manner.

P00-048-amend.ptc Page 8 445599 Revision Year Month

B.1 ^ 89109786 V. Description of the invention (6) Substrate 'so that the bottom of the upper wafer does not touch the arc of the bonding wire of the lower wafer at all' and overcome the defects of the aforementioned U.S. Patent Nos. 5,323,060 and 6005778. In order to make the above and other objects, features, and advantages of the present invention more apparent, the preferred embodiments of the present invention will be described in detail below, in conjunction with the accompanying drawings, as follows. [Explanation of the Invention]: Please refer to FIGS. 6 and 7, which are cross-sectional views of the multi-chip stacked package structure of the present invention. According to the multi-chip stacked package structure of the present invention, a first chip 210 has a bonding face 212 and a base face 214 opposite to each other. The bottom surface 214 of the first chip 210 is adhered to a multi-chip module substrate 220 by an adhesive layer 222, such as an epoxy 'tape or a thermoplastic adhesive layer. The bonding surface 212 of the first wafer 210 has a central region 218 and a plurality of bonding pads 216 are located around the central region 218. A second wafer 230 has a bonding face 232 and a base face 234 opposite to each other. The bottom surface 234 is adhered to the central region 218 of the bonding surface 2 j 2 of the first wafer 2 through an adhesive layer 240, such as an adhesive layer of epoxy resin, tape, or thermoplastic. The bonding surface 232 of the second wafer 230 has a central region 238 and a plurality of bonding pads 236 are located around the central region 238. According to the multi-chip stacked package structure of the present invention, at least two sides of the second wafer 2 30 bottom surface 2 34 are formed by an outer tier 234a and a central tier by chemical etching or mechanical cutting.

tier) 234b 'The central stepped layer 234b of the second wafer 230 has a thickness T and a periphery. The periphery of the central stepped layer 234b is completely located and adhered to the central region 218 of the first wafer. The plurality of first connecting lines 2 50

Page 9 445599

The individual bonding pads 216 of the chip 210 are electrically connected to the multi-chip module substrate 220. The plurality of second connecting wires 260 electrically connect the individual bonding pads of the second chip 23o to the multi-chip module substrate 22o. The first connecting line 25 defines a loop height H—referring to the distance between the connecting surface 21 2 of the first wafer 210 and the connecting line 2 50 line vertex 2 5 2. The central stepped layer of the second wafer 2 3 0 (〇6111 ^ 3 11: 丨 61〇23413 has a thickness] [must be greater than the arc height of the first connection line 25 0, so that the second wafer 23 0 can be connected to the first Lines 250 are stacked on the contact surface 2 12 of the first wafer 210 in a non-contact manner. According to one embodiment of the multi-chip stacked package structure of the present invention, the central tier of the second wafer 2 300 ) The thickness of 234b is about 8-10 mils, and the arc height of the first connection line 250 is about 6 mils. Therefore, the thickness T of the central wafer 234b of the second wafer 2 30 is T The second wafer 23 0 and the first connecting wire 2 50 are stacked on the joint surface 2 i 2 of the first wafer 2 in a non-contact manner on 0. Referring to FIGS. 2 to 5, it discloses the second wafer of the present invention. The manufacturing flow chart of 2 3 0. Please refer to FIG. 2. First, a wafer 200 is fixed on a workbench 10 with an adhesive layer 20 so that the back surface 2 0 of the wafer 2 0 2 faces upward. The front surface 202 of the wafer 2000 is in contact with the adhesive layer 20, and the front surface 200 of the wafer 2000 has a plurality of bonding pads 216. Please refer to FIG. 3, and a polishing wheel 30 flat On the back of the wafer, ο mechanically grind the δ black wafer 2000. Generally, wafer waste wafer 2000 has a thickness of about 200 to 25 mils (mi 1), and the wafer must be ground. Up to $ si 〇mil (mi 丨) thickness, and then use a diamond knife to cut into the required wafer, and then package. The first wafer 2 1 0 is to directly grind the wafer to 6 to 0 mil (m ± 丨) 'S thickness, then

P00-048-amend. Ptc Page 10 445599 — ___Case No. 89109786 __Amendment _ V. Description of the invention (8) Use a diamond knife to cut the required wafer. When grinding the second wafer 23 °, the wafer is first ground to a preset first thickness of about 14 to 20 mils (wafer thickness 6 to 10 mils plus the thickness of the central step layer 234b is about 8-10 mils). Next, as shown in FIG. 4, a thick cutting blade 40 is used to cut the wafer 200 along the wafer cutting line of the polished wafer 200 to form a depth of about 8 to 10 mils and a width of about 6 -8 Mill's Groove. Please refer to FIG. 5 again, and use a thin dicing knife 50, such as a diamond knife, to cut the grooved wafer of FIG. 4 into individual second wafers 2 3 0. Therefore, the bottom surface 234 of the second wafer 230 forms an outer tier 234a and a central tier 234b. The central step 234b has a thickness of about 8-10 mils, so that the second wafer 23 〇 and the first connection line 250 are stacked on the bonding surface 212 of the first wafer 210 in a non-contact manner. As mentioned above, the multi-chip stacked package structure according to the present invention is characterized in that the bottom and bottom masks of the upper chip have an outer step layer and a central step layer, and the central step layer provides lower chip soldering. The space required for the loops of the bonding wires to prevent the upper wafers from contacting the wire arcs of the lower wafers. Although the present invention has been disclosed with the aforementioned preferred embodiments, it is not intended to limit the present invention, 'any person skilled in the art', can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the attached patent application.

445599 Case No. 89109786 Brief Description of Modified Drawings [Illustration]: Figure la: A cross-sectional view of a multi-chip package structure known to US Patent No. 532 30 6 0; Figure lb: Known US Patent No. 60 0 577 No. 8 multi-chip package structure cross-sectional view; Figure 2: Cross-sectional view of a wafer mounted on a polishing table of the second wafer of the present invention; Figure 3: Figure 3: Wafer grinding using a grinding wheel to Sectional view of required thickness; Figure 4: Cross-sectional view of cutting the polished wafer with a thick dicing knife to form the required groove; Figure 5: Slotting of Figure 4 with a thin dicing knife The cross-section of a trench wafer cut into individual dies is not shown. Figure 6: A cross-sectional view of the multi-chip stacked package structure of the present invention; and Figure 7: A multi-chip stacked package structure of the present invention along the section line of Figure 7-7 Sectional view. Description of drawing number 10 Workbench 20 Adhesive layer 30 Grinding wheel 40 Thick cutter 50 Thin cutter 110 Wafer 120 Substrate 130 Wafer 140 Adhesive layer 150 Welding wire 200 Wafer 202 Wafer front 204 Wafer back 210 First wafer 212 Joint surface 214 Underside 216 Bonding pad 218 Central area

P00-048-amend. Ptc Page 12 445599 Case No. 89109786 Λ_Ά Brief description of correction diagram 220 Substrate 230 Second wafer 234a External step layer 236 Bonding pad 2 5 0 First connection line 2 6 0 Second connection line 2 2 2 Adhesive layer 232 Joint surface 234 234b Central step layer 238 Central area 252 Arc top surface

P00-048-amend.ptc Page 13

Claims (1)

Amend the Chinese invention patent specification to make polycrystalline Jiang 445599 Name of the invention English name (Chinese) 1. Tao Shu 2. Lin Junhong Inventor (total 2 persons) Applicant (total 1 person) — Name (English) l.TAOSu ---- -------------------__ ------------- 2 · LIN Chun Hung Nationality (Chinese and English) 1 · ROC 2 · ROC Residence of the Republic of China (Chinese) J. No. 72-2, Chongguan New Village, Camp Area 2 · 9th Floor Residence, No. 72, Qin Lei Title, Laoshan District, Nanxiong (English) l.No. iZ-Z, Chorng-Shyr New Village, Tso Ying District, Kaohsiung, Taiwan 2.9F1., No. 72, Huafeng St., Gushan Chiu, Kaohsiung, Taiwan, R. 0. C. Name or Name (Chinese) 1. Yueguang Semiconductor Manufacturing Co., Ltd. Name or Name (English) 1. Advanced Semiconductor Engineering, Inc. J-J (Chinese and English) 1. ROC Residence (F Business Office) (Chinese) 1 .. No. 26, Jingsan Road, Zizi Processing Export Zone, Kaohsiung City (This address is the same as the applicant who applied to your office before.) Residence Office) (Operation) 1.26, Chin 3rd Rd., Nantze Export Processing Zone, Kaohsiung, Taiwan, ROC Representative ( Text) tile Qian-sheng __ representative (English) ----, 1. Chian Seng CHANG Sheng 1 hundred 445599 __ Case No. 89109786_ Year Month ___ I. This case has been applied to the country (region) for the patent application date of the case No. Claims Article 24 of the Patent Law First Priority Rights II. □ Claims the Patent Law One of Article 25, the first priority: Application number: No date: 3. The claim is that the case is in accordance with Article 20 (1) of the Patent Law □ Paragraph 1 or □ Paragraph 2 Period: Date: □ The relevant microorganisms have been deposited abroad: The depositing country: The deposit institution: # Deposit date: The deposit number: □ The relevant microorganisms have been deposited in the country (the deposit institution designated by this bureau): the deposit institution : Storage date: No storage number: □ Those who are familiar with this technology are easy to obtain and do not need to be stored. ΙϋΙΙΙΙΙΙ P00-〇48-amend.ptc Page 3