WO2022120657A1

WO2022120657A1 - Packaging structure and preparation method therefor, and electronic device

Info

Publication number: WO2022120657A1
Application number: PCT/CN2020/135010
Authority: WO
Inventors: 郭茂; 任亦纬; 赵南; 郑见涛; 张晓东
Original assignee: 华为技术有限公司
Priority date: 2020-12-09
Filing date: 2020-12-09
Publication date: 2022-06-16
Also published as: CN116569327A

Abstract

Embodiments of the present application provide a packaging structure and a preparation method therefor, and an electronic device, relating to the technical field of chip packaging, and used for solving the problem of greatly reduced heat dissipation capability of a bare chip structure due to a reduced degree of attachment between a heat sink and the bare chip structure. The packaging structure comprises: a bare chip structure and a heat sink. The bare chip structure comprises a first bare chip, and the first bare chip comprises a silicon substrate. The heat sink comprises a heat sink body, and a first silicide bonding layer disposed on the heat sink body. The first silicide bonding layer is bonded to the silicon substrate.

Description

Package structure and preparation method thereof, and electronic device

technical field

The present application relates to the technical field of chip packaging, and in particular, to a packaging structure, a preparation method thereof, and an electronic device.

Background technique

Nowadays, the heat dissipation of the package structure has become one of the bottlenecks in the design of the package structure. For the heat dissipation of the package structure, in addition to using hardware (such as a heat sink) to realize the heat dissipation of the package structure, the design of the package structure itself also has a significant impact on the heat dissipation.

The heat generated by the bare chip structure itself in the package structure is mainly dissipated through the surface of the bare chip structure. Therefore, as shown in FIG. 1a , in the current package structure, generally, a heat sink (lid) 20 is added on the bare chip structure 10 , and the bare chip structure 10 and the heat sink 20 are bonded by a thermal integration material 30 (TIM). , so that the heat on the surface of the bare chip structure 10 is dissipated through the heat sink 20 . Based on the structure shown in FIG. 1a , the thermal resistance R ₁₀ of the bare chip structure 10 , the thermal resistance R 20 of the heat sink ₂₀ , the thermal resistance R ₃₀ of the thermally conductive adhesive 30 , and the degree of fit between the heat sink 20 and the thermally conductive adhesive 30 (affecting Factors such as the interface thermal resistance R _20/30 of the heat sink 20 and the thermally conductive adhesive 30 ), the fit between the thermally conductive adhesive 30 and the bare chip structure 10 (affecting the interface thermal resistance R _30/10 of the thermally conductive adhesive 30 and the bare chip structure 10 ) and other factors It directly affects the heat dissipation effect of the package structure.

However, although those skilled in the art use new thermal conductive materials (such as sintered silver, carbon nanotubes, graphene, etc.) as the main material of the thermal conductive adhesive 30 in order to reduce the thermal resistance of the thermal conductive adhesive 30, the main material of the heat sink 20 is usually It is metal (such as copper, copper alloy, etc.), and the main structure of the bare chip structure 10 is usually a silicon substrate. Therefore, there are still coefficients of thermal expansion of the materials used in the heat sink 20 , the thermally conductive adhesive 30 and the bare chip structure 10 . expansion, CTE) problems with large differences. As a result, after the temperature of the bare chip structure 10 is high, the heat sink 20 , the thermal conductive adhesive 30 and the bare chip structure 10 are deformed in different degrees, and there are different degrees of separation between the two, and even the entire layer is completely delaminated, thereby reducing the The degree of adhesion between the heat sink 20 and the thermally conductive adhesive 30 and/or the degree of adhesion between the thermally conductive adhesive 30 and the bare chip structure 10 (in the final analysis, the degree of adhesion between the heat sink 20 and the bare chip structure 10 ).

In this way, taking the partial separation of the heat sink 20 and the thermally conductive adhesive 30 as shown in FIG. 1b (at the dotted line circle) as an example, since the fit between the heat sink 20 and the thermally conductive adhesive 30 is reduced, the difference between the heatsink 20 and the thermally conductive adhesive 30 is reduced. The presence of air between the heat sinks 20 and the thermally conductive adhesive 30 increases the thermal resistance R _20/30 of the interface between the heat sinks 20 and the thermally conductive adhesive 30 , which leads to a sharp increase in the thermal resistance of the package structure and a sharp decrease in the heat dissipation capability of the bare chip structure 10 , which in turn causes the temperature of the bare chip structure 10 to rise sharply. increase, degrade performance, or even fail completely.

SUMMARY OF THE INVENTION

Embodiments of the present application provide a package structure, a method for manufacturing the same, and an electronic device, which are used to solve the problem that the heat dissipation capability of the bare chip structure decreases sharply due to the decrease in the degree of fit between the heat sink and the bare chip structure.

To achieve the above object, the application adopts the following technical solutions:

A first aspect of the embodiments of the present application provides a package structure, including: a bare chip structure, the bare chip structure includes a first bare chip; the first bare chip includes a silicon substrate; a heat sink includes a heat sink body and a heat sink disposed on the heat sink The first silicide bonding layer on the body; wherein, the first silicide bonding layer is bonded with the silicon substrate.

In the package structure provided by the embodiment of the present application, the bare chip structure and the heat sink are bonded through the first silicide bonding layer, and there is no need to provide heat dissipation glue. Since the bare chip structure and the heat sink are molecular-molecular bonds, the connection stability is far greater than the adhesive force of the heat-dissipating glue. Therefore, the worry about the adhesion of the heat dissipation glue in the traditional structure is removed. The chip stack structure and the heat sink in the present application have a good connection effect and a stable adhesion, which solves the problem of the adhesion between the bare chip structure and the heat sink. The problem is that the heat dissipation capacity of the bare chip structure decreases sharply. Thus, the performance and service life of the package structure are guaranteed. In addition, the bare chip structure and the heat sink are bonded through a first silicide bonding layer. The material of the first silicide bonding layer is silicide, which can well block metal ions (such as copper ions) in the heat sink body. ) into the bare chip structure. In this way, it is difficult for the metal ions to diffuse to the silicon substrate of the first bare chip in the bare chip structure, avoiding the problem that the performance of the transistors on the silicon substrate is affected due to the conduction of the silicon substrate, thereby affecting the performance of the first bare chip.

Optionally, the bare chip structure further includes a second silicide bonding layer covering the surface of the silicon substrate, and the first silicide bonding layer is bonded to the second silicide bonding layer. The second silicide bonding layer can further block metal ions (eg, copper ions) in the heat sink body from diffusing into the bare chip structure. In this way, it is difficult for metal ions to diffuse into the silicon substrate of the first bare chip in the bare chip structure, avoiding the problem that the performance of the transistors on the silicon substrate is affected due to the conduction of the silicon substrate, thereby affecting the performance of the first bare chip. .

Optionally, the first silicide bonding layer covers the surface of the heat sink body. In this way, the steps of patterning the formed first silicide thin film to form the first silicide bonding layer can be reduced, the process steps can be reduced, and the cost can be reduced.

Optionally, the heat sink body is provided with a slit. Because the deformation of the heat sink body is not only related to the thermal expansion coefficient of the material, but also to the size of the heat sink body. Therefore, by setting gaps on the heat sink body, an integral heat sink body is divided into a plurality of connected units, so that there is a buffer area (ie, the gap) between adjacent units, and the deformation force between adjacent units is not equal. overlay. Therefore, the influence of the stress on the bare chip structure caused by the deformation of the heat sink body can be reduced without affecting the adhesion between the heat sink body and the bare chip structure.

Optionally, the region where the gap is provided on the heat sink body overlaps with the region where the first silicide bonding layer is bonded to the silicon substrate. The stress on the bare chip structure is most affected by the area of the heat sink body that is bonded to the silicon substrate. Therefore, by arranging a gap in the area where the heat sink body is bonded to the silicon substrate, the influence of the stress on the bare chip structure caused by the deformation of the heat sink body can be significantly reduced.

Optionally, the heat sink body is provided with multiple slits; the multiple slits intersect at the center of the heat sink body. The structure of the heat sink body is simple, and the heat sink body is divided into multiple structures by a plurality of slits, and the stress on the heat sink body is dispersed, which can reduce the stress effect on the heat sink body.

Optionally, the heat sink body includes an outer ring and a plurality of extension bars extending inward along the inner edge of the outer ring, and there are gaps between adjacent extension bars. In this way, the central area of the heat sink body has more and more dispersed gaps, and the stress dispersion effect on the heat sink body is good. Moreover, the heat can be prevented from accumulating in the central area of the heat sink body, and at the same time, the heat can be transmitted from the extension strip to the outer ring, and the heat dissipation effect can be ensured.

Optionally, the gap is located in the center of the heat sink body, and the gap is a closed figure. Since the stress is most concentrated at the center of the heat dissipation plate body, disposing a gap in the center of the heat dissipation plate body can reduce the stress effect on the heat dissipation plate body.

Optionally, the first silicide bonding layer and the silicon substrate are bonded by a direct bonding process. The direct bonding process achieves the perfect combination of the first silicide bonding layer and the silicon substrate at room temperature, and completes annealing at 90-300°C. When the annealing ambient temperature is lower than 250°C, the bonding process has little negative impact on the performance of the bare chip structure (because the packaged package structure will be tested for performance at 250°C), which can improve product yield.

Optionally, the material constituting the first silicide bonding layer includes one of SiN, SiC, and SiO2. The thermal conductivity of SiN, SiC, and SiO2 exceeds that of the current best heat dissipation glue, so the thermal conductivity of the bare chip structure can be significantly improved.

Optionally, the thickness of the first silicide bonding layer is 0.3-2 μm. Compared with the 50 μm thick heat dissipation glue in the related art, the thickness of the 0.3 μm-2 μm thick first silicide bonding layer in the embodiment of the present application is much smaller than the thickness of the heat dissipation glue, which can shorten the gap between the bare chip structure and the heat sink body. The heat dissipation path between the two reduces the thermal resistance of the first silicide bonding layer and improves the heat dissipation effect of the bare chip structure. In addition, the package structure can also be made thinner and lighter.

Optionally, the material constituting the second silicide bonding layer includes one of SiN, SiC, and SiO2. The thermal conductivity of SiN, SiC, and SiO2 exceeds that of the current best heat dissipation glue, so the thermal conductivity of the bare chip structure can be significantly improved.

Optionally, the thickness of the second silicide bonding layer is 0.3-2 μm. In the embodiment of the present application, the thickness of the second silicide bonding layer with a thickness of 0.3 μm-2 μm is 0.3-2 μm, which can shorten the heat dissipation path between the bare chip structure and the heat sink body, and reduce the thickness of the second silicide bonding layer. The thermal resistance with a thickness of 0.3-2μm improves the heat dissipation effect of the bare chip structure. In addition, the package structure can also be made thinner and lighter. Optionally, the bare chip structure further includes a second bare chip, the first bare chip and the second bare chip form a vertical stack structure, and the active surface of the first bare chip is bonded to the back surface of the second bare chip. In this way, the bare chip structure can be miniaturized and integrated, thereby reducing the area of the package structure.

Optionally, the package structure further includes a substrate, and the substrate is bonded to the active surface of the bare chip structure.

Optionally, there is a gap between the heat sink and the substrate. Because in the embodiment of the present application, the bare chip structure is bonded to the heat sink before being bonded to the substrate. Therefore, by arranging a gap between the heat sink and the substrate, the influence of the stress between the heat sink and the bare chip structure on the bonding effect or the bonding reliability of the bare chip structure and the substrate can be reduced.

Optionally, the package structure further includes a pressing ring, and the pressing ring is disposed on the surface of the substrate facing the bare chip structure; the pressing ring is located at the periphery of the bare chip structure. Since the substrate is prone to warp deformation after being heated, the stability of the bonding between the substrate and other components will be affected. Therefore, by arranging a pressing ring on the substrate, the traction force of the pressing ring on the substrate can alleviate the warping deformation of the substrate.

Optionally, the pressing ring is located between the heat sink and the substrate. By arranging the pressing ring between the heat sink and the substrate, it is not necessary to require the area of the substrate to be larger than that of the heat sink, and the area of the package structure can be reduced.

Optionally, the fin ring is located on the periphery of the heat sink. In some structures, the area of the substrate is larger and the degree of warpage is larger. The greater the stiffness of the pressing ring, the better the flattening effect on the substrate. Since the stiffness of the pressing ring is related to the thickness of the pressing ring along the direction perpendicular to the substrate, by arranging the pressing ring on the periphery of the heat sink, it is not necessary to limit the thickness of the pressing ring. Adjust the thickness of the pressing ring according to the area of the substrate, so as to adjust the stiffness of the pressing ring, so as to solve the problem of warping of the substrate to the greatest extent.

Optionally, there is a gap between the heat sink and the pressing ring. In this way, the pressing ring can not only adjust the warping problem of the substrate, but also the deformation of the heat sink and the substrate will not affect each other after the package structure is heated, so as to avoid the influence of stress between the heat sink and the substrate.

In a second aspect of the embodiments of the present application, a method for preparing a package structure is provided, including: forming a bare chip structure; the bare chip structure includes a first bare chip; the first bare chip includes a silicon substrate; forming a heat sink; A chip body and a first silicide bonding layer formed on the heat sink body; bonding the first silicide bonding layer with the silicon substrate. The beneficial effects of the method for preparing the encapsulation structure provided by the embodiments of the present application are the same as those of the encapsulation structure, which will not be repeated here.

Optionally, forming the heat sink includes: forming a first silicide film on the heat sink; the heat sink includes a plurality of cutting lines intersecting horizontally and vertically; polishing the surface of the first silicide film away from the heat sink; The heat sink plate is cut by wire to obtain the heat sink.

Optionally, the bare chip structure includes a first bare chip; forming the bare chip structure includes: polishing the back surface of the wafer layer; the wafer layer includes a plurality of dicing lines intersecting horizontally and longitudinally; Separation is performed to obtain a bare chip structure.

Optionally, before polishing the backside of the wafer layer, the method further includes: grinding and thinning the backside of the wafer layer.

Optionally, the bare chip structure includes a first bare chip and a second silicide bonding layer covering the silicon substrate of the first bare chip; forming the bare chip structure includes: forming a second silicide on the backside of the wafer layer film; the wafer layer includes a plurality of cross-cutting lanes; polishing the surface of the second silicide film away from the wafer layer; separating the wafer layer along the cutting lanes to obtain a bare chip structure.

Optionally, before forming the second silicide film on the backside of the wafer layer, the method further includes: grinding and thinning the backside of the wafer layer.

Optionally, a direct bonding process is used to bond the first silicide bonding layer to the silicon substrate. The direct bonding process is to achieve the perfect combination of the first silicide bonding layer and the bare chip structure at room temperature, and complete the annealing at 90-300°C. When the annealing ambient temperature is lower than 250°C, the bonding process has little negative impact on the performance of the bare chip structure (because the packaged package structure will be tested for performance at 250°C), which can improve product yield.

Optionally, before cutting the heat dissipation plate along the cutting line, the bare chip structure and the first silicide film are bonded. In this way, the first silicide film is larger and easier to handle. In addition, after the bare chip structures are aligned, a plurality of bare chip structures can be bonded to the first silicide film through a single bonding process, which can reduce the number of bonding times.

Optionally, the preparation method of the package structure further includes: after bonding the first silicide bonding layer with the silicon substrate, bonding the substrate and the bare chip structure on the active surface of the bare chip structure.

Optionally, the preparation method of the package structure further includes: before bonding the substrate and the silicon substrate, connecting the pressing ring to the substrate; wherein, the pressing ring is arranged on the surface of the substrate facing the bare chip structure.

In a third aspect of the embodiments of the present application, an electronic device is provided, including a circuit board and a package structure according to any one of the first aspect; the package structure is bonded to the circuit board.

The beneficial effects of the electronic device provided by the embodiments of the present application are the same as the beneficial effects of the above-mentioned packaging structure, which will not be repeated here.

Description of drawings

1a is a schematic structural diagram of a heat sink and a bare chip structure provided by the related art;

Fig. 1b is a schematic diagram of thermal deformation of a heat sink and a bare chip structure provided by the related art;

FIG. 2 is a schematic structural diagram of an electronic device provided by an embodiment of the present application;

3a is a schematic structural diagram of a heat sink and a bare chip structure provided by an embodiment of the application;

3b is a schematic structural diagram of another heat sink and a bare chip structure provided by an embodiment of the present application;

FIG. 3c is a schematic structural diagram of another heat sink and a bare chip structure provided by an embodiment of the present application;

3d is a schematic structural diagram of another heat sink and a bare chip structure provided by an embodiment of the application;

4a is a schematic structural diagram of a packaging structure provided by an embodiment of the present application;

4b is a flowchart of a method for preparing a bare chip structure provided by an embodiment of the present application;

FIG. 5 is a schematic diagram of a preparation process of a bare chip structure provided by an embodiment of the present application;

6a is a schematic structural diagram of another packaging structure provided by an embodiment of the present application;

FIG. 6b is a schematic structural diagram of another packaging structure provided by an embodiment of the present application;

FIG. 7a is a schematic structural diagram of a heat sink body according to an embodiment of the present application;

7b is a schematic structural diagram of another heat sink body provided by an embodiment of the present application;

7c is a schematic structural diagram of another heat sink body provided by an embodiment of the present application;

8 is a flowchart of a method for preparing a heat sink provided by an embodiment of the present application;

9a is a schematic structural diagram of a heat dissipation plate provided by an embodiment of the present application;

9b is a schematic diagram of a preparation process of a heat sink provided by an embodiment of the application;

10a is a schematic diagram of a bonding process of a heat sink and a bare chip structure according to an embodiment of the present application;

10b is a flowchart of a method for bonding a heat sink and a bare chip structure according to an embodiment of the application;

FIG. 10c is a schematic diagram of another bonding process of a heat sink and a bare chip structure according to an embodiment of the present application;

FIG. 10d is a flowchart of another method for bonding a heat sink and a bare chip structure according to an embodiment of the application;

11a is a schematic structural diagram of another packaging structure provided by an embodiment of the present application;

11b is a top view of a die ring and a bare chip structure provided by an embodiment of the application;

FIG. 11c is a schematic structural diagram of another packaging structure provided by an embodiment of the present application;

12a is a schematic structural diagram of another packaging structure provided by an embodiment of the present application;

12b is a top view of a package structure provided by an embodiment of the application;

13 is a schematic structural diagram of a tableting ring provided by an embodiment of the application;

14 is a flowchart of a method for preparing a packaging structure provided by an embodiment of the present application;

15a is a schematic structural diagram of another packaging structure provided by an embodiment of the present application;

15b is a schematic diagram of a preparation process of a bare chip structure provided by an embodiment of the present application;

16a is a schematic structural diagram of another packaging structure provided by an embodiment of the present application;

16b is a schematic diagram of a preparation process of another bare chip structure provided by an embodiment of the present application;

17a is a schematic structural diagram of another packaging structure provided by an embodiment of the present application;

17b is a schematic structural diagram of another packaging structure provided by an embodiment of the present application;

18 is a flowchart of a method for preparing a bare chip structure provided by an embodiment of the application;

FIG. 19 is a schematic diagram of a preparation process of yet another bare chip structure provided by an embodiment of the present application.

Reference number:

200-electronic equipment; 210-middle frame; 2101-carrier board; 2102-frame; 220-back shell; 230-display screen; 240-circuit board; 250-electronic device; 100-package structure; 10-bare chip structure; 11-first bare chip; 111-silicon substrate; 112-pad; 113-wafer layer; 12-second silicide bonding layer; 121-second silicide film; 13-second bare chip; 20- 21- heat sink body; 211- gap; 212- heat sink; 213- outer ring; 214- extension strip; 22- first silicide bonding layer; 221- first silicide film; 30- thermally conductive adhesive ; 40-substrate; 50-tablet ring.

Detailed ways

The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments.

Hereinafter, the terms "first", "second", etc. are only used for convenience of description, and should not be construed as indicating or implying relative importance or implying the number of indicated technical features. Thus, a feature defined as "first", "second", etc., may expressly or implicitly include one or more of that feature. In the description of this application, unless stated otherwise, "plurality" means two or more.

In addition, in the embodiments of the present application, "upper", "lower", "left" and "right" are not limited to be defined relative to the schematic placement of components in the drawings, and it should be understood that these directional terms may be Relative notions, they are used for relative description and clarification, which may vary accordingly depending on the orientation in which the components are placed in the drawings.

In this application, unless otherwise expressly specified and limited, the term "connection" should be understood in a broad sense. For example, "connection" may be a fixed connection, a detachable connection, or an integrated body; it may be directly connected, or Can be indirectly connected through an intermediary. In addition, the term "electrical connection" may be a direct electrical connection or an indirect electrical connection through an intermediate medium.

The embodiments of the present application provide an electronic device. The electronic device may include a mobile phone (mobile phone), a tablet computer (pad), a TV, a smart wearable product (for example, a smart watch, a smart bracelet), a virtual reality (virtual reality, VR) terminal device, an augmented reality (augmented reality), AR) terminal equipment, charging small household appliances (such as soymilk maker, sweeping robot), drones and other electronic products. The embodiments of the present application do not specifically limit the specific form of the above electronic device.

Any of the above electronic devices is taken as an example of a mobile phone. As shown in FIG. 2 , the electronic device 200 may include a middle frame 210 , a rear case 220 and a display screen 230 . The middle frame 210 includes a carrier board 2101 for carrying the display screen 230 , and a frame 2102 surrounding the carrier board 2101 . The electronic device 200 may include a circuit board 240 disposed on the surface of the carrier board 2101 facing the rear case 220 and some electronic devices 250 disposed on the circuit board 240 .

The circuit board 240 may be, for example, a printed circuit board (printed circuit boards, PCB), and the electronic device 250 may be, for example, a motherboard, a system on chip (SOC), a package structure, etc. The circuit board 240 is used to carry the above-mentioned electronic device 250 , and completes signal interaction with the above-mentioned electronic device 250 .

The rear case 220 is connected with the middle frame 210 , which can prevent the external water vapor and dust from affecting the performance of the circuit board 240 and the electronic device 250 .

Taking the package structure as an example, the performance and service life of the package structure directly affect the performance and service life of the electronic device 200 .

Based on this, an embodiment of the present application provides a package structure. As shown in FIG. 3 a , the package structure 100 includes a bare chip structure 10 .

Among them, the bare chip structure 10 has an active surface a1 and a back surface b1 which are arranged opposite to each other. The side provided with the transistors of the bare chip structure 10 is called the active side a1, and the side where the transistors are not provided is called the back side b1.

Regarding the structure of the bare chip structure 10, the bare chip structure 10 may include only one layer of bare chips (die), may also include multiple layers of vertically stacked bare chips, and may also include some on the basis of including one or more layers of bare chips. Encapsulation auxiliary layer, etc.

Illustratively, in a possible embodiment, as shown in FIG. 3 a , the bare chip structure 10 includes only one layer of the first bare chip 11 .

The first bare chip 11 includes a silicon substrate 111 and a pad 112 .

Based on this structure, the active surface of the first bare chip 11 serves as the active surface a1 of the bare chip structure 10 . Based on the structure shown in FIG. 3 a , the backside of the first bare chip 11 serves as the backside b1 of the bare chip structure 10 .

Illustratively, in another possible embodiment, as shown in FIG. 3b, the bare chip structure 10 includes a first bare chip 11 and a second bare chip 13, and the first bare chip 11 and the second bare chip 13 form a vertical stack In the structure, the active surface of the first bare chip 11 is bonded to the back surface of the second bare chip 13 .

Based on this structure, the active surface of the second bare chip 13 serves as the active surface a1 of the bare chip structure 10 . Based on the structure shown in FIG. 3 b , the back surface of the first bare chip 11 is used as the back surface b1 of the bare chip structure 10 .

The sizes of the first bare chip 11 and the second bare chip 13 may be the same or different.

It can be understood that the bare chip structure 10 may further include multiple layers of second bare chips 13 , and FIG. 3 b is only illustrated by taking the bare chip structure 10 including one layer of second bare chips 13 as an example.

Illustratively, in another possible embodiment, as shown in FIGS. 3 c and 3 d , the bare chip structure 10 includes a first bare chip 11 and a second silicide covering the surface of the silicon substrate 111 of the first bare chip 11 . For the bonding layer 12 , the first silicide bonding layer 22 is bonded to the second silicide bonding layer 12 .

Based on the structure shown in FIG. 3 c , the active surface of the first bare chip 11 serves as the active surface a1 of the bare chip structure 10 , and the backside of the second silicide bonding layer 12 serves as the backside b1 of the bare chip structure 10 . Based on the structure shown in FIG. 3d , the active surface of the second bare chip 13 serves as the active surface a1 of the bare chip structure 10 , and the backside of the second silicide bonding layer 12 serves as the backside b1 of the bare chip structure 10 .

On this basis, as shown in FIG. 3 a , the package structure 100 further includes a heat sink 20 . The heat sink 20 is located on the side where the back surface b1 of the bare chip structure 10 is located.

The heat sink 20 includes a heat sink body 21 and a first silicide bonding layer 22 disposed on the heat sink body 21 .

Here, the material of the heat sink body 21 is not limited, and the heat sink body 21 in the prior art is applicable to the present application. Since metal has better thermal conductivity, in some embodiments, the material of the heat sink body 21 is metal. For example, the material of the heat sink body 21 is copper (Cu), copper alloy, stainless steel, or the like.

The material of the first silicide bonding layer 22 is not limited, and the material of the first silicide bonding layer 22 may be a metal silicide or a non-metal silicide. In some embodiments, the material of the first silicide bonding layer 22 includes, for example, one of silicon nitride (SiN), silicon carbide (SiC), and silicon oxide (SiO 2 ).

The first silicide bonding layer 22 can be deposited on the first silicide bonding layer 22 by, for example, a plasma chemical vapor deposition (PECVD) process to form a fixed connection between the first silicide bonding layer 22 and the first silicide bonding layer 22. The heat sink body 21 .

As shown in FIG. 3a, the first silicide bonding layer 22 is close to the die structure 10 relative to the heat sink body 21 (that is, the first silicide bonding layer 22 is located between the heat sink body 21 and the die structure 10), and The first silicide bonding layer 22 is bonded to the bare chip structure 10 .

The way to realize the bonding between the first silicide bonding layer 22 and the bare chip structure 10 is based on the structures shown in FIG. 3 a and FIG. 3 b . The silicon substrate 111 is bonded. Based on the structures shown in FIGS. 3 c and 3 d , the first silicide bonding layer 22 is bonded to the second silicide bonding layer 12 in the bare chip structure 10 .

The embodiments of the present application do not limit the bonding process of the first silicide bonding layer 22 and the bare chip structure 10 , as long as the two can be fixedly connected. Whether the first silicide bonding layer 22 is bonded with the silicon substrate 111 or with the second silicide bonding layer 12, both are silicon-silicon bonding. Based on this, for example, the first silicide bonding layer 22 and the bare chip structure 10 may be bonded by an in-direct bonding process, or a direct bonding process or the like.

Among them, bonding refers to a process in which two homogeneous or heterogeneous materials are surface-treated and directly combined under certain conditions to achieve electrical/mechanical interconnection between the two materials. Indirect bonding means that the bonding surface is activated by certain technical means or sputtering other substances to improve the bonding, and a reliable connection is formed on the bonding surface. Usually, the bonding surface has a single composition. Direct bonding refers to the direct bonding of two surfaces without intervening substances.

In the package structure 100 provided by the embodiment of the present application, the bare chip structure 10 and the heat sink 20 are bonded by the first silicide bonding layer 22 , and it is not necessary to provide heat dissipation glue. Since the bare chip structure 10 and the heat sink 20 are molecule-to-molecular bonds, the connection stability is far greater than the adhesive force of the heat-dissipating glue. Therefore, the concern about the fit of the heat-dissipating glue in the traditional structure is removed. In the present application, the connection effect between the chip stack structure 10 and the heat sink 20 is good, and the fit is stable, which solves the problem of the bare chip structure 10 and the heat sink. The adhesion degree of 20 decreases, which leads to the problem that the heat dissipation capability of the bare chip structure 10 decreases sharply. Thus, the performance and service life of the package structure 100 are guaranteed.

In addition, the bare chip structure 10 and the heat sink 20 are bonded through the first silicide bonding layer 22 , and the material of the first silicide bonding layer 22 is silicide, which can well block the metal in the heat sink body 21 Ions (eg, copper ions) diffuse into the bare chip structure 10 . In this way, it is difficult for metal ions to diffuse to the silicon substrate 111 of the first bare chip 11 in the bare chip structure 10 that is closest to the heat sink 20, so that the performance of the transistors on the silicon substrate 111 is prevented from being affected due to the conduction of the silicon substrate. A problem affecting the performance of the first bare chip 11 .

Hereinafter, the package structure 100 provided by the embodiments of the present application will be described with several detailed embodiments.

Example 1

An embodiment of the present application provides a package structure 100 . As shown in FIG. 4 a , the package structure 100 includes a bare chip structure 10 . The bare chip structure 10 has an active surface a1 and a back surface b1 disposed opposite to each other.

The bare chip structure 10 includes a layer of a first bare chip 11 , and the first bare chip 11 includes a silicon substrate 111 and a pad 112 . The active surface a3 of the first bare chip 11 is used as the active surface a1 of the bare chip structure 10 , and the back surface b3 of the first bare chip 11 is used as the back surface b1 of the bare chip structure 10 .

Based on the bare chip structure 10 shown in FIG. 4a, in a possible embodiment, as shown in FIG. 4b, the preparation method of the bare chip structure 10 includes:

S10 , as shown in FIG. 5 , grinding and thinning the back surface b2 of the wafer layer 113 .

It can be understood that the bare chip structure 10 includes a layer of first bare chips 11 , and therefore, the wafer layer 113 only includes a layer of wafer. The back surface b2 of the wafer layer 113 is opposite to the active surface a2 of the wafer layer 113 .

In addition, when backside grinding (BG) is performed on the wafer layer 113, the specific thickness of the backside b2 of the wafer layer 113 is determined according to the actual requirements of the product. Of course, if the thickness of the wafer layer 113 meets product requirements, this step may not be performed.

As shown in FIG. 5 , in the process of grinding and thinning the second back surface b2 of the wafer layer 113 , since the surface of the active surface a2 of the wafer layer 113 is not flat, a filling layer may be provided to remove the wafer layer The active surface a2 of 113 is filled flat (for example, filled with a polymer material). Then, it is placed on a carrier, and then the backside b2 of the exposed wafer layer 113 is ground and thinned. In order to ensure that the wafer layer 113 is fixed in position during the grinding process, the filling layer and the carrier plate may be bonded together through an adhesive layer to fix the wafer layer 113 .

S20 , polishing the back surface b2 of the wafer layer 113 .

In this step, the wafer layer 113 can still be placed on the carrier board, and the back surface b2 of the wafer layer 113 can be polished.

S30 , as shown in FIG. 5 , the wafer layer 113 is separated along the dicing lines to obtain the bare chip structure 10 .

It can be understood that, if the wafer layer 113 is placed on the carrier board, and the back surface b2 of the wafer layer 113 is ground and thinned, then the wafer layer 113 needs to be removed before cutting the wafer layer 113 along the dicing road. Separate from the filler layer.

As shown in FIG. 4 a , the package structure 100 further includes a heat sink 20 . The heat sink 20 includes a heat sink body 21 and a first silicide bonding layer 22 disposed on the heat sink body 21 .

Here, the main function of the first silicide bonding layer 22 is to bond the heat sink body 21 to the bare chip structure 10 . Therefore, in order to ensure the bonding effect between the heat sink body 21 and the bare chip structure 10 , the first silicide bonding layer 22 at least covers the back surface b1 of the bare chip structure 10 .

Based on this, in a possible embodiment, as shown in FIG. 6 a , the first silicide bonding layer 22 covers the backside b1 of the bare chip structure 10 .

The first silicide bonding layer 22 may be formed by, for example, a PECVD process.

In order not to pattern the first silicide bonding layer 22 , in another possible embodiment, as shown in FIG. 4 a , the first silicide bonding layer 22 covers the surface of the heat sink body 21 .

Since the heat dissipation effect is related to both the heat dissipation material and the heat dissipation path, on the basis of satisfying the stable bonding between the first silicide bonding layer 22 and the bare chip structure 10, the thinner the thickness of the first silicide bonding layer 22, the better .

In some embodiments, the thickness of the first silicide bonding layer 22 is 0.3 μm-2 μm. For example, the thickness of the first silicide bonding layer 22 is 0.5 μm, 0.7 μm, 0.8 μm, 1 μm, 1.3 μm, 1.5 μm, 1.7 μm, or the like.

Compared with the heat dissipation glue with a thickness of about 50 μm in the related art, the thickness of the first silicide bonding layer 22 with a thickness of 0.3 μm-2 μm in the embodiment of the present application is much smaller than the thickness of the heat dissipation glue, which can shorten the thickness of the bare chip structure 10 and the heat dissipation. The heat dissipation path between the chip bodies 21 reduces the thermal resistance of the first silicide bonding layer 22 and improves the heat dissipation effect of the bare chip structure 10 . In addition, the package structure 100 can also be made thinner and lighter.

The material of the first silicide bonding layer 22 can be, for example, one of silicon nitride (SiN), silicon carbide (SiC), and silicon oxide (SiO 2 ). Taking SiN as an example, the thermal conductivity of SiN is 10-43 W/m.K, which is higher than that of the current best heat dissipation glue, so the thermal conductivity of the bare chip structure 10 can be significantly improved.

Regarding the structure of the heat sink body 21, in a possible embodiment, as shown in FIG. 6b, the heat sink body 21 includes a groove, and the bare chip structure 10 is located in the groove. That is, the heat sink body 21 is a cover-like structure.

In order to form the first silicide bonding layer 22 on the plurality of heat sink bodies 21 in the same process, so as to improve the preparation efficiency of the heat sink 20 and simplify the structure of the heat sink bodies 21, another possible implementation In an example, as shown in FIG. 4a, the heat sink body 21 is a plate-like structure.

Considering that the coefficient of thermal expansion (CTE) of the material of the heat sink body 21 is quite different from the thermal expansion coefficient of the material of the silicon substrate 111 in the bare chip structure 10 (taking the material of the heat sink body 21 as copper as an example, The thermal expansion coefficient of copper is about 171E-6/K, and the thermal expansion coefficient of silicon is about 31E-6/K.) The heat sink body 21 may be damaged by thermal deformation.

In some embodiments, as shown in FIG. 7a , the heat sink body 21 is provided with a slit 211 .

The embodiment of the present application does not limit the shape, size, setting position, etc. of the slit 211 , and the heat sink body 21 may be a discontinuous structure.

Because the deformation of the heat sink body 21 is not only related to the thermal expansion coefficient of the material, but also related to the size of the heat sink body 21 . Therefore, by arranging slits 211 on the heat sink body 21, an integral heat sink body 21 is divided into a plurality of connected units, so that there is a buffer area between adjacent units (ie, at the gap 211), and the adjacent units have a buffer area. The inter-deformation forces are not superimposed. Therefore, the influence of the stress on the bare chip structure 10 caused by the deformation of the heat sink body 21 can be reduced without affecting the adhesion between the heat sink body 21 and the bare chip structure 10 .

In some embodiments, as shown in FIG. 7a , the heat sink body 21 is provided with a gap in the region, and the first silicide bonding layer 22 is bonded with the silicon substrate 111 in the region (the region enclosed by the dotted line in the figure). )overlapping.

The area where the gap is provided on the heat sink body 21 overlaps with the area where the first silicide bonding layer 22 and the silicon substrate 111 are bonded. The two areas may be completely overlapped or the two areas may overlap. part.

Due to the area of the heat sink body 21 bonded to the silicon substrate 111 , the stress generated on the bare chip structure 10 has the greatest influence. Therefore, the gap 211 is provided in the area where the heat sink body 21 is bonded to the silicon substrate 111 , which can significantly reduce the stress influence on the bare chip structure 10 caused by the deformation of the heat sink body 21 .

Regarding the shape of the slits 211 on the heat sink body 21 , in some embodiments, as shown in FIG.

The widths and shapes of the plurality of slits may be different or the same. In FIG. 7a, the plurality of slits are taken as an example of strip-shaped structures with the same width for illustration.

In this way, the structure of the heat sink body 21 is simple, the plurality of slits 211 divide the heat sink body 21 into multiple structures, and the stress on the heat sink body 21 is discontinuous, thereby reducing the stress effect on the heat sink body 21 .

In other embodiments, as shown in FIG. 7 b , the heat sink body 21 includes an outer ring 213 and a plurality of extension bars 214 extending inward along the inner edge of the outer ring 213 , and there are gaps 211 between adjacent extension bars 214 .

The specific shape of the outer ring 213 is not limited, and may be a circular ring, a rectangular ring, or the like. The inner edge of the outer ring 213 refers to the inner contour enclosing the shape of the outer ring 213 , and extending inward refers to extending toward the hollow area of the outer ring 213 .

In addition, as shown in FIG. 7b , the dimensions of the plurality of extension bars 214 are not limited to be the same, and the dimensions of the plurality of extension bars 214 may be different.

In this way, the gaps 211 in the central region of the heat sink body 21 are numerous and dispersed, and the stress dispersion effect on the heat sink body 21 is good. Moreover, it can prevent heat from accumulating in the central area of the heat sink body 21, and at the same time, it can ensure that the heat is transferred from the extension strip 214 to the outer ring 213, and the heat dissipation effect is ensured.

In other embodiments, as shown in FIG. 7 c , the slit 211 is located in the center of the heat sink body 21 , and the slit 211 is a closed figure.

The slit 211 may be a closed figure of any shape, and FIG. 7c only takes the slit as a rectangle as an example for illustration.

Since the stress is most concentrated at the center of the heat dissipation plate body 21 , the gap 211 is provided in the center of the heat dissipation plate body 21 to reduce the stress effect on the heat dissipation plate body 21 .

Based on the heat sink 20 shown in FIG. 4a , in a possible embodiment, as shown in FIG. 8 , the preparation method of the heat sink 20 includes:

S100 , forming a first silicide film 221 on the heat dissipation plate 212 .

Wherein, as shown in FIG. 9 a , the heat dissipation plate 212 is provided with cutting lines intersecting horizontally and vertically, and the intersecting cutting lines enclose a plurality of heat sink bodies 21 .

As shown in FIG. 9b, the heat dissipation plate 212 can be placed on the carrier plate, and the first silicide film 221 can be formed by a PECVD process.

It can be understood that, as shown in FIG. 7a and FIG. 7b, in the case where the gap 211 is provided on the heat sink body 21, due to the large difference between the thickness of the first silicide film 221 and the thickness of the heat sink body 21, the first A silicide film 221 does not fill the gap 211 on the heat sink body 21 .

S200 , as shown in FIG. 9 b , polishing the surface of the first silicide film 221 away from the heat dissipation plate 212 .

S300 , as shown in FIG. 9 b , the heat dissipation plate 212 is cut along the cutting line to obtain the heat dissipation fin 20 .

Regarding the positional relationship between the heat sink 20 and the bare chip structure 10, as shown in FIG. 111 bonding.

Based on this, the preparation method of the package structure 100 further includes: bonding the first silicide bonding layer 22 to the silicon substrate 111 of the first bare chip 11 .

The embodiments of the present application do not limit the bonding manner of the first silicide bonding layer 22 and the bare chip structure 10 . In some embodiments, the first silicide bonding layer 22 is bonded to the silicon substrate 111 of the first bare chip 11 using a direct bonding process.

The direct bonding process is to achieve the perfect combination of the first silicide bonding layer 22 and the bare chip structure 10 at room temperature, and complete the annealing at a temperature of 90-300°C. In the case where the annealing ambient temperature is lower than 250°C, the bonding process has little negative impact on the performance of the bare chip structure 10 (because the packaged package structure 100 will be tested for performance in an environment of 250°C), which can improve product quality. Rate.

In order to improve the alignment accuracy between the bare chip structure 10 and the heat sink 20 , in a possible embodiment, as shown in FIG. 10 a , the prepared bare chip structure 10 and the prepared heat sink 20 are bonded.

The preparation process is shown in FIG. 10 b , after performing steps S30 and S300 , the preparation method of the package structure 100 further includes: S1000 , bonding the first silicide bonding layer 22 to the silicon substrate 111 of the first bare chip 11 .

It can be understood that, steps S10-S30 and steps S100-S300 are not limited in order, and they can also be performed simultaneously.

In another possible embodiment, as shown in FIG. 10c , before cutting the heat dissipation plate 212 along the cutting line, the bare chip structure 10 and the first silicide film 221 are bonded. Then, the heat dissipation plate 212 is cut along the cutting line.

In this way, the first silicide film 221 is larger and easier to handle. In addition, after the bare chip structures 10 are aligned, a plurality of bare chip structures 10 can be bonded to the first silicide film 221 through a single bonding process, which can reduce the number of bonding times.

The preparation process is shown in FIG. 10d , before step S300 is performed, the preparation method of the package structure 100 further includes: S2000 , bonding the first silicide film 221 to the silicon substrate 111 of the first bare chip 11 .

Then, step S300 is performed to cut the heat dissipation plate 212 along the cutting line. The heat sink 20 obtained at this time has been bonded to the bare chip structure 10 .

On this basis, as shown in FIG. 4 a , the package structure 100 further includes a substrate 40 , and the substrate 40 is bonded to the active surface a1 of the bare chip structure 10 .

The bare chip structure 10 can perform signal interaction with other electronic devices through the substrate 40 , for example, the bare chip structure 10 can be connected to the circuit board 240 in the above-mentioned electronic device 200 through the substrate 40 .

The embodiments of the present application do not limit the bonding method between the substrate 40 and the bare chip structure 10 . For example, the bonding method between the substrate 40 and the bare chip structure 10 may be realized by means of thermal compression non-conductive paste (TCNCP). Bond. The non-conductive glue can be, for example, an underfill glue.

As can be seen from the above, in the embodiment of the present application, the bare chip structure 10 is bonded with the heat sink 20 before bonding with the substrate 40 . Therefore, in order to reduce the influence of the stress between the heat sink 20 and the bare chip structure 10 on the bonding effect or the bonding reliability of the bare chip structure 10 and the substrate 40, as shown in FIG. 4a, FIG. 6a and FIG. 6b, regardless of the heat dissipation Regardless of the structure of the sheet 20 , in some embodiments, there is a gap between the heat sink 20 and the substrate 40 . That is, the heat sink 20 is not in contact with the substrate 40 .

Since the substrate 40 is easily warped and deformed after being heated, the stability of the bonding between the substrate 40 and other components will be affected. In some embodiments, as shown in FIG. 11 a , the package structure 100 further includes a die ring 50 , and the die ring 50 is disposed on the surface of the substrate 40 facing the bare chip structure 10 . As shown in FIG. 11 b , the die ring 50 is located at the periphery of the die structure 10 .

As shown in FIG. 11a, the pressing ring 50 and the substrate 40 may be bonded by, for example, an adhesive layer.

The material of the tableting ring 50 is not limited, and the material of the tableting ring 50 may be stainless steel, for example.

By arranging the pressing ring 50 on the substrate 40 , the pulling force of the pressing ring 50 to the substrate 40 can effectively relieve the warping deformation of the substrate 40 .

Regarding the setting position of the pressing ring 50 , in a possible embodiment, as shown in FIG. 11 a , along the direction perpendicular to the substrate 40 , the pressing ring 50 is located between the heat sinks 20 and the substrates 40 .

By disposing the pressing ring 50 between the heat sink 20 and the substrate 40 , the area of the substrate 40 does not need to be larger than that of the heat sink 20 , and the area of the package structure 100 can be reduced.

Based on this, in some embodiments, as shown in FIG. 11 a , along the direction perpendicular to the substrate 40 , there is a gap between the pressing ring 50 and the heat sink 20 . That is, the fin ring 50 and the heat sink 20 are not in contact.

In this way, the pressing ring 50 can not only adjust the warping problem of the substrate 40 , but also after the package structure 100 is heated, the deformations of the heat sink 20 and the substrate 40 do not affect each other, so as to avoid the influence of stress between the heat sink 20 and the substrate 40 . .

In addition, if the substrate 40 provided with the die ring 50 is bonded to the bare chip structure 10 that has been bonded to the heat sink 20 . By setting a gap between the die ring 50 and the heat sink 20 , the influence of the stress between the heat sink 20 and the die ring 50 on the bonding effect or the bonding reliability of the bare chip structure 10 and the substrate 40 can be reduced.

In other embodiments, as shown in FIG. 11 c , the fin ring 50 is connected to the heat sink 20 .

In this way, the pressing ring 50 can not only adjust the warping problem of the substrate 40 , but also can support the heat sink 20 to improve the stability of the package structure 100 .

In another possible embodiment, as shown in FIG. 12 a , the fin ring 50 is located on the periphery of the heat sink 20 .

That is to say, as shown in FIG. 12 b , the pressing ring 50 is arranged around the heat sink 20 in one circle.

In some configurations, the substrate 40 has a larger area and has a larger degree of warpage. The greater the stiffness of the pressing ring 50 is, the better the flattening effect on the substrate 40 is. Since the stiffness of the pressing ring 50 is related to the thickness of the pressing ring 50 along the direction perpendicular to the substrate 40 , by disposing the pressing ring 50 on the periphery of the heat sink 20 , it is not necessary to limit the thickness of the pressing ring 50 . The thickness of the pressing ring 50 is adjusted according to the area of the substrate 40 to adjust the stiffness of the pressing ring 50 , so as to solve the problem of warpage of the substrate 40 to the greatest extent.

Based on this, in some embodiments, as shown in FIG. 12 a , along the direction perpendicular to the substrate 40 , the thickness h1 of the pressing ring 50 is greater than the gap h2 between the heat sink 20 and the substrate 40 (in FIG. 12 a , the pressing ring 50 is flush with the heat sink 20 as an example for illustration).

In some embodiments, as shown in FIG. 12 a , along a direction parallel to the substrate 40 , there is a gap between the pressing ring 50 and the heat sink 20 . That is, the fin ring 50 and the heat sink 20 are not in contact.

Regarding the structure of the tableting ring 50 , from a top view, in some embodiments, as shown in FIG. 12 b , the widths of the tableting ring 50 are equal everywhere. Of course, as shown in FIG. 13 , the widths of the tableting rings 50 may not be equal.

It can be understood that the embodiment of the present application does not limit the tableting ring 50 to be a rectangular ring, a circular ring, a triangular ring or other rings, and FIG. 13 only illustrates the tableting ring 50 being a rectangular ring as an example.

Based on this, as shown in FIG. 14 , the preparation method of the package structure 10 further includes:

S3000 , connecting the pressing ring 50 to the substrate 40 .

The die ring 50 is disposed on the surface of the substrate 40 facing the bare chip structure 10 . The pressing ring 50 and the substrate 40 may be connected by an adhesive layer.

S4000 , bonding the substrate 40 and the bare chip structure 10 on the active surface a1 of the bare chip structure 10 .

That is, the side of the substrate 40 provided with the die ring 50 is bonded to the bare chip structure 10 .

The execution order of steps S300 and S3000 is not limited. After steps S300 and S3000 are executed, step S4000 may be executed.

In the package structure 100 provided by the embodiment of the present application, the first silicide bonding layer 22 is provided on the heat sink body 21 , and then the heat sink body 21 and the bare chip structure 10 are bonded through a bonding process. There is no heat-dissipating adhesive layer in the package structure 100 , which completely eliminates the problem in the related art that the adhesiveness of the heat-dissipating fin 20 and the bare chip structure 10 is reduced due to peeling of the heat-dissipating adhesive layer. And the first silicide bonding layer 22 and the silicon substrate 111 of the first bare chip 11 in the bare chip structure 10 are bonded by molecular bonding, the connection is reliable, and the factors such as temperature and package warpage affect the first silicide. The bonding degree between the bonding layer 22 and the bare chip structure 10 has little effect, the bonding degree between the heat sink 20 and the bare chip structure 10 is close to 100%, and the stable heat dissipation capability is guaranteed, thereby ensuring the heat dissipation effect.

Embodiment 2

The second embodiment is the same as the first embodiment in that the structure of the heat sink 20 is the same.

The difference between the second embodiment and the first embodiment is that the bare chip structure 10 includes a plurality of stacked bare chips, and adjacent bare chips are bonded.

An embodiment of the present application provides a package structure 100 . As shown in FIG. 15 a , the package structure 100 includes a bare chip structure 10 . The bare chip structure 10 has an active surface a1 and a back surface b1 disposed opposite to each other.

The bare chip structure 10 includes a plurality of stacked bare chips ( FIG. 15 a takes the bare chip structure 10 including a first bare chip 11 and a second bare chip 13 as an example for illustration).

As shown in FIG. 15a, the bare chip structure includes a first bare chip 11 and a second bare chip 13, the first bare chip 11 and the second bare chip 13 form a vertical stack structure, and the active surface a3 of the first bare chip 11 and the The backside b4 of the two bare chips 13 is bonded.

Based on this structure, the active surface a4 of the second bare chip 13 is used as the active surface a1 of the bare chip structure 10 , and the back surface b3 of the first bare chip 11 is used as the back surface b1 of the bare chip structure 10 .

Regarding the sizes of the first bare chip 11 and the second bare chip 13, in a possible embodiment, as shown in FIG. 15a, the sizes of the first bare chip 11 and the second bare chip 13 are equal.

Based on the bare chip structure 10 shown in FIG. 15a, in a possible embodiment, as shown in FIG. 4b, the preparation method of the bare chip structure 10 includes:

S10 , as shown in FIG. 15 b , grinding and thinning the back surface b2 of the wafer layer 113 .

It can be understood that the bare chip structure 10 includes a first bare chip 11 and a second bare chip 13 that are stacked in layers. Therefore, the wafer layer 113 includes multiple layers of wafers, and adjacent wafers are bonded to each other. ), the scribe lines of the multilayer wafers overlap. The back surface b2 of the wafer layer 113 is opposite to the active surface a2 of the wafer layer 113 .

Grinding and thinning the back surface b2 of the wafer layer 113 is equivalent to grinding and thinning the back surface of the wafer located in the outermost layer.

S20 , as shown in FIG. 15 b , polishing the back surface b2 of the wafer layer 113 .

S30 , as shown in FIG. 15 b , the wafer layer 113 is separated along the dicing lines to obtain the bare chip structure 10 .

In a possible embodiment, as shown in FIG. 16a, the sizes of the first bare chip 11 and the second bare chip 13 are not equal.

Based on the bare chip structure 10 shown in FIG. 16a, in a possible embodiment, as shown in FIG. 4b, the preparation method of the bare chip structure 10 includes:

S10 , as shown in FIG. 16 b , grinding and thinning the back surface b2 of the wafer layer 113 .

It can be understood that the bare chip structure 10 includes a first bare chip 11 and a second bare chip 13 that are stacked and arranged, and the sizes of the first bare chip 11 and the second bare chip 13 are not equal. Therefore, the wafer layer 113 includes a layer of wafer and a second die to wafer 13 bonded to the wafer.

Grinding and thinning the back surface b2 of the wafer layer 113 is equivalent to grinding and thinning the back surface of the wafer.

S20 , as shown in FIG. 16 b , polishing the back surface b2 of the wafer layer 113 .

S30 , as shown in FIG. 16 b , the wafer layers 113 are separated along the dicing lines to obtain the bare chip structure 10 .

The package structure 100 further includes a heat sink 20 , a substrate 40 , and a die ring 50 . For the structures of the heat sink 20 , the substrate 40 , and the pressing ring 50 , reference may be made to the relevant descriptions in the first embodiment, which will not be repeated here.

Wherein, when the bare chip structure 10 includes the stacked first bare chip 11 and the second bare chip 13, the silicon substrate 111 of the first bare chip 11 is bonded to the first silicide bonding layer 22, and the second bare chip 11 is bonded to the first silicide bonding layer 22. The active surface a4 of the chip 13 is bonded to the substrate 40 .

In the present embodiment, the bare chip structure 10 includes the first bare chip 11 and the second bare chip 13 which are arranged in layers. In this way, there is no need to bond the two bare chips to the substrate 40, so that the bare chip structure 10 can be miniaturized and reduced in size. integration, thereby reducing the area of the package structure 100 .

Embodiment 3

The third embodiment is the same as the first embodiment and the second embodiment in that the structure of the heat sink 20 is the same.

The difference between Embodiment 3 and Embodiment 1 and Embodiment 2 is that: the backside b1 of the bare chip structure 10 is covered with a second silicide bonding layer 12 .

An embodiment of the present application provides a package structure 100 . As shown in FIGS. 17 a and 17 b , the package structure 100 includes a bare chip structure 10 . The bare chip structure 10 includes a first bare chip 11 and a second silicide bonding layer 12 covering the silicon substrate 111 of the first bare chip 11 . The first silicide bonding layer 22 is bonded to the second silicide bonding layer 12 .

That is, the first bare chip 11 and the first silicide bonding layer 22 are bonded through the second silicide bonding layer 12 .

Since the heat dissipation effect is related to both the heat dissipation material and the heat dissipation path, on the basis of satisfying the stable bonding between the second silicide bonding layer 12 and the first silicide bonding layer 22, the thickness of the second silicide bonding layer 12 The thinner the better.

In some embodiments, the thickness of the second silicide bonding layer 12 is 0.3 μm-2 μm. For example, the thickness of the second silicide bonding layer 12 is 0.5 μm, 0.7 μm, 0.8 μm, 1 μm, 1.3 μm, 1.5 μm, 1.7 μm, or the like.

The material of the second silicide bonding layer 12 is not limited, and the material of the second silicide bonding layer 12 may be a metal silicide or a non-metal silicide. In some embodiments, the material of the second silicide bonding layer 12 includes, for example, one of silicon nitride (SiN), silicon carbide (SiC), and silicon oxide (SiO 2 ).

Based on the bare chip structure 10 shown in FIG. 17a and FIG. 17b, as shown in FIG. 18, the preparation method of the bare chip structure 10 includes:

S1 , as shown in FIG. 19 , grinding and thinning the back surface b2 of the wafer layer 113 .

The wafer layer 113 here may be any one of the wafer layers 113 shown in the first embodiment or the second embodiment, and the wafer layer 113 in FIG. 19 is only for illustration.

S2 , forming a second silicide film 121 on the back surface b2 of the wafer layer 113 .

Wherein, the second silicide film 121 may be formed by, for example, a PECVD process.

S3 , polishing the surface of the second silicide film 121 away from the wafer layer 113 .

S4 , separating the wafer layers 113 along the dicing lines to obtain the bare chip structure 10 .

Wherein, in the case where the bare chip structure 10 includes the second silicide bonding layer 12, the second silicide bonding layer 12 is bonded with the first silicide bonding layer 22, and the heat sink body 21 is bonded by the first silicide bonding The bonding layer 22 and the second silicide bonding layer 21 are bonded to the first bare chip 11 .

In this embodiment, the bare chip structure 10 includes a second silicide bonding layer 12 , and the second silicide bonding layer 12 can further block metal ions (eg, copper ions) in the heat sink body 21 from diffusing into the bare chip structure 10 . In this way, it is difficult for metal ions to diffuse to the silicon substrate 111 of the first bare chip 11 in the bare chip structure 10 , so that the performance of the transistors on the silicon substrate 111 is prevented from being affected due to the conduction of the silicon substrate, thereby affecting the first bare chip. 11 performance issues.

The above are only specific embodiments of the present application, but the protection scope of the present application is not limited to this. should be covered within the scope of protection of this application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

A package structure, characterized in that, comprising:

a bare chip structure, the bare chip structure includes a first bare chip; the first bare chip includes a silicon substrate;

a heat sink, including a heat sink body and a first silicide bonding layer disposed on the heat sink body;

Wherein, the first silicide bonding layer is bonded with the silicon substrate.
The package structure according to claim 1, wherein the bare chip structure further comprises a second silicide bonding layer covering the surface of the silicon substrate, the first silicide bonding layer and the first silicide bonding layer The disilicide bonding layer is bonded.
The package structure according to claim 1 or 2, wherein the first silicide bonding layer covers the surface of the heat sink body.
The package structure according to any one of claims 1-3, wherein a slit is provided on the heat sink body.
The package structure according to claim 4, wherein the region where the gap is provided on the heat sink body overlaps the region where the first silicide bonding layer and the silicon substrate are bonded.
The package structure according to claim 4 or 5, wherein the heat sink body is provided with a plurality of the slits; a plurality of the slits intersect at the center of the heat sink body;

or,

The heat sink body includes an outer ring and a plurality of extension bars extending inward along the inner edge of the outer ring, and the gap is provided between adjacent extension bars;

or,

The gap is located in the center of the heat sink body, and the gap is a closed figure.
The package structure according to any one of claims 1-6, wherein the first silicide bonding layer and the silicon substrate are bonded by a direct bonding process.
The package structure according to any one of claims 1-7, wherein the material constituting the first silicide bonding layer comprises one of SiN, SiC, and SiO2.
The package structure according to any one of claims 1-8, wherein the thickness of the first silicide bonding layer is 0.3-2 μm.
The package structure according to any one of claims 1-9, wherein the bare chip structure further comprises a second bare chip, the first bare chip and the second bare chip form a vertical stack structure, so The active surface of the first bare chip is bonded to the back surface of the second bare chip.
The package structure according to any one of claims 1-10, wherein the package structure further comprises a substrate, and the substrate is bonded to the active surface of the bare chip structure.
The package structure according to claim 11, wherein the package structure further comprises a pressing ring, and the pressing ring is disposed on a surface of the substrate facing the bare chip structure;

The die ring is located at the periphery of the bare chip structure.
The package structure according to claim 12, wherein,

the sheet pressing ring is located between the heat sink and the base plate;

or,

The sheet pressing ring is located on the periphery of the heat sink.
The package structure according to claim 12 or 13, wherein a gap is formed between the heat sink and the pressing ring.
A preparation method of an encapsulation structure, comprising:

forming a bare chip structure; the bare chip structure includes a first bare chip; the first bare chip includes a silicon substrate;

forming a heat sink; the heat sink includes a heat sink body and a first silicide bonding layer formed on the heat sink body;

The first silicide bonding layer is bonded to the silicon substrate.
The method for manufacturing a package structure according to claim 15, wherein forming the heat sink comprises:

A first silicide film is formed on a heat dissipation plate; the heat dissipation plate includes a plurality of cutting lines that intersect horizontally and vertically;

polishing the surface of the first silicide film away from the heat sink;

The cooling plate is cut along the cutting line to obtain the cooling fins.
The method for preparing a package structure according to claim 15 or 16, wherein the bare chip structure comprises a first bare chip;

Forming the bare chip structure includes:

polishing the back surface of the wafer layer; the wafer layer includes a plurality of dicing lines intersecting horizontally and vertically;

The wafer layers are separated along the dicing lines to obtain the bare chip structure.
The method for preparing a package structure according to claim 17, wherein before polishing the backside of the wafer layer, the method further comprises:

The backside of the wafer layer is ground and thinned.
The method for manufacturing a package structure according to claim 15 or 16, wherein the bare chip structure comprises a first bare chip and a second silicide bonding layer covering a silicon substrate of the first bare chip ;

Forming the bare chip structure includes:

A second silicide film is formed on the backside of the wafer layer; the wafer layer includes a plurality of scribe lines intersecting horizontally and vertically;

polishing the surface of the second silicide film away from the wafer layer;

The wafer layers are separated along the dicing lines to obtain the bare chip structure.
The method for preparing a package structure according to claim 19, wherein before forming the second silicide film on the backside of the wafer layer, the method further comprises:

The backside of the wafer layer is ground and thinned.
The method for preparing a package structure according to any one of claims 15-20, wherein a direct bonding process is used to bond the first silicide bonding layer to the silicon substrate.
The method for manufacturing a package structure according to claim 16, wherein the bare chip structure and the first silicide film are bonded before cutting the heat dissipation plate along the cutting line.
The preparation method of the packaging structure according to any one of claims 15-22, wherein the preparation method of the packaging structure further comprises:

After the first silicide bonding layer and the silicon substrate are bonded, the substrate and the bare chip structure are bonded on the active surface of the bare chip structure.
The preparation method of the packaging structure according to claim 23, wherein the preparation method of the packaging structure further comprises:

Before bonding the substrate and the silicon base, a pressing ring is connected to the substrate; wherein, the pressing ring is arranged on the surface of the substrate facing the bare chip structure.
An electronic device, characterized in that it comprises a circuit board and the packaging structure according to any one of claims 1-14;

The package structure is bonded to the circuit board.