WO2023274031A1

WO2023274031A1 - Stacked chip and preparation method therefor

Info

Publication number: WO2023274031A1
Application number: PCT/CN2022/100806
Authority: WO
Inventors: 韩彦武; 郭立; 薛小飞; 龙晓东
Original assignee: 西安紫光国芯半导体有限公司
Priority date: 2021-07-02
Filing date: 2022-06-23
Publication date: 2023-01-05
Also published as: CN113314510A

Abstract

Disclosed in the present application are a stacked chip and a preparation method therefor. The stacked chip comprises at least two mutually stacked chip units, wherein a first support column and a first conductive column are arranged between two adjacent chip units; the first support column is used for generating a support stress for the chip units; and the first conductive column is used for conducting a line on the two connected chip units. Therefore, the problem of a chip function failure occurring due to chip being easy to crack in the existing chip stacking manner can be solved.

Description

A kind of stacked chip and preparation method

This application claims the priority of the Chinese patent application with application number 202110753141.0, the content of which is incorporated in this application by reference.

【Technical field】

The present application relates to the technical field of semiconductors, in particular to a stacked chip and a preparation method.

【Background technique】

In recent years, with the continuous upgrading of consumer products, the chip market has higher and higher requirements for the performance of chip components, and at the same time, there is an increasing demand for the miniaturization of chip components. At present, the use of 3D IC (three dimensional Integrated Circuit Chip, three-dimensional chip) technology can stack two chips with different functions face to face to form a functional system, which can reduce the overall area of the chip. Size requirements.

However, in the existing chip stacking method, cracking of the chips is prone to occur, resulting in functional failure of the chips.

【Content of invention】

The embodiments of the present application provide a stacked chip and a preparation method thereof, which can improve the existing chip stacking method, which is prone to chip cracking leading to chip function failure.

According to the first aspect of the embodiments of the present application, a stacked chip is provided, including: at least two chip units stacked on each other;

A first support column and a first conductive column are arranged between two adjacent chip units;

The first support column is used to generate support stress on the chip unit, and the first conductive column is used to conduct the circuit on the two connected chip units.

In a feasible implementation manner, the circuit side of the chip unit includes a circuit area and a non-circuit area, and the circuit area includes the circuit;

The contact area between the first conductive pillar and the chip unit is located in the circuit area;

The contact area between the first support pillar and the chip unit is located in the non-circuit area.

In a feasible implementation manner, the first supporting pillar is arranged on a virtual dividing line of the chip unit, wherein the virtual dividing line is obtained by dividing the chip unit into equal parts, and the virtual dividing line The dividing line is located in the non-line area.

In a feasible implementation manner, the first support columns arranged on the virtual dividing line are arranged at equal intervals.

In a feasible implementation manner, it also includes a second conductive column;

The second conductive column is arranged between two non-adjacent chip units, the second conductive column is used to conduct the lines of the two connected chip units, and the second conductive column The contact area between the pillar and the chip unit is located in the wiring area.

In a feasible implementation manner, it also includes a second support column;

The second support column is arranged between two non-adjacent chip units, the second support column is used to generate support stress on the chip unit, and the second support column and the chip unit The contact area is located in the non-line area.

In a feasible implementation manner, it includes: chip units on the Nth layer, chip units on the N+1 layer and chip units on the N+2 layer stacked in sequence, where N is a natural number greater than 0, and the Nth layer The line side of the chip unit is opposite to the line side of the N+1th layer chip unit, and the line side of the N+2th layer chip unit is opposite to the line side of the N+2th layer chip unit Relative setting on the line side;

The first support pillar and the first conductive pillar are arranged between the Nth layer chip unit and the N+1th layer chip unit;

The first supporting column is arranged between the N+1th layer chip unit and the N+2th layer chip unit;

The second conductive column is disposed between the Nth layer chip unit and the N+2th layer chip unit.

In a feasible implementation manner, the non-circuit area of the chip unit on the N+1th layer is provided with a first through hole;

The second conductive pillar disposed between the Nth layer chip unit and the N+2th layer chip unit passes through the first through hole.

In a feasible implementation manner, it further includes a third conductive pillar, and the third conductive pillar is arranged between the chip unit on the N+1th layer and the chip unit on the N+2th layer;

The circuit area of the N+1th layer chip unit is provided with a second through hole, and the second through hole is electrically connected to the circuit on the N+1th layer chip unit;

The third conductive column passes through the second through hole and is electrically connected with the second through hole.

In a feasible implementation manner, materials of the first support pillar and the first conductive pillar include metal materials.

In a feasible implementation manner, the first support pillar and the first conductive pillar are connected to a corresponding one of the chip units through metal bonding.

The second aspect of the embodiment of the present application provides a method for preparing a stacked chip, which is applied to the stacked chip as described in the first aspect, and the method includes:

setting a first support post and a first conductive post on one side of the chip unit on the first layer;

The second-layer chip unit is arranged opposite to the first-layer chip unit, wherein the first support column and the first conductive column are located between the first-layer chip unit connection and the second-layer chip unit In between, the first support column is used to generate support stress on the chip unit, and the first conductive column is used to conduct the circuit on the two connected chip units.

In a feasible implementation manner, before the step of arranging the first support column and the first conductive column on one side of the chip unit on the first layer, it further includes:

An integrated circuit is arranged on one side of the first layer chip unit to form the line side of the first layer chip unit, and an integrated circuit is arranged on one side of the second layer chip unit to form the second layer chip The line side of the unit, wherein the line side of the first layer chip unit includes a first line area and a first non-line area, and the line side of the second layer chip unit includes a second line area and a second line area Second non-line area;

The step of arranging the first support column and the first conductive column on one side of the chip unit on the first layer includes:

The first conductive column and the first supporting column are arranged on the line side of the first layer chip unit, wherein the contact area between the first conductive column and the first layer chip unit is located at the In the first circuit area, the contact area between the first support pillar and the first layer chip unit is located in the first non-circuit area;

The step of arranging the second-layer chip unit relative to the first-layer chip unit includes:

The second-layer chip unit is arranged opposite to the first-layer chip unit, wherein the contact area between the first conductive column and the second-layer chip unit is located in the second line area, and the first The contact area between the support pillar and the chip unit on the second layer is located in the second non-circuit area.

In a feasible implementation manner, the step of arranging the first conductive pillar and the first support pillar on the line side of the first layer chip unit includes:

The first conductive column, the first support column, the second conductive column and/or the second support column are arranged on the line side of the first layer chip unit, wherein the second conductive column is connected to the The contact area of the first-layer chip unit is located in the first circuit area, and the contact area between the second support pillar and the first-layer chip unit is located in the first non-circuit area;

Before the step of arranging the second-layer chip unit relative to the first-layer chip unit, it also includes:

An integrated circuit is arranged on one side of the third-layer chip unit to form the line side of the third-layer chip unit, wherein the line side of the third-layer chip unit includes a third line area and a third non-line area ;

A first through hole and/or a third through hole are arranged on the second layer chip unit, wherein the first through hole is arranged in the second circuit area, and the third through hole is arranged in the first through hole Second non-line area;

After the step of arranging the second-layer chip unit relative to the first-layer chip unit, it further includes:

The second-layer chip unit is arranged opposite to the third-layer chip unit, wherein the second conductive column is located between the first-layer chip unit and the third-layer chip unit, and/or, The second support column is located between the first layer chip unit and the third layer chip unit, the second conductive column penetrates the first through hole, and/or, the second support The post is passed through the third through hole.

The stacked chip and the preparation method provided in the embodiment of the present application aim at thinning the top chip unit on the top due to packaging requirements during the stacking process of the stacked chip. The strength of the thinned top chip unit is reduced, and the first conductive The posts are used to conduct the lines on the two connected chip units. The setting of the first conductive posts needs to be set according to the position of the lines on the chip units and the electrical connection requirements. Therefore, the distribution of the first conductive posts is in many cases It is uneven, and it is easy to cause cracking or fragmentation of the stacked chip, resulting in the failure of the function of the chip. According to the research on the trace of cracking or the reduction of fragmentation, it is found that the origin of cracking or the point of concentration of crushing stress is usually at or near the position of the first conductive column. Therefore, it can be found that the uneven distribution of the first conductive pillars will lead to different stresses on the connected chip units, and the strength of the superimposed top chip unit will decrease after thinning, and it is very easy to cause chip cracking or cracking due to uneven stress. Broken, resulting in the failure of the function of the chip unit and stacked chips. The stacked chip provided by the embodiment of the present application can generate supporting stress on the contacting chip unit by setting the first support column, which can assist the first conductive column to support the chip unit, and can make the first conductive column and the first support column integral The distribution tends to be uniform, which can improve the uneven stress on the connected chip units easily caused by the first conductive pillar, so as to solve the problem that the existing stacked chips are prone to cracking or breaking.

【Description of drawings】

FIG. 1 is a schematic structural diagram of a stacked chip provided in an embodiment of the present application;

Fig. 2 is a cross-sectional view along A-A' of a stacked chip provided by the embodiment of the present application;

FIG. 3 is a schematic structural diagram of another stacked chip provided by the embodiment of the present application;

FIG. 4 is a schematic structural diagram of yet another stacked chip provided in an embodiment of the present application;

FIG. 5 is a schematic structural diagram of yet another stacked chip provided in an embodiment of the present application;

FIG. 6 is a schematic diagram of the position of a virtual dividing line of stacked chips provided by the embodiment of the present application;

FIG. 7 is a schematic diagram of the position of another virtual dividing line of a stacked chip provided by the embodiment of the present application;

FIG. 8 is a side view of a stacked chip provided by an embodiment of the present application;

FIG. 9 is a schematic flow chart of a method for manufacturing stacked chips provided in an embodiment of the present application.

【detailed description】

In order to better understand the technical solutions provided by the embodiments of this specification, the technical solutions of the embodiments of this specification will be described in detail below through the drawings and specific examples. The detailed description of the technical solutions of the embodiments is not a limitation to the technical solutions of this specification. In the case of no conflict, the embodiments of this specification and the technical features in the embodiments can be combined with each other.

In this document, relational terms such as first and second etc. are used only to distinguish one entity or operation from another without necessarily requiring or implying any such relationship between these entities or operations. Actual relationship or sequence. Furthermore, the term "comprises", "comprises" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article or apparatus comprising a set of elements includes not only those elements, but also includes elements not expressly listed. other elements of or also include elements inherent in such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article or apparatus comprising said element. The term "two or more" includes two or more cases.

In recent years, with the continuous upgrading of consumer products, the chip market has higher and higher requirements for the performance of chip components, and at the same time, there is an increasing demand for the miniaturization of chip components. At present, using 3D IC (which can be called stacked chip) technology can stack two chips with different functions face to face, or stack multiple chips to form a functional system, which can be called a three-dimensional chip. This functional system (three-dimensional chip) can reduce the overall area of the chip, and while taking into account the performance, it also meets the demand for small size. However, in the existing chip stacking method, cracking of the chips is prone to occur, resulting in functional failure of the chips.

In view of this, the present application provides a stacked chip and a preparation method, which can improve the existing chip stacking method, which is prone to chip cracking and leads to chip function failure.

The first aspect of the embodiment of the present application provides a stacked chip. FIG. 1 is a schematic structural diagram of a stacked chip provided in the embodiment of the present application, and FIG. 2 is a cross-section along A-A' of a stacked chip provided in the embodiment of the present application. picture. Referring to FIG. 1 and FIG. 2 , a stacked chip provided by an embodiment of the present application includes: at least two chip units 100 stacked on each other. A first support pillar 300 and a first conductive pillar 200 are disposed between two adjacent chip units 100 . The first support column 300 is used to generate supporting stress on the chip unit 100 , and the first conductive column 200 is used to conduct the circuit on the two connected chip units 100 . It should be noted that the chip unit 100 here may be a wafer (wafer), or a chip (chip) after the wafer has been cut.

Exemplarily, the stacked chip shown in FIG. 2 includes two chip units, namely a bottom chip unit 101 and a top chip unit 102. The top chip unit 102 may be a thinned chip unit, which is not specifically limited in this application. Continuing to refer to FIG. 2 , the first support pillar 300 and the first conductive pillar 200 are disposed between the bottom chip unit 101 and the top chip unit 102 . The stacked chip shown in FIG. 2 includes two chip units, which is only schematic, and may also include more than two chip units, which is not specifically limited in this application. The chip unit 100 shown in FIG. 1 is a rectangle, and may also be a circle, an ellipse or a polygon, which is not specifically limited in this application.

In the stacked chips provided in the embodiment of the present application, during the stacking process of the stacked chips, the top chip unit 102 on the top will be thinned due to packaging requirements. The strength of the thinned top chip unit 102 is reduced, and the first conductive column 200 is used to conduct the lines on the two connected chip units 100. The setting of the first conductive pillars 200 needs to be set according to the position of the lines on the chip units 100 and the electrical connection requirements. Therefore, the distribution of the first conductive pillars 200 is In many cases, it is uneven, which is likely to cause cracks or breakage of the stacked chips, resulting in chip function failure. Research on the traces of cracking or broken restoration has found that the origin of cracking or the point of concentration of broken stress is usually at the first conductive pillar 200. location or nearby. Therefore, it can be found that the uneven distribution of the first conductive pillars 200 will lead to different stresses on the connected chip units 100, and the strength of the superimposed top chip unit 102 will decrease after thinning, and it is very easy to occur due to uneven stress. The chip is cracked or broken, thereby causing the function of the chip unit 100 and stacked chips to fail.

The stacked chip provided by the embodiment of the present application can generate support stress on the contacting chip unit 100 by setting the first support column 300, which can assist the first conductive column 200 to support the chip unit, and can make the first conductive column 200 and the second conductive column 200 The overall distribution of the supporting pillars 300 tends to be even, which can improve the uneven stress on the connected chip units 100 easily caused by the first conductive pillars 200, so as to solve the problem that the existing stacked chips are prone to cracking or breaking.

In a feasible implementation manner, FIG. 3 is a schematic structural diagram of another stacked chip provided in the embodiment of the present application. As shown in FIG. 3 , the first support column 300 can also be arranged on the edge of the chip unit 100. Since there is a difference in the stress between the edge and the center of the chip unit 100, setting the first support column 300 on the edge of the chip unit 100 can reduce the stress on the edge of the chip unit 100. More support at the edges to relieve uneven stress.

In a feasible implementation manner, FIG. 4 is a schematic structural diagram of another stacked chip provided in the embodiment of the present application. As shown in FIG. 4 , the first support column 300 provided in the central area of the chip unit 100 may include a combination of elongated columns and square columns, similar to the shape of "dotted line", which can increase the supporting force and increase the stress. Auxiliary effect.

The arrangements of the first support pillars 300 and the first conductive pillars 200 in FIG. 1 , FIG. 3 and FIG. 4 are only schematic, and are not intended to be specific limitations of the present application.

In a feasible implementation manner, FIG. 5 is a schematic structural diagram of another stacked chip provided in the embodiment of the present application. As shown in FIG. 5 , the line side of the chip unit 100 includes a line area 110 and a non-line area 120 , and the line area 110 includes lines. The chip unit 100 may have circuits fabricated on one side, and the side on which the circuits are fabricated may be referred to as the circuit side. The circuit on the chip unit 100 is the integrated circuit integrated on the circuit side of the chip unit 100. The circuits on the chip unit 100 with different functions are also different, and the circuit distribution is also different. Since the circuit is usually more complicated, the circuit is not shown in FIG. 5 . Since the first conductive pillar 200 is used to conduct the circuit on the connected chip unit 100 , the contact area between the first conductive pillar 200 and the chip unit 100 is located in the circuit area 110 . The contact area between the first support pillar 300 and the chip unit 100 is located in the non-circuit area 120 . The line area 110 shown in FIG. 5 is just an exemplary illustration.

In the stacked chip provided by the embodiment of the present application, since the first conductive pillars 200 are usually concentrated in the circuit area, and are used to conduct the circuit between the two chip units 100, the non-circuit area 120 usually has no support to provide supporting stress. Therefore, the second A support column 300 is arranged in the non-circuit area 120, which can make the overall distribution of the first conductive column 200 and the first support column 300 tend to be uniform, and can improve the connection between the first conductive column 200 and the connected chip unit 100. Uneven stress to solve the problem that existing stacked chips are prone to chip cracking or chipping.

In a feasible implementation manner, FIG. 6 is a schematic diagram of the position of a virtual dividing line of a stacked chip provided in the embodiment of the present application; FIG. 7 is another virtual dividing line of a stacked chip provided in the embodiment of the present application. location diagram.

As shown in FIG. 6 , by dividing the chip unit 100 into equal parts, a virtual dividing line 400 (dashed line shown in FIG. 6 ) can be obtained. The first support pillar 300 is disposed on the virtual dividing line 400 of the chip unit 100 . As shown in Figure 6, there is a situation that the virtual dividing line 400 may partially fall in the line area 110. In the process of determining the virtual dividing line 400, if the virtual dividing line 400 falls in the line area 110, it will cause part of the first support In the case where the column 300 is arranged in the wiring area 110 , the first supporting column 300 may cause damage to the wiring in the wiring area 110 . In order to prevent the first support column 300 from affecting the line, it is necessary to fine-tune the position of the virtual dividing line 400. Specifically, the part of the virtual dividing line 400 that falls within the line area 110 can be moved to the nearest non-line area 120, At the same time, it can be evaluated as a whole whether each divided area is equal. By moving the position of part of the virtual dividing line 400 again, each divided area tends to be equal. This is achieved on the basis that the virtual dividing line 400 is located in the non-line area 120. The greatest degree of equalization, where equalization can be the same area.

The distribution positions of the virtual dividing lines 400 shown in FIG. 7 can be regarded as fine-tuned so that the virtual dividing lines 400 are located in the non-line area 120 and each dividing area tends to be equal. The position of the virtual dividing line 400 in FIG. 7 is only schematic, and is not intended as a specific limitation of the present application.

In the stacked chip provided by the embodiment of the present application, the chip unit 100 is divided into equal parts by introducing a virtual dividing line 400. If the virtual dividing line 400 falls into the line area 110, fine-tune the virtual dividing line 400 to avoid the line area. 110. The virtual dividing line 400 may be further adjusted so that each divided area tends to be equal. Setting the first support pillars 300 on the adjusted virtual dividing line 400 can make the first supporting pillars 300 distributed on the virtual dividing line 400 support the chip unit 100 more uniformly and contribute more uniformly to the supporting stress.

In a feasible implementation manner, as shown in FIG. 6 , the virtual dividing line 400 partially falls within the line area 110 , then the first support column 300 may be disposed on the virtual dividing line located in the non-line area 120 . Since the first conductive column 200 is usually arranged in the line area 110, if the virtual dividing line 400 falls in the line area 110, no adjustment is made to the section of the virtual dividing line 400, and the position of the section of the virtual dividing line 400 is not provided with the first conductive column. Support column 300 . The first support column 300 is arranged on the virtual dividing line located in the non-line area 120, which can make the overall distribution of the first conductive column 200 and the first support column 300 tend to be uniform, and can improve the connection between the first conductive column 200 and the phase connection. The uneven stress on each part of the chip unit 100 can solve the problem that the existing stacked chips are easy to crack or break.

In a feasible implementation manner, the first support columns arranged on the virtual dividing line are arranged at equal intervals. The first support pillars arranged at equal intervals can provide uniformly distributed stress support, so that the overall distribution of the first conductive pillars 200 and the first support pillars 300 tends to be uniform, and can improve the resistance of the first conductive pillars 200 to the connected chip units. 100, the stress is not uniform everywhere, so as to solve the problem that the existing stacked chips are prone to chip cracking or breaking.

In a feasible implementation manner, FIG. 8 is a side view of a stacked chip provided in the embodiment of the present application. Exemplarily, as shown in FIG. 8, a stacked chip may include three chip units 100, which are respectively a first-layer chip unit 103, a second-layer chip unit 104, and a third-layer chip unit 105. The second-layer chip unit 104 is located at A second conductive column 500 is also provided between the first-layer chip unit 103 and the third-layer chip unit 105 , and between non-adjacent first-layer chip units 103 and third-layer chip units 105 . The second conductive column 500 is used to conduct the circuit on the connected first layer chip unit 103 and the third layer chip unit 105, and the second conductive column 500 is in contact with the first layer chip unit 103 and the third layer chip unit 105 Areas are located in the line area.

In a feasible implementation manner, the stacked chip includes sequentially stacked Nth layer chip units, N+1th layer chip units, and N+2th layer chip units, wherein N is a natural number greater than 0, and the Nth layer chip The line side of the unit is set opposite to the line side of the N+1th layer chip unit, and the line side of the Nth layer chip unit is set opposite to the line side of the N+2th layer chip unit; the Nth layer chip unit and the N+1th layer The first support column and the first conductive column are arranged between the chip units of the layer; the first support column is arranged between the chip unit of the N+1 layer and the chip unit of the N+2 layer; the chip unit of the N layer and the N+ A second conductive column is arranged between the two-layer chip units.

Continuing to refer to FIG. 8 , for example, when N=1, the Nth layer chip unit, the N+1th layer chip unit and the N+2th layer chip unit are the first layer chip unit 103 shown in FIG. 8 , The second layer chip unit 104 and the third layer chip unit 105 . The circuit side of the first-layer chip unit 103 is opposite to the circuit side of the second-layer chip unit 104 , which facilitates the arrangement of the first conductive pillar 200 . The circuit side of the first-layer chip unit 103 is opposite to the circuit side of the third-layer chip unit 105 , which facilitates the arrangement of the second conductive pillar 500 . The non-circuit area of the second-layer chip unit 104 may be provided with a first through hole 510 , and the second conductive column 500 disposed between the first-layer chip unit 103 and the third-layer chip unit 105 penetrates through the first through hole 510 .

In the stacked chip provided by the embodiment of the present application, by setting the second conductive column 500 through the first through hole 510, the circuits of the first-layer chip unit 103 and the third-layer chip unit 105 can be electrically connected together, and multiple Chip unit stacking.

Exemplarily, continuing to refer to FIG. 8, a first support column 300 may also be provided between the second-layer chip unit 104 and the third-layer chip unit 105, The position of the first support column 300 can correspond to the position of the first support column 300 provided between the first layer chip unit 103 and the second layer chip unit 104, which can play the role of stress balance without causing additional Uneven stress.

In a feasible implementation manner, for example, continuing to refer to FIG. 8 , the stacked chips further include a second support pillar 600 . The second support column 600 is disposed between the non-adjacent first-layer chip units 103 and the third-layer chip unit 105 , and the second support column 600 is used to support the first-layer chip unit 103 and the third-layer chip unit 105 Stress, the contact area between the second support pillar 600 and the first-layer chip unit 103 and the third-layer chip unit 105 is located in the non-circuit area.

In a feasible implementation manner, for example, continuing to refer to FIG. 8 , a third through hole 610 is provided in the non-circuit area of the second-layer chip unit 104, and the second support column 600 can pass through the third through hole. within 610.

In the stacked chip provided by the embodiment of the present application, by setting the second support column 600 through the third through hole 610, the second support column 600 can exert support stress on the first-layer chip unit 103 and the third-layer chip unit 105 The role of balance.

In a feasible implementation manner, for example, continuing to refer to FIG. 8 , a third conductive column 700 is also provided between the second-layer chip unit 104 and the third-layer chip unit 105 , and the circuit of the second-layer chip unit 104 The region is provided with a second through hole 710, and the second through hole 710 is electrically connected to the circuit on the second layer chip unit 104; . The third conductive pillar 700 can be used to conduct the lines on the second-layer chip unit 104 and the third-layer chip unit 105 .

In the stacked chip provided by the embodiment of the present application, by setting the third conductive pillar 700 through the second through hole 710, the third conductive pillar 700 can electrically connect the second-layer chip unit 104 and the third-layer chip unit 105 together. , enabling stacking of multiple chip units and electrical connection of multiple chip units.

In a feasible implementation manner, for example, referring to FIG. 1 , the material of the first support pillar 300 and the first conductive pillar 200 includes a metal material.

In a feasible implementation manner, for example, referring to FIG. 1 , the first support pillar 300 and the first conductive pillar 200 may use the same material. The first support column 300 and the first conductive column 200 use the same material, and the first support column 300 and the first conductive column 200 can be prepared in the same process, which can optimize the process flow and achieve improvement without increasing the process cost. Effect of stress unevenness problem on stacked die.

In a feasible implementation manner, the first support pillar 300 and the first conductive pillar 200 are connected to a corresponding chip unit 100 through metal bonding. Exemplarily, referring to FIG. 2, if both the first support pillar 300 and the first conductive pillar 200 are made of metal materials, the first support pillar 300 and the first conductive pillar 200 are first prepared together on the bottom chip unit 101, and then the first support pillar 300 and the first conductive pillar 200 are prepared together through the metal bond. The top chip unit 102 is arranged and bonded with the first support pillar 300 and the first conductive pillar 200 in a combined manner to obtain a stacked chip. It should be noted that before bonding, the top chip unit 102 may be thinned on the non-circuit side (thinned on the back side).

In a feasible implementation manner, referring to FIG. 1 , pads may be provided at the contact areas between the chip unit 100 and the first support pillar 300 and the first conductive pillar 200 respectively, and the pads may be made of metal materials to facilitate the preparation process. The chip unit 100 is bonded to the first support pillar 300 and the first conductive pillar 200 respectively by means of metal bonding, which is not specifically limited in this application.

The second aspect of the embodiment of the present application provides a method for preparing a stacked chip, which is applied to the stacked chip described in the first aspect. FIG. 9 is a schematic flow chart of a method for preparing a stacked chip provided by the embodiment of the present application. picture. As shown in Figure 9, the method for preparing stacked chips provided in the embodiment of the present application includes:

S100: arranging a first support pillar and a first conductive pillar on one side of the chip unit on the first layer;

S200: Arranging the chip unit on the second layer opposite to the chip unit on the first layer, wherein the first support column and the first conductive column are located between the connection of the chip unit on the first layer and the chip unit on the second layer, and the first support column is used for The support stress is generated on the chip units, and the first conductive column is used to conduct the circuits on the two connected chip units.

In a feasible implementation manner, before the step of arranging the first support column and the first conductive column on one side of the chip unit on the first layer, the method further includes:

An integrated circuit is arranged on one side of the chip unit of the first layer to form the circuit side of the chip unit of the first layer, and an integrated circuit is arranged on one side of the chip unit of the second layer to form the circuit side of the chip unit of the second layer. The line side of the first layer of chip units includes a first line area and the first non-line area, and the line side of the second layer of chip units includes a second line area and a second non-line area;

A first conductive column and a first support column are arranged on the line side of the first layer chip unit, wherein the contact area between the first conductive column and the first layer chip unit is located in the first circuit area, and the first support column and the first The contact area of the layer chip unit is located in the first non-circuit area;

The step of arranging the chip unit on the second layer relative to the chip unit on the first layer includes:

The second-layer chip unit is arranged opposite to the first-layer chip unit, wherein the contact area between the first conductive pillar and the second-layer chip unit is located in the second circuit area, and the contact area between the first support column and the second-layer chip unit is located in the The second non-line area.

In a feasible implementation manner, the step of arranging the first conductive pillar and the first support pillar on the line side of the chip unit on the first layer includes:

A first conductive column, a first support column, a second conductive column and/or a second support column are arranged on the line side of the first layer chip unit, wherein the contact area between the second conductive column and the first layer chip unit is located at the first In the circuit area, the contact area between the second support pillar and the chip unit on the first layer is located in the first non-circuit area;

Before the step of arranging the chip units on the second layer relative to the chip units on the first layer, it also includes:

An integrated circuit is arranged on one side of the third-layer chip unit to form a line side of the third-layer chip unit, wherein the line side of the third-layer chip unit includes a third line area and a third non-line area;

A first through hole and/or a third through hole are arranged on the chip unit of the second layer, wherein the first through hole is arranged in the second circuit area, and the third through hole is arranged in the second non-circuit area;

After the step of arranging the chip units on the second layer relative to the chip units on the first layer, it also includes:

The chip unit on the second layer is arranged opposite to the chip unit on the third layer, wherein the second conductive column is located between the chip unit on the first layer and the chip unit on the third layer, and/or the second support column is located on the chip unit on the first layer Between the chip unit on the third layer, the second conductive pillar penetrates through the first through hole, and/or, the second supporting pillar penetrates through the third through hole.

Exemplarily, taking a stacked chip comprising two layers of chip units (including a bottom chip unit and a top chip unit) as an example, the exemplary preparation method of the stacked chip is briefly described as follows.

A method for preparing stacked chips, comprising the steps of:

Step 1, disposing an integrated circuit on one side of the bottom chip unit to form the circuit side of the bottom chip unit. In this step, during the process of setting the integrated circuit, a conductive pad (conductive pad) can be synchronously set at the position where the first conductive column needs to be set. The conductive pad is not specifically limited in this application, and may or may not be set.

In step 2, a first conductive pillar and a first supporting pillar are arranged on the circuit side of the bottom chip unit, wherein the first conductive pillar is arranged in the circuit area, and the first supporting pillar is arranged in the non-circuit area. If the first conductive pillar and the first supporting pillar are made of the same material, the first conductive pillar and the first supporting pillar can be prepared synchronously. The first conductive pillars and the first support pillars can be obtained by film formation and etching, or the pre-prepared first conductive pillars and first support pillars can be bonded to the bottom chip unit by metal bonding line side.

Step 3, setting an integrated circuit on one side of the top chip unit to form the circuit side of the top chip unit. Similarly, during the process of setting the integrated circuit on the top chip unit, a conductive pad (conductive pad) can be synchronously set at the corresponding position where the first conductive column needs to be set. The application does not specifically limit the conductive pad, and it can be set or not set. . If the first support column and the top chip unit are bonded by metal bonding, the contact area corresponding to the top chip unit and the first support column can also be provided with a pad. Since the first support column is located in the non-circuit area, even the pad It is a metal material, and it will not conduct the line.

Step 4, thinning the non-circuit side of the top chip unit. It should be noted that the order of step 3 and step 4 can be reversed, and the thinning process sequence can be adjusted according to the actual process flow design.

Step 5, the top chip unit is bonded to the first support pillar and the first conductive pillar respectively through metal bonding, and the line side of the bottom chip unit is opposite to the line side of the top chip unit. It should be noted that step five is based on the premise that both the first support pillar and the first conductive pillar are made of metal materials. In addition, the top chip unit is metal-bonded with the ends of the first support pillar and the first conductive pillar away from the bottom chip unit respectively.

Taking a stacked chip including three-layer chip units as an example (including a first-layer chip unit, a second-layer chip unit, and a third-layer chip unit), as an example, a method for preparing a stacked chip is briefly described as follows.

When the stacked chip includes three chip units, the bottom chip unit is the first layer chip unit, the top chip unit is the third layer chip unit, and the second layer chip unit can also be thinned, which is not specifically limited in this application.

Step 2 may also include:

A second conductive pillar, and/or a second supporting pillar is arranged on the line side of the chip unit on the first layer.

The following steps need to be included before step five:

An integrated circuit is arranged on one side of the second-layer chip unit to form the circuit side of the second-layer chip. Similarly, during the process of setting the integrated circuit in the chip unit of the second layer, a conductive pad (conductive pad) can be set at the corresponding position where the first conductive column needs to be set synchronously. This application does not specifically limit the conductive pad, and it can be set or Do not set. If the first support column and the top chip unit are bonded by metal bonding, the contact area corresponding to the top chip unit and the first support column can also be provided with a pad. Since the first support column is located in the non-circuit area, even the pad It is a metal material, and it will not conduct the line.

The first through hole and/or the third through hole are arranged on the chip unit of the second layer, the first through hole is arranged in the circuit area, and the third through hole is arranged in the non-circuit area.

Bonding the second-layer chip unit with the first conductive column and the second conductive column on the first-layer chip unit, the line side of the first-layer chip unit corresponds to the line side of the second-layer chip unit; at the same time, The second conductive pillar passes through the first through hole, and/or the second support pillar passes through the third through hole.

Step five may include:

Bonding the third-layer chip unit and the second support pillar together by means of metal bonding; and/or,

The third-layer chip unit and the second conductive pillar are bonded together by metal bonding, and the circuit side of the third-layer chip unit is opposite to the circuit side of the first-layer chip unit.

If there is a third conductive column between the second-layer chip unit and the third-layer chip unit, it is necessary to set a second through hole in the circuit area of the second-layer chip unit, and the second through hole and the circuit of the second-layer chip unit For electrical connection, the third conductive column may be firstly disposed on the back of the second-layer chip unit, electrically connected to the second through hole, and then bonded to the third-layer chip unit. It is also possible to arrange the third conductive column on the chip unit on the third layer first, and then pass the third conductive column in the second through hole to realize electrical connection.

The above steps of the preparation method are only listed as examples, and are not intended as specific limitations of the present application.

While the preferred embodiments of the present specification have been described, additional changes and modifications can be made to these embodiments by those skilled in the art once the basic inventive concept is appreciated. Therefore, it is intended that the appended claims be interpreted to cover the preferred embodiment as well as all changes and modifications that fall within the scope of this specification.

Obviously, those skilled in the art can make various changes and modifications to this description without departing from the spirit and scope of this description. In this way, if these modifications and variations of this specification fall within the scope of the claims of this specification and their equivalent technologies, this specification also intends to include these modifications and variations.

Claims

A stacked chip, characterized in that it comprises:

At least two chip units stacked on top of each other;

A first support column and a first conductive column are arranged between two adjacent chip units;

The first support column is used to generate support stress on the chip unit, and the first conductive column is used to conduct the circuit on the two connected chip units.
The stacked chip according to claim 1, characterized in that,

The line side of the chip unit includes a line area and a non-line area, and the line area includes the line;

The contact area between the first conductive pillar and the chip unit is located in the circuit area;

The contact area between the first support pillar and the chip unit is located in the non-circuit area.
The stacked chip according to claim 2, characterized in that,

The first supporting pillar is disposed on a virtual dividing line of the chip unit, wherein the virtual dividing line is obtained by dividing the chip unit into equal parts, and the virtual dividing line is located in the non-circuit area.
The stacked chip according to claim 3, characterized in that,

The first supporting pillars arranged on the virtual dividing line are arranged at equal intervals.
The stacked chip according to claim 2, characterized in that,

Also includes a second conductive column;

The second conductive column is arranged between two non-adjacent chip units;

The second conductive column is used for conducting the lines of the two connected chip units;

The contact area between the second conductive pillar and the chip unit is located in the circuit area.
The stacked chip according to claim 5, characterized in that,

also includes a second support column;

The second support column is arranged between two non-adjacent chip units;

The second supporting column is used to generate supporting stress on the chip unit;

The contact area between the second support pillar and the chip unit is located in the non-circuit area.
The stacked chip according to claim 6, characterized in that,

Including: chip units on the Nth layer, chip units on the N+1 layer and chip units on the N+2 layer stacked in sequence, where N is a natural number greater than 0;

The circuit side of the chip unit on the Nth layer is opposite to the circuit side of the chip unit on the N+1 layer;

The line side of the Nth layer chip unit is opposite to the line side of the N+2th layer chip unit;

The first support pillar and the first conductive pillar are arranged between the Nth layer chip unit and the N+1th layer chip unit;

The first supporting column is arranged between the N+1th layer chip unit and the N+2th layer chip unit;

The second conductive column is disposed between the Nth layer chip unit and the N+2th layer chip unit.
The stacked chip according to claim 7, characterized in that,

The non-circuit area of the N+1th layer chip unit is provided with a first through hole;

The second conductive pillar disposed between the Nth layer chip unit and the N+2th layer chip unit passes through the first through hole.
The stacked chip according to claim 7, characterized in that,

Also includes a third conductive post,

The third conductive column is disposed between the N+1th layer chip unit and the N+2th layer chip unit;

The line area of the N+1th layer chip unit is provided with a second through hole;

The second through hole is electrically connected to the circuit on the N+1th layer chip unit;

The third conductive column passes through the second through hole and is electrically connected with the second through hole.
The stacked chip according to claim 1, characterized in that,

The material of the first support column and the first conductive column includes a metal material.
The stacked chip according to claim 10, characterized in that,

The first support pillar and the first conductive pillar are connected to a corresponding one of the chip units through metal bonding.
A method for preparing a stacked chip, characterized in that it is applied to the stacked chip according to any one of claims 1-11, the method comprising:

setting a first support post and a first conductive post on one side of the chip unit on the first layer;

The second-layer chip unit is arranged opposite to the first-layer chip unit, wherein the first support column and the first conductive column are located between the first-layer chip unit connection and the second-layer chip unit In between, the first support column is used to generate support stress on the chip unit, and the first conductive column is used to conduct the circuit on the two connected chip units.
The method for preparing stacked chips according to claim 12, characterized in that before the step of arranging the first supporting pillars and the first conductive pillars on one side of the chip unit on the first layer, further comprising:

An integrated circuit is arranged on one side of the first layer chip unit to form the line side of the first layer chip unit, and an integrated circuit is arranged on one side of the second layer chip unit to form the second layer chip The line side of the unit, wherein the line side of the first layer chip unit includes a first line area and a first non-line area, and the line side of the second layer chip unit includes a second line area and a second line area Second non-line area;

The step of arranging the first support column and the first conductive column on one side of the chip unit on the first layer includes:

The first conductive column and the first supporting column are arranged on the line side of the first layer chip unit, wherein the contact area between the first conductive column and the first layer chip unit is located at the In the first circuit area, the contact area between the first support pillar and the first layer chip unit is located in the first non-circuit area;

The step of arranging the second-layer chip unit relative to the first-layer chip unit includes:

The second-layer chip unit is arranged opposite to the first-layer chip unit, wherein the contact area between the first conductive column and the second-layer chip unit is located in the second line area, and the first The contact area between the support pillar and the chip unit on the second layer is located in the second non-circuit area.
The method for manufacturing stacked chips according to claim 13, wherein the step of arranging the first conductive pillars and the first support pillars on the line side of the first-layer chip unit includes :

The first conductive column, the first support column, the second conductive column and/or the second support column are arranged on the line side of the first layer chip unit, wherein the second conductive column is connected to the The contact area of the first-layer chip unit is located in the first circuit area, and the contact area between the second support pillar and the first-layer chip unit is located in the first non-circuit area;

Before the step of arranging the second-layer chip unit relative to the first-layer chip unit, it also includes:

An integrated circuit is arranged on one side of the third-layer chip unit to form the line side of the third-layer chip unit, wherein the line side of the third-layer chip unit includes a third line area and a third non-line area ;

A first through hole and/or a third through hole are arranged on the second layer chip unit, wherein the first through hole is arranged in the second circuit area, and the third through hole is arranged in the first through hole Second non-line area;

After the step of arranging the second-layer chip unit relative to the first-layer chip unit, it further includes:

The second-layer chip unit is arranged opposite to the third-layer chip unit, wherein the second conductive column is located between the first-layer chip unit and the third-layer chip unit, and/or, The second support column is located between the first layer chip unit and the third layer chip unit, the second conductive column penetrates the first through hole, and/or, the second support The post is passed through the third through hole.