JPS60182731A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS60182731A
JPS60182731A JP59038086A JP3808684A JPS60182731A JP S60182731 A JPS60182731 A JP S60182731A JP 59038086 A JP59038086 A JP 59038086A JP 3808684 A JP3808684 A JP 3808684A JP S60182731 A JPS60182731 A JP S60182731A
Authority
JP
Japan
Prior art keywords
chip
semiconductor
conductor
size
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59038086A
Other languages
Japanese (ja)
Inventor
Tamotsu Kawaguchi
川口　保
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP59038086A priority Critical patent/JPS60182731A/en
Publication of JPS60182731A publication Critical patent/JPS60182731A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
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    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71

Abstract

PURPOSE:To improve area efficiency by bringing the size of a semiconductor chip on the upper side to a slightly small size and each connecting a semiconductor chip on the lower side to a conductor through wireless bonding and the upper side chip to it through wire bonding in two kinds of the semiconductor chips, the backs thereof are fixed mutually. CONSTITUTION:When the backs of semiconductor chips 14' and 16' of two kinds are fixed mutually by using adhesives 15, the size of the upper chip 16' is previously made slightly larger than that of the lower chip 14'. When the lower chip 14' is connected to split conductors 12 formed on the surface of a substrate 11, solder bumps 13 are shaped at both ends of the lower surface of the chip 14', and the bumps 13 are each fixed to the conductors 12 through a face down. Metallic wires 17 are used in the chip 16', and the chip 16' is connected to several conductor 12 through a face up. Accordingly, a semiconductor device with a large number of connecting conductors is obtained without magnifying the size of the chips.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は半導体装置に係り、特に半導体素子ペレットと
リードフレーム間の配線が行われる半導体装置に関する
。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device, and particularly to a semiconductor device in which wiring is performed between a semiconductor element pellet and a lead frame.

〔発明の技術的背景〕[Technical background of the invention]

半導体装置はウェーハ上写真食刻技術等によって多数形
成された集積回路を分離して半導体チックとし、これを
セラミック基板上またはリードフレームのベッドに搭載
し、適当なシール等を行ってパッケージを形成している
。Semiconductor devices are manufactured by separating a large number of integrated circuits formed on a wafer using photolithography technology to form semiconductor chips, mounting them on a ceramic substrate or a bed of a lead frame, and forming a package by performing appropriate sealing. ing.

第１図ないし第３図は従来使用されている半導体装置の
代表的な形式を示しまた中心断面図でろって、第１図で
はセラミック等の基板／上に設けら′！′した導体−の
上に半拾体チッゾグがダイポンディングにより表面を上
向き（フェースアップ）に固着されており、この半導体
チップ≠の電極はその周囲に配設さｊた外部引出用導体
３とポンディングワイヤ！によって接続されている。1 to 3 show typical types of conventionally used semiconductor devices, and are central sectional views. A half-chip chip is fixed on top of the semiconductor chip with its surface facing upward (face-up) by die bonding, and the electrode of this semiconductor chip is connected to the external lead-out conductor 3 arranged around it. Ding wire! connected by.

ま７’Ｃ第、２図および第３図はポンディングワイヤを
使用しない、いわゆるワイヤレスポンディングによる半
導体装置を示す正面図で必って、第２図においてはセラ
ミック等の基板／上に設けられた外部引出用導体乙に半
導体チソゾグが表■１を下向き（フェースタウン）には
んだ等の突起物であるパンシフを介し７て取付けられて
おり、フリップテップ方式と称さハる。第３図はビーム
リード方式の実装法を示すもので、半導体テップのＭｉ
、極部に微細な金のビーム状リードｇをウェーッ・工程
で形成しておき、基鈑／上に形成さｒた金導体パターン
タにフェースダウンで熱圧＠烙れている。ワイヤレスボ
ンディング方式には他に金バンゾを有する半導体チッソ
′を長尺ポリイミドテープ上に多数取ｆ’Ｊ’　ｉ’ｌ
’　ｆｔ：ものから＋；１．ｌｔＥ＋ｌ、て使用するＴ
　Ａ　Ｂ　（ＴａｐｅＡｕｔｏｍａｔｅｄＢｏｎｄｉｎ
ｇ　）方式等があり、それそｉｑ、％　徴を有している
が、こｊ２らは単独で使用されるにすぎない。Figures 7'C, 2, and 3 are front views showing semiconductor devices using so-called wireless bonding, which do not use bonding wires. The semiconductor chisosog is attached to the external lead-out conductor B with the front side facing downward (face town) via a pansif, which is a protrusion such as solder, and is called a flip-tep method. Figure 3 shows the beam-lead mounting method.
A fine gold beam-shaped lead (g) is formed at the extreme part by a waving process, and is hot-pressed face-down onto the gold conductor pattern (r) formed on the base plate. In addition to the wireless bonding method, a large number of semiconductors containing gold alloys are placed on a long polyimide tape.
' ft: from thing+;1. ltE+l, T used
A B (Tape Automated Bondin
g) There are various methods, each with iq and % characteristics, but these are only used alone.

〔清１Ｌ技術の間廐点〕 しかし、なから、近年の半導体装置における高集私化に
伴い半導体テップから引き出す笥極の数は増加しつつあ
るが、このような多数の電極に対しては従来の構成では
小さな半導体チップの周囲に配設できる導体の数に限度
が生する。[The point between Qing 1L technology] However, the number of electrodes extracted from a semiconductor chip is increasing due to the high density privateization of semiconductor devices in recent years. Conventional configurations place a limit on the number of conductors that can be placed around a small semiconductor chip.

半導体チップの周囲に配設される導体の数を増加させる
手段として導体の先端位置を半導体テップの中心より遠
さけることも可能であるか、そのためには半畳体チッソ
′の大きさそのものを大きくする必要が生ずる。このよ
うな大きな半導体テップ′では不良箇所の生ずる可能性
が高せυ、高い歩留りで半導体テップを製造することが
回軸となるという問題がある。Is it possible to move the tip of the conductor away from the center of the semiconductor chip as a means of increasing the number of conductors arranged around the semiconductor chip?To do this, the size of the semi-conductor Chisso' itself should be increased. A need arises. With such a large semiconductor chip, there is a high possibility that defective parts will occur υ, and there is a problem in that manufacturing the semiconductor chip with a high yield is the key.

〔発明の目的〕[Purpose of the invention]

不発り］は、上記問題点を銅決するためにガさ扛たもの
で、半導体ナツツの大きさを拡大することなく、しかも
大部の導体括続を廟する半導体装置を朴′供１−ること
を目的とする。``Unexploded'' was a great effort to solve the above problems, and it was possible to create a semiconductor device without increasing the size of the semiconductor and with most of the conductor connections. The purpose is to

〔発明の仲要］ 上記目的達成のため、本発明においては、互いに船ｍ１
どうじを固着したコ釉類の半導体チックを備え、一方の
半導体チップはワイヤレスポンディングにより霜１極引
出導体に接続さｊ、他方の半導体チップはワイヤボンデ
ィングにより前記％、極引出導体に払齢するようにし２
ておジ、半導体チップの大きさをハエ１加させることな
く多数の引出導体との接線５を可能ならしめるものであ
る。[Intermediary of the invention] In order to achieve the above object, in the present invention, the ship m1
It is equipped with a glazed semiconductor chip to which the metal is fixed, one semiconductor chip is connected to the frost single pole lead-out conductor by wireless bonding, and the other semiconductor chip is connected to the pole lead-out conductor by wire bonding. Yonishi 2
In addition, it is possible to form tangent lines 5 to a large number of lead conductors without increasing the size of the semiconductor chip.

〔発明の実施例〕[Embodiments of the invention]

以下、図面を参照しな力・ら本発明の一実施例について
泪゛細に詐明する。Hereinafter, one embodiment of the present invention will be explained in detail with reference to the drawings.

第を図は不発、明の典型的な実施例を示す中央障１面図
であって、カーイタｌ／上に形成場また導体／２にはは
んたバンズ／３によって斗妨・体テップ／ｑかフェース
ダウンで同浴−され−ており、この半畳体チッソ／Ｉ／
の上には話、左１斉１１１５によりもう一つの手法’　
（２・ナツプ１６かフェースアップで辻茄芒７１でいる
。半４□・体テップ１６上の電極からは金捷たはアルミ
ニウムのワイヤ／７で導体／２に文」しで拓＃、ｉ？か
イ丁わｆｌている。したかって２つの斗２７′１体テッ
ツ゛／９および／６は力いに失Ｕｎどうしが貼合わされ
ている。Figure 1 is a front view of a central barrier showing a typical embodiment of Ming, with a formation field on the conductor /2 and solder buns /3 on the conductor /2. They are bathed face down, and this semi-tatami Chisso/I/
Above is another method by 1115 on the left.
(2.Natsupu 16 or face-up, Tsujima 71. From the electrode on half 4□ body tip 16, wire /7 of gold or aluminum to conductor /2.''?It's just fl.Therefore, the two dots /9 and /6 are glued together.

１５図は汗弘図の場合ン−１ｉｆ＋＋から究たシｉてわ
って、放射状に形成芒ｆ）だｄＦ体／２Ａは半畳体チッ
ソ／４’の下まで伸び、第、グーに示ｔ−，＊ようには
んたバンズ１３を介し２てワイヤレスポンディングによ
り括Ｅ１さ力ている。杉林ｌ：１ＡＩｉＡ１に形成さ扛
た導体ｌコＢはやはり放射状と力っているｔ、：その先
端荀楢は尋体／コＡとショートのおそねかない程度の間
隙を荀゛ｉ（鐘て゛きるも’ｒ’　ｉ？＋でとど貰って
いる。この私・イ杢／コＡけ１、半嗜体テノグ／ｑ土に
フェースアップで括オｊ芒わだ＃ネ゛ζ体チップｌｔ上
の１−４．什／ｇとワイヤ／７によって接ｈ【°芒扛１
いる。Figure 15 shows that in the case of the sweat diagram, the cylindrical body formed radially from n-1if++, the dF body/2A extends to the bottom of the semiconvoluted body Chisso/4', and the t- ,*The bundle E1 is powered by wireless bonding through the solder buns 13. Sugibayashi L: 1 AIi The conductor B formed on A1 is still radial and strong. The tip of the conductor B has a gap between it and the core A that does not cause a short circuit. I'm getting it with 'r' i? 1-4.Connected by ti/g and wire/7
There is.

第６図は本発明の他１の実施例を示す中央断ｍｊ図であ
って、第グ図および第５図では２つの半畳体チッソ′／
ｌおよび／６の大きさか同じでａっだのに対し、この黄
施セ１１ではワイヤレスポンチインクで罰を体／Ｌ２と
多動さｆｌろ下側の半朴、・体テラｆｉｔｉ’の太きさ
力・ワイヤ／７によシ鴎体／呪→紗さ九ろ半導体テップ
／６′　の太きさよりも大さくなっている１、このよう
な朴順νではあらかじめ２つの半畳体チッソをｂ１湊し
、ておき、ワイヤレスポンディングを１の半導体テップ
の外形をカイトとし、て上伸に惰い、またワイヤホンデ
ィングを安定に行うことかできる。FIG. 6 is a center cut mj diagram showing another embodiment of the present invention, and FIG. 6 and FIG.
While L and /6 are the same size and a, this Huang Shise 11 uses wireless punch ink to punish the body / L2 and hyperactivity, the lower half of fl, and the thickness of body tera fiti'. Kisa force/Wire/7 Yoshi Uta/Curse → Sasakuro Semiconductor tip/6' Thickness is larger than 1. In such a Pakjun ν, two half-tatami body Chisso are prepared in advance. It is possible to carry out wireless bonding by setting the external shape of the semiconductor tip b1 to a kite, allowing it to move upward, and also to perform wire bonding stably.

以上の火施ｆＬにおいては互いに次ｍ１とつし、を括殆
剤で接浴した牛シ１体チツ′ｊ′全使用しているが、（
１１！の適当な手段により固着ネ扛るものであってもよ
い。In the above fire fL, one cow body ``j'', which has been bathed with the next m1, is used, but (
11! It may be fixed by any suitable means.

！た実施例で１１側の半導体ナツツの導体との接左メ・
をはんたパンツを使用したフリッズテンプ方式で？”ｊ
っているか、ビームリード方式やＴＡＢ方式粂のを・ら
ゆるワイヤレスポンディングを使用することができる、 〔究明の効果〕 以」二のように、本祈りｈにおいては、万いに裏面どう
しを固３′コした。２１１・・類の半導体チップのうち
一方はワイヤレスポンディングで、他力はワイヤポンデ
ィングで基昏上の導体に打続するようにしているので、
半導体テップ周囲に形成づ１、る心外の裟ソを半瀉口・
チッソの大きさをＪ］ｌ太イることなく増加部ぜること
かでき、面朴：９ＪＪ率が向上する。! In the example given above, the connection between the semiconductor nut on the 11th side and the conductor is
Frizz balance method using solder pants? ”j
It is possible to use any wireless bonding method, such as the beam lead method or the TAB method. It was hard 3'. One of the semiconductor chips of type 211 is connected by wireless bonding, and the other is connected to the underlying conductor by wire bonding.
Semi-open the external holes that form around the semiconductor chip.
It is possible to increase the size of Chisso without increasing the size of J]l, and the face-to-face ratio is improved.

ｔた、小芒な半小鉢チックを、２　ａ！類使用している
ので、１１品を選択して糾合わせることができ、はじめ
〃・ら太きな半々ン体テソゾでル成する騒、合と比較し
２て歩留りを向上させること力・で＠石。2 a! Since we are using similar products, we can select and combine 11 products, and first, we can improve the yield compared to the noise made by thick half-half body Tesozo. @stone.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図ないし第３図は従来の半満体ギｆ悄における実験
の様子を示す中央Ｖノ（面し１、第１１．図は本発明の
一実施例の相成を示す中央断百１図、第５図はその平曲
１図、第６図は本発す―の（ｊＩ〕の裸か１伜□を示す
中央「Ｊ１面図である。 ／、／／・°・ノーー座役　、２，３．　Ｉ）　、　？
　、／−！・・・小体、４ｔ。 ／４’　、　／／、・・・半導体テップ、ｊ、／７・・
・ワイヤ、７．／３・・・はんまたパンツ′、１５・・
・拝着剤。 出ルＩｔ、Ａ心理人　犯　股　苗 ち　１　閃 ち　２　履 ら　３　図 ６４　図 ６５　図 ら　６　図Figures 1 to 3 show the state of the experiment in the conventional half-full body Gifu (center V section 1, side 11). Fig. 5 is the flat curve 1, and Fig. 6 is the central "J1 side view showing the bare or 1□ of (jI) of the main issue. /, //・°・Noー seat, 2, 3. I), ?
,/-! ... corpuscle, 4t. /4', //,...semiconductor tip, j, /7...
・Wire, 7. /3... Hanmata pants', 15...
・Adhesive. It comes out, A psychological person criminal crotch Naechi 1 Flash 2 Shoe 3 Figure 64 Figure 65 Figure 6 Figure

Claims (1)

【特許請求の範囲】 １、互いに裏面どうしを固着した２柚類の半導体テップ
を備え、−万の半導体チップはワイヤレスポンディング
により基板上の電極引出導体に接続さ扛、他方の半導体
チックはワイヤポンディングにより前記％極引出導体に
接続さｊた半導体装置。 ユ　ワイヤホンディングによりｔｉ、極引出導体に接続
さｎ、る半導体チップの大きさがワイヤレスポンディン
グにより前記電極引出導体に′＃枕される半導体チップ
の太きさよりも小さいものでおる特許請求の範囲第１項
記載の半導体装置。[Scope of Claims] 1. Two semiconductor chips are bonded to each other with their back surfaces fixed to each other, one semiconductor chip is connected to an electrode lead conductor on the substrate by wireless bonding, and the other semiconductor chip is connected to a wire. A semiconductor device connected to the above-mentioned lead-out conductor by bonding. The size of the semiconductor chip connected to the electrode lead conductor by wire bonding is smaller than the thickness of the semiconductor chip connected to the electrode lead conductor by wireless bonding. A semiconductor device according to scope 1.
JP59038086A 1984-02-29 1984-02-29 Semiconductor device Pending JPS60182731A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59038086A JPS60182731A (en) 1984-02-29 1984-02-29 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59038086A JPS60182731A (en) 1984-02-29 1984-02-29 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS60182731A true JPS60182731A (en) 1985-09-18

Family

ID=12515659

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59038086A Pending JPS60182731A (en) 1984-02-29 1984-02-29 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS60182731A (en)

Cited By (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5291061A (en) * 1993-04-06 1994-03-01 Micron Semiconductor, Inc. Multi-chip stacked devices
WO1996017505A1 (en) * 1994-12-01 1996-06-06 Motorola Inc. Method, flip-chip module, and communicator for providing three-dimensional package
US5703405A (en) * 1993-03-15 1997-12-30 Motorola, Inc. Integrated circuit chip formed from processing two opposing surfaces of a wafer
US6014586A (en) * 1995-11-20 2000-01-11 Pacesetter, Inc. Vertically integrated semiconductor package for an implantable medical device
US6395578B1 (en) 1999-05-20 2002-05-28 Amkor Technology, Inc. Semiconductor package and method for fabricating the same
US6452278B1 (en) 2000-06-30 2002-09-17 Amkor Technology, Inc. Low profile package for plural semiconductor dies
US6552416B1 (en) 2000-09-08 2003-04-22 Amkor Technology, Inc. Multiple die lead frame package with enhanced die-to-die interconnect routing using internal lead trace wiring
US6555917B1 (en) 2001-10-09 2003-04-29 Amkor Technology, Inc. Semiconductor package having stacked semiconductor chips and method of making the same
US6642610B2 (en) 1999-12-20 2003-11-04 Amkor Technology, Inc. Wire bonding method and semiconductor package manufactured using the same
US6737750B1 (en) 2001-12-07 2004-05-18 Amkor Technology, Inc. Structures for improving heat dissipation in stacked semiconductor packages
US6798049B1 (en) 1999-08-24 2004-09-28 Amkor Technology Inc. Semiconductor package and method for fabricating the same
EP1187210A3 (en) * 2000-09-07 2005-03-02 Matsushita Electric Industrial Co., Ltd. Semiconductor device
US6879047B1 (en) 2003-02-19 2005-04-12 Amkor Technology, Inc. Stacking structure for semiconductor devices using a folded over flexible substrate and method therefor
US6930378B1 (en) 2003-11-10 2005-08-16 Amkor Technology, Inc. Stacked semiconductor die assembly having at least one support
US6946323B1 (en) 2001-11-02 2005-09-20 Amkor Technology, Inc. Semiconductor package having one or more die stacked on a prepackaged device and method therefor
US7126218B1 (en) 2001-08-07 2006-10-24 Amkor Technology, Inc. Embedded heat spreader ball grid array
US7154171B1 (en) 2002-02-22 2006-12-26 Amkor Technology, Inc. Stacking structure for semiconductor devices using a folded over flexible substrate and method therefor
US7211884B1 (en) 2002-01-28 2007-05-01 Pacesetter, Inc. Implantable medical device construction using a flexible substrate
USRE40061E1 (en) 1993-04-06 2008-02-12 Micron Technology, Inc. Multi-chip stacked devices
US7485490B2 (en) 2001-03-09 2009-02-03 Amkor Technology, Inc. Method of forming a stacked semiconductor package
JP2015070036A (en) * 2013-09-27 2015-04-13 ローム株式会社 Semiconductor device and electronic apparatus
US20160379933A1 (en) * 2007-02-21 2016-12-29 Amkor Technology, Inc. Semiconductor package in package

Cited By (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5703405A (en) * 1993-03-15 1997-12-30 Motorola, Inc. Integrated circuit chip formed from processing two opposing surfaces of a wafer
USRE36613E (en) * 1993-04-06 2000-03-14 Micron Technology, Inc. Multi-chip stacked devices
US5291061A (en) * 1993-04-06 1994-03-01 Micron Semiconductor, Inc. Multi-chip stacked devices
USRE40061E1 (en) 1993-04-06 2008-02-12 Micron Technology, Inc. Multi-chip stacked devices
WO1996017505A1 (en) * 1994-12-01 1996-06-06 Motorola Inc. Method, flip-chip module, and communicator for providing three-dimensional package
US6014586A (en) * 1995-11-20 2000-01-11 Pacesetter, Inc. Vertically integrated semiconductor package for an implantable medical device
US6762078B2 (en) 1999-05-20 2004-07-13 Amkor Technology, Inc. Semiconductor package having semiconductor chip within central aperture of substrate
US6395578B1 (en) 1999-05-20 2002-05-28 Amkor Technology, Inc. Semiconductor package and method for fabricating the same
US6798049B1 (en) 1999-08-24 2004-09-28 Amkor Technology Inc. Semiconductor package and method for fabricating the same
US6642610B2 (en) 1999-12-20 2003-11-04 Amkor Technology, Inc. Wire bonding method and semiconductor package manufactured using the same
US6803254B2 (en) 1999-12-20 2004-10-12 Amkor Technology, Inc. Wire bonding method for a semiconductor package
US6452278B1 (en) 2000-06-30 2002-09-17 Amkor Technology, Inc. Low profile package for plural semiconductor dies
EP1187210A3 (en) * 2000-09-07 2005-03-02 Matsushita Electric Industrial Co., Ltd. Semiconductor device
US6552416B1 (en) 2000-09-08 2003-04-22 Amkor Technology, Inc. Multiple die lead frame package with enhanced die-to-die interconnect routing using internal lead trace wiring
US7485490B2 (en) 2001-03-09 2009-02-03 Amkor Technology, Inc. Method of forming a stacked semiconductor package
US7126218B1 (en) 2001-08-07 2006-10-24 Amkor Technology, Inc. Embedded heat spreader ball grid array
US6555917B1 (en) 2001-10-09 2003-04-29 Amkor Technology, Inc. Semiconductor package having stacked semiconductor chips and method of making the same
US6946323B1 (en) 2001-11-02 2005-09-20 Amkor Technology, Inc. Semiconductor package having one or more die stacked on a prepackaged device and method therefor
US6919631B1 (en) 2001-12-07 2005-07-19 Amkor Technology, Inc. Structures for improving heat dissipation in stacked semiconductor packages
US6737750B1 (en) 2001-12-07 2004-05-18 Amkor Technology, Inc. Structures for improving heat dissipation in stacked semiconductor packages
US7211884B1 (en) 2002-01-28 2007-05-01 Pacesetter, Inc. Implantable medical device construction using a flexible substrate
US7154171B1 (en) 2002-02-22 2006-12-26 Amkor Technology, Inc. Stacking structure for semiconductor devices using a folded over flexible substrate and method therefor
US6879047B1 (en) 2003-02-19 2005-04-12 Amkor Technology, Inc. Stacking structure for semiconductor devices using a folded over flexible substrate and method therefor
US7132753B1 (en) 2003-11-10 2006-11-07 Amkor Technology, Inc. Stacked die assembly having semiconductor die overhanging support
US6930378B1 (en) 2003-11-10 2005-08-16 Amkor Technology, Inc. Stacked semiconductor die assembly having at least one support
US7459776B1 (en) 2003-11-10 2008-12-02 Amkor Technology, Inc. Stacked die assembly having semiconductor die projecting beyond support
US7071568B1 (en) 2003-11-10 2006-07-04 Amkor Technology, Inc. Stacked-die extension support structure and method thereof
US7859119B1 (en) 2003-11-10 2010-12-28 Amkor Technology, Inc. Stacked flip chip die assembly
US20160379933A1 (en) * 2007-02-21 2016-12-29 Amkor Technology, Inc. Semiconductor package in package
US9768124B2 (en) 2007-02-21 2017-09-19 Amkor Technology, Inc. Semiconductor package in package
JP2015070036A (en) * 2013-09-27 2015-04-13 ローム株式会社 Semiconductor device and electronic apparatus

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