1242280 五、發明說明（2) 圓可被分割為獨立的半導體晶圓。 由刮線所包圍的晶片通常是以在晶圓上以積體電路内部 半導體結構、電性格離用或形成記憶胞元電晶體用之溝槽 被施加至上側的交點或類似者朝向晶體的主要方向的方式 而被設置。這些結構元件因此額外增加半導體晶片斷裂的 風險。在局度薄形化的半導體晶片的情況中尤其真實。 如果複數個半導體晶片使用垂直或立方體集積以形成半 導體晶片堆疊的話，此問題發生的程度更大。在垂直集積 的情況中，此晶片必需接地，直到它們是特別的薄，尤其 是如果它們想被使用在薄晶片卡的話。如果此垂直集積晶_丨 片係於慣用方式中產生，斷裂的傾向持續至增加至穿過整 個晶片堆疊的程度。 本發明之一目的在於描述薄化的晶片，尤其是垂直的集 積，斷裂可被降低以便它們可以在晶片卡的領域中被使 用。 此目的藉由具有申請專利範圍第1或3項之特徵的半導體 晶片或半導體晶片堆疊而達成。結構將從申請專利範圍依 附項產生。 如同以往，依然可能使用從具有（1，0，0 )晶體面做為上 側之晶矽而來的基板。積體電路用之上側的金屬相互連接4 連接實質上朝向沿互相垂直並包括與{ 0，1，〇 }面及{ 0，0，1 } 面呈至少1 0 °角之二方向。因此，如果該等相互連接傾斜 過該主要晶體面，其具有機械穩定的動作。此外，金屬相 互連接是多晶矽或非結晶的，並且因此可以在特定限制中1242280 V. Description of the invention (2) The circle can be divided into independent semiconductor wafers. The wafer surrounded by the scratch line is usually the main point on the wafer that is applied to the upper intersection or similar with the semiconductor structure inside the integrated circuit, the groove for the electrical character separation or the formation of the memory cell transistor, or the like. The way is set. These structural elements therefore increase the risk of semiconductor wafer breakage. This is particularly true in the case of locally thin semiconductor wafers. This problem occurs more if a plurality of semiconductor wafers are stacked vertically or cubely to form a semiconductor wafer stack. In the case of vertical accumulation, the chips must be grounded until they are particularly thin, especially if they are intended to be used in thin chip cards. If this vertically integrated crystal is produced in the conventional manner, the tendency to fracture continues to increase to the extent that it passes through the entire wafer stack. It is an object of the present invention to describe thinned wafers, especially vertical accumulations, and fractures can be reduced so that they can be used in the field of wafer cards. This object is achieved by a semiconductor wafer or a stack of semiconductor wafers having the features of the scope of claims 1 or 3 of the patent application. The structure will be generated from the scope of the patent application. As in the past, it is still possible to use a substrate from a crystalline silicon having a (1,0,0) crystal plane as the upper side. The integrated circuit is interconnected with metal on the upper side. 4 The connection is substantially perpendicular to each other and includes two directions at least 10 ° from the {0,1, 〇} plane and the {0,0,1} plane. Therefore, if the interconnections are inclined across the main crystal plane, they have a mechanically stable action. In addition, the metal interconnects are polycrystalline silicon or amorphous, and therefore can be within certain limits
1242280 五、發明說明（3) 被變形或拉 可與織品強 此外，也 構同樣包括 為此目 向一個 上側之 緣不具 因為 所定義 理期間 階器中 邊，而 以實質 於習知 造成在 導體元 行，因 在依 電路平 面之間 較佳者 中一者 面之一 的， 角度 主要 有啟 半導 ，為 ，晶 是足 是旋 上維 製程 半導 件内 為不 據本 面， 係以 ，在 在另 共同 伸。它們因此具有額外的機械強化的表現，約 化合成材料中的纖維比較。 可以使晶體内的積體電路之元件的直線及面結 與{0，1，0}面及{0,0，1}面成至少10°的角度。 在半導體晶片的製造期間，晶圓上的元件係朝 ，較佳者在1 5 °及4 5 °之間，相對於垂直晶圓 晶體面。由於此方向，在結構化期間產生的邊 動裂痕的效應。 體元件的結構係由製程期間所使用的光學微影 產生本發明之一半導體晶片，原則上在曝光處 圓在被旋轉穿過預定角度之一位置中被插入步 夠的（亦即，以平坦或凹槽不面向下方或側 轉通過15°至45° )。所有其它的製程步驟可 持不變。在此方式中，晶圓上的晶片排列相較 被旋轉且鑛齒台相對於裝置是斜向的。這不會 體晶片本身的設計及傳導中的任何改變，且半 部結構尤其可以如同之前一般與晶片邊緣平 需要鋸開平行一主晶體面之後者。 發明之一半導體晶片堆疊中，其形成該個別的 垂直於連續半導體晶片之電路平面的主要晶體 朝向包括除了 0°及90°角的方向被設置，且 每一情況中包括不同的角度。因為在每一情況 一者之上之二連續設置的電路平面經由做為介 金屬化而被連結在一起，這是足夠的，如果二1242280 V. Description of the invention (3) Deformed or pulled can be stronger than the fabric. In addition, it also includes the edge to the upper side for this purpose. It does not have the middle edge of the stepper because of the defined theorem. OK, because according to one of the better planes between the planes of the circuit, the angle mainly has the semiconducting semiconductor, so that the crystal is enough to spin the maintenance process semiconducting component, which is not based on the surface, so, Together in another stretch. They therefore have the additional performance of mechanical strengthening, reducing the fiber comparison in synthetic materials. The linear and surface junctions of the integrated circuit components in the crystal can be at least 10 ° from the {0,1,0} plane and the {0,0,1} plane. During the manufacture of a semiconductor wafer, the components on the wafer are oriented toward, preferably between 15 ° and 45 °, relative to the vertical wafer crystal plane. Due to this direction, the effect of edge cracks during structuring. The structure of the body element is produced by the optical lithography used during the manufacturing process of a semiconductor wafer of the present invention. In principle, the circle at the exposure position is inserted in a position rotated through a predetermined angle (that is, flat Or the grooves do not face downward or turn sideways through 15 ° to 45 °). All other process steps can remain the same. In this way, the wafer arrangement on the wafer is rotated as compared to the tine table is inclined with respect to the device. This does not change the design and conduction of the wafer itself, and the half structure can be flat with the wafer edge as before. It needs to be sawn parallel to the main crystal plane. One of the inventions is a semiconductor wafer stack, which forms the individual main crystals perpendicular to the circuit plane of the continuous semiconductor wafer. The directions including directions other than 0 ° and 90 ° are set, and each case includes a different angle. Because in each case two or more successively arranged circuit planes are connected together as a metallization, this is sufficient, if two
1242280 五、發明說明（4) 連續半導體晶片之至少一者相對於垂直半導體晶片之主晶 體面形成除了 0°及90°的角度。如果以此方式形成之半 導體晶片被放置在另一者的上方以形成半導體晶片堆豐並 且經由金屬化互相電性連接，垂直電路平面的主晶體面變 成位於除了 0 °及9 0 °的角度，而不需要進一步測量。 在另一實施例中，僅有由於以上相互連接之方向而本質 上對抗斷裂之半導體晶片被相互連接。 如果半導體堆疊之至少一些半導體晶片的互相連接相對 於主晶體面傾斜，但晶片的側面，晶片邊緣在所有半導體 晶片中平行於互相連接截面被鋸開，這些側面可能對應彼_丨 此在同一平面的方式中被定向。這產生具有平面邊界的晶 片堆疊，其中，在個別的電路面中，垂直於電路平面的主 晶體面的層互不相同。位於垂直層平面上之主晶體面相互 之間在每一晶片形成除了 0 及90 的角度’即使在具有 平面邊界之半導體晶片之例中。 現在參照圖一及二進行半導體晶片或半導體晶片堆疊之 實施例的詳細描述。 圖一表示具有施加於上側之相互連接2之半導體晶片之 平面圖。該等相互連接於本例中實質上被朝向二個互相垂 直的方向。相互連接之截面被設置在方向A或B，其於圖一 4 中位於互相垂直的角度。圖一所示之半導體晶片之上側相 對於對應基板或半導體晶體之{ 1，0，0 }面是共平面。在習 知的半導體晶片中，晶片邊緣4，5係一 { 0，1，0丨面或 {0，0，1}面。相反地，在本例中，{0，1，0}面或{0，0，1}面1242280 5. Description of the invention (4) At least one of the continuous semiconductor wafers forms an angle other than 0 ° and 90 ° with respect to the main crystal plane of the vertical semiconductor wafer. If a semiconductor wafer formed in this way is placed on top of the other to form a semiconductor wafer stack and is electrically connected to each other via metallization, the main crystal plane of the vertical circuit plane becomes at an angle other than 0 ° and 90 °, No further measurements are required. In another embodiment, only semiconductor wafers that are substantially resistant to fracture due to the above directions of interconnection are connected to each other. If the interconnection of at least some of the semiconductor wafers of the semiconductor stack is inclined with respect to the main crystal plane, but the side of the wafer, the wafer edge is sawed in all semiconductor wafers parallel to the interconnected cross-section, these sides may correspond to each other In the way. This results in a wafer stack with a planar boundary, in which the layers of the main crystal plane perpendicular to the circuit plane are different from each other in the individual circuit planes. The main crystal planes located on the plane of the vertical layer mutually form angles other than 0 and 90 'on each wafer, even in the case of a semiconductor wafer having a plane boundary. A detailed description of an embodiment of a semiconductor wafer or semiconductor wafer stack will now be made with reference to Figs. Fig. 1 shows a plan view of a semiconductor wafer having interconnects 2 applied to the upper side. These interconnections are essentially oriented in two perpendicular directions in this example. The interconnected cross sections are set in direction A or B, which are located at mutually perpendicular angles in FIG. The {1,0,0} plane of the upper side of the semiconductor wafer shown in Fig. 1 with respect to the corresponding substrate or semiconductor crystal is coplanar. In conventional semiconductor wafers, wafer edges 4, 5 are a {0,1,0 丨 plane or a {0,0,1} plane. Conversely, in this example, the {0,1,0} plane or the {0,0,1} plane
第7頁 1242280 五、發明說明（5) 在每一情況中於，例如，在所示之二箭頭之一所指之方向 延伸。但是，此晶片邊緣4，5平行於互相連接被鋸開。或 者是，也可以使側邊晶片邊緣被設置於箭頭所示的方向以 及與之垂直的方向中。於此例中，此等互相連接相對於晶 片邊緣傾斜。 圖一所示位於圖一水平相互連接截面之方向B與由右邊 箭號所指示之一主晶體方向之間的角度6或與角度6相關的 補角7係在1 0 °與8 0 °之間，較佳者在1 5 °與7 5 °之間。 在圖一所示實施例中角度6為6 7. 5 ° 。由所示箭號指示之 二方向互相之間形成4 5 °角。 φ 如果，在包括二半導體晶片的半導體晶片堆璧的情況 中，半導體晶體或基板的主晶體平面於此例中適用相對之 間呈4 5 °角，如果二半導體晶片之相互連接截面係沿著方 向A及B，此半導體晶片，在垂直集積的情況中，以晶片的 主晶體平面朝向相對間4 5 °角的方式藉由其個別的互相平 行的金屬化被互相連接，且於此方式中互相穩定。於此例 中，晶片邊緣4，5平行相互連接2之截面，其中晶片的垂直 電路平面之主晶體平面包括相互間的4 5 角以及和對應晶 片之相關金屬化之2 2 · 5或6 7 . 5 °角。 圖二表示一半導體晶片堆疊之實施例之截面，其中一第j 一另一晶片1 1及一第二另一晶片1 2被設置於一較低的半導 體晶片1内。此等半導體晶片藉由其上側3互相連接，其與 基板或半導體晶體之{ 1，0，0 }面共平面。在圖二所示簡化 的說明中，半導體晶片之間的結構金屬化被省略。Page 7 1242280 V. Description of the invention (5) In each case, for example, extending in the direction indicated by one of the two arrows shown. However, the wafer edges 4, 5 are sawed apart parallel to the interconnections. Alternatively, the edge of the side wafer may be set in a direction indicated by an arrow and a direction perpendicular to the edge. In this example, these interconnects are inclined relative to the wafer edge. The angle 6 shown in Figure 1 between the direction B of the horizontal interconnected section of Figure 1 and one of the main crystal directions indicated by the arrow on the right, or the supplementary angle 7 related to angle 6, is between 10 ° and 80 °. Between, preferably between 15 ° and 75 °. In the embodiment shown in FIG. 1, the angle 6 is 67.5 °. The two directions indicated by the arrows shown form a 45 ° angle with each other. φ If, in the case of a semiconductor wafer stack including two semiconductor wafers, the main crystal plane of the semiconductor crystal or substrate is in this example applicable at an angle of 45 °, the cross-section of the interconnection between the two semiconductor wafers follows Directions A and B. In the case of vertical accumulation, the semiconductor wafers are connected to each other by their individual parallel metallizations in such a way that the main crystal plane of the wafer is oriented relative to each other, and in this way, Mutual stability. In this example, the edges 4, 5 of the wafer are parallel to each other and the cross-section of 2, where the main crystal plane of the vertical circuit plane of the wafer includes 4 5 angles with each other and the corresponding metallization of the corresponding wafer 2 2 · 5 or 6 7 . 5 ° angle. FIG. 2 shows a cross section of an embodiment of a semiconductor wafer stack, in which a j-th other wafer 11 and a second other wafer 12 are disposed in a lower semiconductor wafer 1. These semiconductor wafers are interconnected by their upper sides 3, which are coplanar with the {1,0,0} plane of the substrate or semiconductor crystal. In the simplified description shown in Figure 2, the metallization of the structures between the semiconductor wafers is omitted.
第8頁 1242280 五、發明說明（6) 依據本發明，晶片邊緣4，5在圖二所示之截面的側邊或 在圖式的平面中不與其它主晶體面{0，1，0}及{0,0，1} 一 致。相反地，晶片邊緣相對於這些主晶體面朝向不同的角 度。因此，晶片可以在邊緣共形下被互相重疊，因此，二 連續半導體晶片，較佳者為成對的半導體晶片，之位於垂 直上側3之該主晶體面相互間角度不為0 °或9 0 ° 。 垂直於半導體晶片1之主晶體面可以，例如與垂直於第 一另外晶片1 1之上側3之一主晶體面形成5 5 °的角度。垂 直於第一另外晶片1 1之上側3之主晶體面可以例如，與垂 直第二另一半導體晶片1 2之上側3之一主晶體面形成1 7 ° __ 角。此結果也造成一個55° - 17°二38°或55° + 17°二 72°的角度，因此與其它角55°及17°不同，出現在較低 半導體晶片1之對應主晶體面與第二另一半導體晶片1 2之 主晶體面之間。因此，於此例中，不僅二連續對之半導體 晶片之對應主晶體面之間的角度，而且任何二晶體對之主 平面之間的角度相互不同。 半導體晶片堆豐之晶片的相互連接相對於主晶體面朝向 不同角度。這已經提供對斷裂的特定阻力。積體電路之半 導體元件本身的結構隨後可以與其線性或平面結構平行或 與於半導體晶體或基板之主晶體面共平面。但是，在一較4 佳實施例中，這些元件本身的結構也朝向相對主晶體面大 於0 °小於9 0 °之角度。 在相互連接之二主要方向在垂直的主晶體面外側但依然 如以前般可以平行半導體元件之基板的情況是有盈的。在Page 8 1242280 5. Description of the invention (6) According to the present invention, the wafer edges 4, 5 are not on the side of the cross section shown in FIG. 2 or in the plane of the figure with other main crystal planes {0, 1, 0} Consistent with {0,0,1}. Conversely, the wafer edges face different angles with respect to these main crystal faces. Therefore, the wafers can be overlapped with each other under the edge conformation. Therefore, two continuous semiconductor wafers, preferably paired semiconductor wafers, which are located on the vertical upper side 3 and the main crystal planes are not at an angle of 0 ° or 9 0 to each other °. The main crystal plane perpendicular to the semiconductor wafer 1 may, for example, form an angle of 5 5 ° with one of the main crystal planes perpendicular to the upper side 3 of the first other wafer 1 1. The main crystal plane perpendicular to the upper side 3 of the first other wafer 1 1 may, for example, form an angle of 17 ° with one of the main crystal planes perpendicular to the upper side 3 of the second other semiconductor wafer 12. This result also results in an angle of 55 °-17 ° to 38 ° or 55 ° + 17 ° to 72 °, so it is different from other angles of 55 ° and 17 °, and appears on the corresponding main crystal plane and Between the main crystal planes of two other semiconductor wafers 12. Therefore, in this example, not only the angles between the corresponding principal crystal planes of two consecutive pairs of semiconductor wafers, but also the angles between the principal planes of any two crystal pairs are different from each other. The interconnections of semiconductor wafer stacks are oriented at different angles with respect to the main crystal plane. This has provided specific resistance to fracture. The structure of the semiconductor element itself of the integrated circuit can then be parallel to its linear or planar structure or coplanar with the main crystal plane of the semiconductor crystal or substrate. However, in a more preferred embodiment, the structure of these elements is also oriented at an angle greater than 0 ° to less than 90 ° with respect to the main crystal plane. There is a surplus in the case where the two main directions of interconnection are outside the vertical main crystal plane but still parallel to the semiconductor element as before. in
第9頁 1242280 五、發明說明（7) 一特定的，較佳的半導體晶片堆疊中，此半導體晶片堆疊 之半導體晶片的方向可以於不同導體晶片之相互連接被設 置為相互間0 °至9 0 °的方式中被設定，如同習知晶片堆 疊的方式。 因為相互連接相對於個別基板之主晶體面之不同的方 向，在半導體晶片堆疊中出現隨晶片而變之主晶體面之方 向。因此，垂直於晶片上側，亦及垂直於{ 1，0，0 }面，沒 有連續穿過整個半導體晶片堆疊之均勾的主晶體平面。這 大大地增加半導體晶片堆疊對斷裂的阻力。因此，此種型 態的半導體晶片堆疊可以被應用於最多1 8 5 // m厚度，即使. 具有三或更多半導體晶片，允許它們被使用於標準的晶片 卡中。在圖二所示的實施例中，此半導體晶片1是，例 如，130// m厚，此第一另一半導體晶片11為30// m厚而第 二另一半導體晶片12為20//Π1厚。 1242280Page 9 1242280 V. Description of the invention (7) In a specific and preferred semiconductor wafer stack, the direction of the semiconductor wafers of the semiconductor wafer stack can be set to be between 0 ° to 9 0 with respect to the interconnection of different conductor wafers. ° is set in the same way as in conventional wafer stacking. Because of the different directions of the interconnections with respect to the main crystal plane of the individual substrates, the direction of the main crystal plane that varies from wafer to wafer appears in a semiconductor wafer stack. Therefore, perpendicular to the upper side of the wafer and also perpendicular to the {1,0,0} plane, there is no uniform main crystal plane passing continuously through the entire semiconductor wafer stack. This greatly increases the resistance of the semiconductor wafer stack to fracture. Therefore, this type of semiconductor wafer stack can be applied up to a thickness of 1 8 5 // m, even if it has three or more semiconductor wafers, allowing them to be used in standard wafer cards. In the embodiment shown in FIG. 2, the semiconductor wafer 1 is, for example, 130 // m thick, the first other semiconductor wafer 11 is 30 // m thick, and the second other semiconductor wafer 12 is 20 // Π1 thick. 1242280
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