TWI785607B - Semiconductor device packages with angled pillars for decreasing stress - Google Patents

Abstract

Semiconductor devices having mechanical pillar structures, such as angled pillars, that are rectangular and orientated with respect to a semiconductor die to reduce bending stress and in-plane shear stress at a semiconductor die to which the angled pillars are attached, and associated systems and methods, are disclosed herein. The semiconductor device can include angled pillars connected to the semiconductor die and to a package substrate. The angled pillars can be configured such that they are orientated relative to a direction of local stress to increase section modulus.

Description

Semiconductor device package with angled legs for stress reduction

The present technology generally relates to semiconductor devices with pillars, and more specifically, in some embodiments, to angled pillars for die-to-die, die-to-substrate, and/or package-to-package interconnects orientation.

Microelectronic devices, such as memory devices, microprocessors, and light emitting diodes, typically include one or more semiconductor die mounted to a substrate. A semiconductor die may include functional features such as memory cells, processor circuits, and interconnect circuitry. A semiconductor die also typically includes bond pads electrically coupled to functional features, active posts electrically coupled to active bond pads, and dummy posts for structural support. The functional posts may be pins or other types of structures used to connect the semiconductor die to bus bars, circuits, or other assemblies.

The semiconductor die may be electrically coupled to another substrate via a flip-chip die attach process (eg, thermocompression bonding (TCB) or mass reflow operations) in which conductive pillars are formed on the bonding pads, or Other regions of the die are coupled to the substrate via a bonding material disposed between the conductive pillars and the substrate. For example, the functional posts are attached to conductive terminals on the substrate. To attach the bonding material to the substrate, the semiconductor package is heated to reflow the bonding material and form a firm connection. However, heating and/or subsequent cooling of the semiconductor package as well as thermal cycling during product reliability testing and power cycling during end-customer use can induce loss of the coefficient of thermal expansion (CTE) between the semiconductor die and the substrate and thus the coefficient of thermal expansion (CTE) of these components. Significant thermo-mechanical stresses due to matching. Often, stress can induce interfacial delamination and crack growth in the semiconductor die passivation material near one or more bond pads, which can render the semiconductor package inoperable.

In one embodiment, a semiconductor device includes: a package substrate including circuit elements; a semiconductor die including an integrated circuit system, functional bonding pads electrically coupled to the integrated circuit system, and a An electrically isolated inactive junction region of the system, wherein the semiconductor die has an active surface having a reference major axis, a reference minor axis orthogonal to the reference major axis, and die center coordinates; Between the substrate and the semiconductor die, wherein the inclined pillars have a non-circular cross-sectional shape, the non-circular cross-sectional shape has a pillar long axis, a pillar short axis, and a pillar center coordinate, wherein the pillar long axis is at least the same as through A line of the die center coordinates and the pillar center coordinates is substantially orthogonal, and wherein the line is at an oblique angle relative to the reference major axis and the reference minor axis.

In another embodiment, a method of forming a semiconductor device includes forming slanted pillars on a semiconductor die including integrated circuitry, active bond pads electrically coupled to the integrated circuitry, and The electrically isolated non-active junction region of the integrated circuit system, wherein the semiconductor die also has an active surface, the active surface has a reference major axis, a reference minor axis orthogonal to the reference major axis, and die center coordinates, and the The equi-sloping strut has a non-circular cross-sectional shape having a strut major axis, a strut minor axis, and a strut center coordinate, and wherein the strut major axis is at least at least the same as the grain center coordinate and the strut center coordinate substantially orthogonal to a line at an oblique angle relative to the reference major axis and the reference minor axis; and attaching the oblique struts to the package substrate.

In another embodiment, a semiconductor device includes: a packaging substrate including circuit elements; a semiconductor die including an integrated circuit system, functional bonding pads electrically coupled to the integrated circuit system, and a Circuitry electrically isolated non-active junction regions, wherein the semiconductor die also has longitudinal and lateral dimensions; and slanted posts between the substrate and the semiconductor die, wherein the slanted posts have non-circular cross-sections Shape, the non-circular cross-sectional shape has a first dimension, a second dimension orthogonal to the first dimension and smaller than the first dimension, and a pillar center coordinate, wherein the second dimension is along relative to the longitudinal dimension and the transverse direction The two dimensions extend along an axis at a non-zero angle.

Specific details of several embodiments of semiconductor devices having mechanically rectangular pillars that slope based on local directionality of stress to increase the section modulus and thereby reduce the distance between the sloped pillars and the semiconductor die are disclosed. The bending stress at the interface and the in-plane shear stress. The term "semiconductor device" generally refers to a solid-state device that includes one or more semiconductor materials. Examples of semiconductor devices include logic devices, memory devices, microprocessors, diodes, and the like. Additionally, the term "semiconductor device" may refer to a finished device or an assembly or other structure at various stages of processing prior to becoming a finished device. Depending on the context in which it is used, the term "substrate" may refer to a wafer-level substrate or may refer to a singulated die-level substrate. Those of ordinary skill in the relevant art will recognize that the methods described herein can be performed at the wafer level or at the die level. In addition, unless the context dictates otherwise, conventional semiconductor fabrication techniques may be used to form the structures disclosed herein. For example, materials may be deposited using chemical vapor deposition, physical vapor deposition, atomic layer deposition, spin coating, and/or other suitable techniques. Similarly, material may be removed using, for example, plasma etching, wet etching, chemical mechanical planarization, or other suitable techniques. Those skilled in the relevant art will also appreciate that the technology is possible with additional embodiments and that the technology can be practiced without several of the details of the embodiments described below with reference to FIGS. 1A-3A and FIGS. 4-6 .

In several embodiments described below, a semiconductor device may include a semiconductor substrate containing circuit elements, active bond pads and/or inactive bond regions, and angled pillars oriented at an angle relative to a reference orthogonal axis. The semiconductor device may also include alignment pillars parallel or perpendicular to the reference orthogonal axis. The pillars of the semiconductor device can be attached to the terminals of the packaging substrate by the bonding material. Some of the angled posts may be connected to electrically inactive junction areas, such as areas on passivation material on the semiconductor substrate. Such pillars are called dummy pillars. Other posts may be electrically connected to electrically active bond pads that are electrically coupled to power, ground, and/or other circuit elements of the semiconductor substrate. Such struts are functional struts, and they may be angled struts and/or alignment struts. The angled struts may have a rectangular cross-section and be oriented at an angle relative to a reference orthogonal axis (eg, an angle other than parallel or perpendicular to an orthogonal axis aligned with the edge of the semiconductor substrate). In some embodiments, some or all of the angled struts may be oriented at different angles of inclination, or some or all of the angled struts may be oriented at the same angle of inclination. The angled struts may be oriented at an angle based on the local direction of die-to-package interface (CPI) stress caused by, for example, a mismatch between the coefficient of thermal expansion (CTE) of the semiconductor die and the CTE of the package substrate. Accordingly, the angled posts can lower the bond pad and/or around the bond region after, for example, a flip-chip die attach process (e.g., thermocompression bonding (TCB) or mass reflow) has been performed and/or during operation (e.g., power cycling or extreme temperature environments) the possibility of mechanical failure.

At the beginning of the TCB operation, heating reflows the bonding material in the interconnect and electrically connects the conductive posts to the package substrate. Semiconductor packages are typically heated to 200° C. or higher (eg, above about 217° C.) to reflow the bonding material. During TCB operation, compressive forces are also applied to attach the interconnects to the packaging substrate. One disadvantage of TCB operation is that cooling of the semiconductor package can twist or bend the semiconductor die and package substrate relative to each other, which can stress the posts. For example, the CTE of a semiconductor die may differ from the CTE of the packaging substrate, and the CTE difference may cause the semiconductor die and packaging substrate to distort relative to each other during cooling and/or heating of the semiconductor package. Therefore, the package substrate 102 may have a distorted non-planar shape after cooling. In other embodiments, the semiconductor die or both the semiconductor die and the packaging substrate may have a non-planar twisted shape after cooling. CTE differences between the semiconductor die and packaging substrate can cause interconnects to be stressed and bowed laterally. This can allow cracks to form and propagate within the semiconductor substrate, which can lead to mechanical and/or electrical failures.

Many embodiments of the present technology are described below in the context of a mechanical strut structure having a rectangular cross-section and inclined relative to the stress direction to provide sufficient section modulus to withstand CPI stress. Those of ordinary skill in the relevant art will also understand that the present technology can have embodiments for forming mechanical strut structures with rectangular cross-sections on either the first side or the second side of the substrate assembly, and that these mechanical strut structures can be used in conjunction with Used in the context of other electrical connectors associated with semiconductor assemblies. Accordingly, the present technique may be practiced without several of the details of the embodiments described herein with reference to FIGS. 1A-3A and 4-6 . For example, some details of semiconductor devices and/or packages that are well known in the art have been omitted so as not to obscure the present technology. In general, it should be understood that various other devices and systems in addition to the specific embodiments disclosed herein may be within the scope of the present technology.

For ease of reference, the same reference numerals are used throughout this disclosure to identify similar or analogous components or features, but use of the same reference numerals does not imply that the features are understood to be identical. In fact, in many of the examples described herein, like-numbered features have multiple embodiments that differ from each other in structure and/or function. Furthermore, unless specifically noted herein, identical coloring may be used to indicate materials in cross-section that may be compositionally similar, but use of the same coloring does not imply that the materials are to be understood as identical.

As used herein, the terms "vertical," "lateral," "upper," "lower," "above," and "below" may refer to the relative orientation or position of features in a semiconductor device in view of the orientation shown in the figures. For example, "top" or "topmost" may refer to a feature positioned closer to the top of the page than another feature. However, these terms should be interpreted broadly to include semiconductor devices having other orientations such as upside-down or oblique orientations, where top/bottom, up/down, up/down, up/down, and left/right may depend on Orientation and exchange.

1A is a plan view of a semiconductor package 100 ("package 100") having angled posts 120 configured in accordance with an embodiment of the present technology. The package 100 may include a package substrate 102 , a semiconductor die 110 , and an angled pillar 120 extending between the package substrate 102 and the semiconductor die 110 . Slanted struts 120 may be oriented at an oblique angle relative to a reference axis, such as non-perpendicular and non-parallel angles relative to a reference orthogonal axis defined by the edges of semiconductor die 110 . In some embodiments, angled struts 120 may be referred to as outriggers. The package 100 may further include alignment posts 130 at least substantially perpendicular or parallel to the reference axis. Depending on the application, slanted posts 120 and/or alignment posts 130 may be "active posts" that are electrically coupled to circuitry in package substrate 102 and/or semiconductor die 110, or slanted posts 120 and/or alignment posts 130 may be “dummy pillars” that are not electrically coupled to one or both of package substrate 102 and/or semiconductor die 110 .

FIG. 1B is a diagram of a coordinate system with reference axes of FIG. 1A and an example orientation of sloped pillars 120 of semiconductor die 110 in accordance with an embodiment of the present technology. As shown in FIGS. 1A and 1B , angled struts 120 can have a non-circular cross-sectional shape (e.g., rectangular, oval, elliptical, square, straight, or irregular) with a major axis 140, a minor axis 142 And the center coordinate 144. The edges of the slanted struts 120 may define a plan view of the slanted struts 120 . The center coordinate 144 may be defined by the centroid of the plan view of the inclined strut 120 . In the illustrated embodiment, major axis 140 and minor axis 142 define a plane of slanted pillar 120 that is parallel to the active surface of semiconductor die 110 . In some other embodiments, the major axis 140 and the minor axis 142 may define a plane of the slanted pillar 120 that is normal to the active surface of the semiconductor die 110 . The active surface of the semiconductor die 110 may have a reference major axis 150, a reference minor axis 152, and a center coordinate 154 at the center of the active surface. Reference major axis 150 and reference minor axis 152 may define reference orthogonal axes. When the semiconductor die 110 has a linear footprint, the reference major axis 150 can be at least substantially parallel to one edge of the semiconductor die 110 , and the reference minor axis 152 can be at least substantially parallel to an orthogonal edge of the semiconductor die 110 . The edges of the semiconductor die 110 may define a plan view of the semiconductor die 110 . The center coordinate 154 may be defined by the centroid of the plan view of the semiconductor die 110 . Slanted strut 120 is oriented such that line 148 passing through center coordinate 144 and central coordinate 154 is (a) at least approximately normal to major axis 140 of slanted strut 120, and (b) is perpendicular to reference major axis 150 and minor axis 152. a certain angle of inclination. In some embodiments, substantially orthogonal includes 90 degrees plus or minus 2 to 8 degrees, 3 to 7 degrees, 4 to 6 degrees, and 5 degrees. In some embodiments, the angled pillars 120 may be configured on the semiconductor die 110 with a rotation angle 156 denoted as _θi . The rotation angle 156 can be defined as θ _i =tan ⁻¹ (h _i /w _i ), where (h _i , w _i ) is the coordinate position of the center coordinate 154 of the inclined pillar 120 relative to the active surface of the semiconductor die 110 .

In the embodiment shown in FIG. 1A , there are 36 inclined posts 120 and 20 active posts 130 , but package 100 may include fewer or more inclined posts 120 and active posts 130 . For example, the package 100 may include tens, hundreds, thousands or more inclined pillars 120 arranged between the semiconductor die 110 and the package substrate 102 and tens, hundreds, thousands or more functional strut 130. In some embodiments, the slanted pillars 120 on the semiconductor die 110 may have the same dimensions (eg, length, width, and height). In other embodiments, some slanted pillars 120 on the semiconductor die 110 may have the same size, while other slanted pillars 120 may have different sizes. In other embodiments, each slanted pillar 120 on the semiconductor die 110 may have a different size.

FIG. 1C is a cross-sectional view of the package 100 shown in FIG. 1A along line 1C-1C. In the illustrated embodiment, the semiconductor die 110 includes a semiconductor substrate 112 (eg, a silicon substrate, a gallium arsenide substrate, an organic laminate substrate, etc.) having a first side/surface 113 a and a first side surface 113 a. The second side/surface 113b opposite to 113a. The first side 113a of the semiconductor substrate 112 may be an active side that includes one or more circuit elements 114 (e.g., schematically shown wires, traces, interconnects, etc.) formed in and/or on the first side 113a. components, transistors, etc.) and function bonding pads 118. Circuit elements 114 may include, for example, memory circuits (eg, dynamic random access memory (DRAM) or other types of memory circuits), controller circuits (eg, DRAM controller circuits), logic circuits, and/or other circuits. In other embodiments, semiconductor substrate 112 may be a "blank" substrate that does not include integrated circuit components and is formed of, for example, crystalline, semi-crystalline, and/or ceramic substrate materials such as silicon, polysilicon, alumina (Al ₂ O ₃ ), sapphire and/or other suitable materials.

Package substrate 102 may include an interposer, a printed circuit board, a dielectric spacer, another semiconductor die (eg, a logic die), or another suitable substrate with circuitry such as a redistributed structure. The package substrate 102 may further include functional bonding pads 105 and electrical connectors 103 (e.g., solder balls, conductive bumps, conductive posts, conductive epoxy, and/or other suitable conductive materials) electrically coupled to the functional bonding pads 105. element). Functional bonding pads 105 and electrical connectors 103 are configured to electrically couple package 100 to an external device or circuitry (not shown). Package substrate 102 may also include inactive pads 108 that are not electrically coupled to circuitry.

In the depicted embodiment, the first side 113a of the semiconductor substrate 112 faces the package substrate 102 (eg, in a direct die attach (DCA) configuration). In other embodiments, semiconductor die 110 may be configured differently. For example, the second side 113 b of the semiconductor substrate 112 may face the packaging substrate 102 , and the semiconductor die 110 may include one or more TSVs extending through the semiconductor substrate 112 to electrically couple the circuit element 114 to the active pillar 120 . Furthermore, while only a single semiconductor die 110 is shown in FIG. 1C , in other embodiments, package 100 may include one or more additional semiconductor dies stacked on and/or over semiconductor die 110 .

In the depicted embodiment, semiconductor die 110 may be mechanically connected to package substrate 102 by connecting non-active angled posts 120 to non-active bonding pads 108 through bonding material 106 . Slanted pillars 120 may be electrically isolated from semiconductor die 110 and formed of a material such as copper. Active pillar 130 may be electrically connected to active bond pad 118 of semiconductor die 110 via bonding material 106 . The active posts 130 may be formed of any suitable conductive material such as copper, nickel, gold, silicon, tungsten, conductive epoxy, combinations thereof, and may be formed by using electroplating, electroless-plating, or other suitable processes. . In some embodiments, a barrier material (not shown) such as nickel, nickel-based intermetallics, and/or gold may be formed over the end portions of the active pillars 130 . The barrier material may facilitate bonding, and/or prevent or at least inhibit electromigration of copper or other metals used to form functional posts 130 .

In some embodiments, the package 100 may further include an underfill or molding material formed on the package substrate 102 and/or at least partially surrounding the semiconductor die 110 . In some embodiments, package 100 may include other components such as an external heat sink, a housing (eg, a thermally conductive housing), electromagnetic interference (EMI) shielding components, and the like.

FIGS. 2A and 2B are cross-sectional and perspective views, respectively, of a portion of the semiconductor package 100 shown in FIG. 1C and a slanted post 120 configured in accordance with an embodiment of the present technology. The angled struts 120 may have a rectangular cross-sectional shape instead of a rectangular, circular or square cross-sectional shape. FIG. 2B shows slanted pillars 120 connected to passivation material of semiconductor die 110 and inactive pads 108 of package substrate 102 by bonding material 106 . In some embodiments, the slanted pillars 120 can be connected to the semiconductor die 110 by bonding materials and bonding pads. Active strut 130 may include features generally similar to those of inclined strut 120 . As shown in FIGS. 2A and 2B , angled pillars 120 are oriented at an angle of inclination relative to reference major axis 150 and reference minor axis 152 of semiconductor die 110 .

FIG. 3A is a graph showing stress directionality relative to a slanted strut 120 configured in accordance with an embodiment of the present technology, and FIG. 3B is a graph showing stress directionality relative to a conventional circular strut 320 . In FIG. 3A, the angled struts 120 may be oriented obliquely such that the long axes of the angled struts are at least substantially perpendicular to the direction of local stress to increase the section modulus. Since CTE mismatch and twist are the two main components that cause thermomechanical stress, crack initiation and crack propagation at semiconductor die 110 occurs primarily in mixed mode fracture (e.g., mode I: exfoliation, and mode II: in-plane cut). Due to thermal loading conditions during various assembly and testing events, the direction of maximum local stress is not horizontal or vertical in slanted struts 120, but is based on the location of slanted struts 120 relative to the center of semiconductor die 110 And change. The rectangular cross-section may provide a greater section modulus than circular struts when the slanted struts 120 are oriented obliquely in the direction of stress. The increased section modulus can help reduce bending stress and in-plane shear stress at the semiconductor die 110, which is expected to reduce cracking, delamination, and other undesirable events. The cross-sectional area of the inclined struts 120 can be constant or increased depending on the pitch to reduce normal stress.

Comparing FIGS. 3A and 3B , the stress profile in the passivation material is significantly smaller in the case of slanted struts 120 ( FIG. 3A ), such as at the slanted struts of the outermost corners, than that of circular struts 320 ( FIG. 3B ). More specifically, the magnitude and magnitude of the stress indicated at the upper right region of the slanted strut 120 is less than the magnitude and magnitude of the stress of the circular strut 320 . Thus, angled struts 120 are expected to provide improved delamination and in-plane shear stress compared to circular struts.

Table 1 shows the dramatic improvement in peel stress and in-plane shear stress reduction when rectangular slanted pillars are in the outermost corners of the semiconductor package compared to circular pillars. For example, the maximum peel stress and maximum in-plane shear stress of circular pillars are 625MPa and 191MPa, respectively. The maximum peeling stress and the maximum in-plane shear stress of square pillars are 15% higher (721MPa) and 27% lower (139MPa) than those of circular pillars, respectively. The maximum peel stress and the maximum in-plane shear stress of the rectangular inclined strut 120 are 24% (478 MPa) and 42% (110 MPa) lower than that of the circular strut, respectively. pillar shape Maximum Peeling Stress (MPa) % Difference from Baseline Maximum in-plane shear stress (MPa) % Difference from Baseline round 625 baseline 191 baseline square 721 15% 139 -27% The proposed rotated rectangle 478 -twenty four% 110 -42%

4A-4C are cross-sectional views of angled struts having various shapes in accordance with embodiments of the present technology. FIG. 4A illustrates a sloped strut 120 comprising a rectangular cross-sectional shape. FIG. 4B depicts a slanted strut 402 comprising an oval or elliptical cross-sectional shape. FIG. 4C illustrates a slanted strut 404 comprising a rectangular cross-sectional shape. In the depicted embodiments, the angled struts 120, 402, and 404 along the major axis 140 are longer in length than they are wide. The shape of the sloping struts may include, but is not limited to, irregular shapes, straight lines, and trapezoids.

5A-5D illustrate slanted pillars and bond pads of semiconductor package 100 having various shapes and configured in accordance with embodiments of the present technology. Various shapes and sizes of bonding pads can be used to cover the entire cross-section of the angled struts. FIG. 5A shows a rectangular bond pad 108 covering the entire cross-section of a rectangular slanted post 120 . FIG. 5B depicts circular bond pads 508 covering the entire cross-section of rectangular slanted struts 120 . FIG. 5C depicts circular bond pads 508 covering the entire cross-section of ovoid or elliptical slanted struts 402 . FIG. 5D depicts circular bond pads 508 covering the entire cross-section of rectangular slanted struts 404 . Active strut 130 may also possess similar features to those of the inclined struts depicted in FIGS. 5A-5D . 5A-5D illustrate the formation of pillar on pad; however, these embodiments can also be used in conjunction with the application of pillar on trace.

6 is a schematic diagram of a system including a semiconductor assembly configured in accordance with an embodiment of the present technology. Any of the semiconductor devices and/or packages having the features described above with reference to FIGS. 1A-1C, 2A-2B, 3A, 4A-4C, 5A-5D may be incorporated into A representative example of any of a number of larger and/or more complex systems is the system 600 shown schematically in FIG. 6 . System 600 may include processor 602 , memory 604 (eg, SRAM, DRAM, Flash, and/or other memory devices), input/output devices 606 , and/or other subsystems or components 608 . The semiconductor die and/or packages described above with reference to FIGS. 1A-1C, 2A-2B, 3A, 4A-4C, 5A-5D may include any of the elements shown in FIG. middle. The resulting system 600 can be configured to perform any of a wide variety of suitable computing, processing, storage, sensing, imaging, and/or other functions. Accordingly, representative examples of system 600 include, but are not limited to, computers and/or other data processors, such as desktop computers, laptop computers, Internet appliances, handheld devices (e.g., palmtops, wearable computers, cellular or mobile phones, personal digital assistants, music players, etc.), tablet computers, multi-processor systems, processor-based or programmable consumer electronic devices, networked computers and microcomputers. Additional representative examples of system 600 include lights, cameras, vehicles, and the like. Regarding these and other examples, system 600 may be housed in a single unit or distributed over multiple interconnected units, such as by a communication network. Accordingly, components of system 600 may include any of a wide variety of suitable computer-readable media, local and/or remote memory storage devices.

From the foregoing it should be appreciated that specific embodiments of the technology have been described herein for purposes of illustration, but that various modifications may be made without departing from the invention. Accordingly, the present invention is not limited beyond the scope of the appended claims. Furthermore, certain aspects of the novel techniques described in the context of particular embodiments may also be combined or eliminated in other embodiments. Furthermore, while advantages associated with certain embodiments of the new technology have been described in the context of those embodiments, other embodiments may exhibit such advantages, and not all embodiments will exhibit such advantages to fall within the scope of the technology. Accordingly, the disclosure and associated technology can encompass other embodiments not expressly shown or described herein.

100: semiconductor package 102: packaging substrate 103: electrical connector 105: bonding pad 106: bonding material 108: non-active pad 110: semiconductor die 112: semiconductor substrate 113a: first side/surface 113b: second side/surface Surface 114: Circuit Element 118: Active Bonding Pad 120: Slanted Post 130: Alignment Post 140: Major Axis 142: Minor Axis 144: Center Coordinate 148: Line 150: Reference Major Axis 152: Reference Minor Axis 154: Center Coordinate 156 : Rotation angle 320: Circular strut 402: Slanted strut 404: Slanted strut 508: Circular joint pad 600: System 602: Processor 604: Memory 606: Input/output device 608: Other subsystems or components 1C-1C : line θ _i : rotation angle

Many aspects of the present technology can be better understood with reference to the following figures. Components in the drawings are not necessarily drawn to scale. Rather, the emphasis is on clearly illustrating the principles of the inventive technique.

1A is a plan view of a semiconductor package with slanted pillars configured in accordance with an embodiment of the present technology; FIG. 1B is a coordinate system diagram of an example orientation of slanted pillars with the reference axis of FIG. 1A and a semiconductor die; and FIG. 1C is A cross-sectional view of the semiconductor package shown in FIG. 1A along line 1C-1C.

2A and 2B are cross-sectional and perspective views, respectively, of a portion of the semiconductor package shown in FIG. 1C and a slanted post configured in accordance with an embodiment of the present technology.

Figure 3A is a graph showing stress directionality relative to a slanted strut configured in accordance with an embodiment of the present technology, and Figure 3B is a graph showing stress directionality relative to a conventional circular strut.

4A-4C are cross-sectional views of angled struts having various shapes in accordance with embodiments of the present technology.

5A-5D illustrate slanted pillars and bonding pads of semiconductor packages having various shapes in accordance with embodiments of the present technology.

6 is a schematic diagram of a system including a semiconductor assembly configured in accordance with an embodiment of the present technology.

100: Semiconductor packaging

102: Package substrate

110: Semiconductor grain

120: Slanted pillar

130: Alignment pillar

148: line

150: Reference major axis

152: Reference minor axis

1C-1C: Line

Claims (20)

A semiconductor device comprising: A packaging substrate including circuit elements; A semiconductor die comprising integrated circuitry, active bonding pads electrically coupled to the integrated circuitry, and inactive bonding regions electrically isolated from the integrated circuitry, wherein the semiconductor die has an active surface , the active surface has a reference major axis, a reference minor axis orthogonal to the reference major axis, and a grain center coordinate; and Inclined pillars between the substrate and the semiconductor die, wherein the inclined pillars have a non-circular cross-sectional shape, the non-circular cross-sectional shape has a pillar major axis, a pillar minor axis, and a pillar center coordinate , wherein the pillar major axis is at least substantially orthogonal to a line passing through the die center coordinates and the pillar center coordinates, and wherein the line forms an oblique angle with respect to the reference major axis and the reference minor axis. The semiconductor device according to claim 1, wherein the substantially orthogonal is 90 degrees plus or minus 2 to 8 degrees, 3 to 7 degrees, 4 to 6 degrees or 5 degrees. The semiconductor device according to claim 1, wherein the non-circular cross-sectional shape is a rectangle. The semiconductor device according to claim 1, wherein the non-circular cross-sectional shape includes an oval, an ellipse, a square, a straight line or an irregular shape. The semiconductor device of claim 1, wherein at least some of the angled pillars are electrically coupled to a functioning bond pad of the semiconductor die. The semiconductor device of claim 1, wherein at least some of the slanted pillars are connected to an inactive junction region of the semiconductor die. The semiconductor device according to claim 1, further comprising alignment pillars having a pillar major axis at least substantially parallel to the reference major axis or one of the reference minor axes, and wherein the alignment pillars The quasi-posts are electrically coupled to functional bond pads of the semiconductor die. The semiconductor device according to claim 1, further comprising alignment pillars having a pillar major axis at least substantially parallel to the reference major axis or one of the reference minor axes, and wherein the alignment pillars The quasi-pillars are electrically coupled to active bonding pads of the semiconductor die, and the angled pillars are coupled to non-active bonding regions of the semiconductor die. The semiconductor device of claim 1, further comprising alignment posts having a post major axis at least substantially parallel to the reference long axis or the reference short axis, and wherein the alignment posts are electrically coupled connected to active bond pads of the semiconductor die, a first set of the slanted posts electrically coupled to the active bond pads of the semiconductor die, and a second set of the slanted posts coupled to the semiconductor die the non-active junction area. A method of forming a semiconductor device, the method comprising: Slanted pillars are formed on a semiconductor die comprising integrated circuitry, active bond pads electrically coupled to the integrated circuitry, and inactive bond regions electrically isolated from the integrated circuitry, wherein The semiconductor die also has an active surface having a reference major axis, a reference minor axis orthogonal to the reference major axis, and a die center coordinate, and the inclined struts have a non-circular cross-section shape, the non-circular cross-sectional shape has a pillar major axis, a pillar minor axis, and a pillar center coordinate, and wherein the pillar major axis is at least approximately orthogonal to a line passing through the grain center coordinate and the pillar center coordinate, the line forms an oblique angle with respect to the reference major axis and the reference minor axis; and The angled posts are attached to a packaging substrate. The method according to claim 10, wherein the roughly orthogonal is 90 degrees plus or minus 2 to 8 degrees, 3 to 7 degrees, 4 to 6 degrees or 5 degrees. The method of claim 10, wherein the non-circular cross-sectional shape is rectangular. The method of claim 10, wherein the non-circular cross-sectional shape includes oval, ellipse, square, straight line or irregular shape. The method of claim 10, wherein at least some of the pillars are electrically coupled to a functional bond pad of the semiconductor die. The method of claim 10, wherein at least some of the pillars are connected to an inactive junction region of the semiconductor die. The method of claim 10, further comprising aligning struts having at least one strut major axis substantially parallel to the reference major axis or one of the reference minor axes, and wherein the aligning struts The pillars are electrically coupled to functional bond pads of the semiconductor die. The method of claim 16, further comprising aligning struts having a strut major axis at least substantially parallel to one of the reference major axis or the reference minor axis, and wherein the aligning struts The pillars are electrically coupled to active bond pads of the semiconductor die, and the angled pillars are coupled to inactive bond regions of the semiconductor die. The method of claim 16, further comprising aligning struts having a strut major axis at least substantially parallel to the reference major axis or the reference minor axis, and wherein the alignment struts are electrically coupled to the active bonding pads of the semiconductor die, a first set of the angled pillars electrically coupled to the active bond pads of the semiconductor die, and a second set of the angled pillars coupled to the semiconductor die Non-active junction area. A semiconductor device comprising: A packaging substrate including circuit elements; A semiconductor die comprising integrated circuitry, active bonding pads electrically coupled to the integrated circuitry, and inactive bonding regions electrically isolated from the integrated circuitry, wherein the semiconductor die also has a longitudinal dimension and a transverse dimension; and Slanted struts between the substrate and the semiconductor die, wherein the slanted struts have a non-circular cross-sectional shape with a first dimension orthogonal to the first dimension and less than A second dimension of the first dimension and a strut center coordinate, wherein the second dimension extends along an axis forming a non-zero angle with respect to both the longitudinal dimension and the transverse dimension. The semiconductor device of claim 19, further comprising alignment posts having a post major axis at least substantially parallel to the longitudinal dimension or the lateral dimension, and wherein the alignment posts are electrically coupled to Functional bonding pads of the semiconductor die, a first set of the slanted pillars electrically coupled to the functional bonding pads of the semiconductor die, and a second set of the slanted pillars coupled to non-functional bonding pads of the semiconductor die Active junction area.

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