WO2004015752A1 - ウェーハの研磨方法及び装置 - Google Patents
ウェーハの研磨方法及び装置 Download PDFInfo
- Publication number
- WO2004015752A1 WO2004015752A1 PCT/JP2003/009658 JP0309658W WO2004015752A1 WO 2004015752 A1 WO2004015752 A1 WO 2004015752A1 JP 0309658 W JP0309658 W JP 0309658W WO 2004015752 A1 WO2004015752 A1 WO 2004015752A1
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- WO
- WIPO (PCT)
- Prior art keywords
- polishing
- wafer
- holding
- divided
- stage
- Prior art date
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Classifications
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B37/00—Lapping machines or devices; Accessories
- B24B37/27—Work carriers
- B24B37/30—Work carriers for single side lapping of plane surfaces
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B37/00—Lapping machines or devices; Accessories
- B24B37/04—Lapping machines or devices; Accessories designed for working plane surfaces
- B24B37/042—Lapping machines or devices; Accessories designed for working plane surfaces operating processes therefor
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B37/00—Lapping machines or devices; Accessories
- B24B37/34—Accessories
- B24B37/345—Feeding, loading or unloading work specially adapted to lapping
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02024—Mirror polishing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
Definitions
- the present invention relates to a method and an apparatus for polishing a wafer which can prevent surface sagging due to polishing and produce a wafer having a high flatness, in particular, a silicon on insulator (SOI) wafer.
- SOI silicon on insulator
- a method for producing a mirror-polished wafer having such a high flatness is generally a single-crystal growth in which a single-crystal ingot is produced using a Czochralski (CZ) method, a floating zone (FZ) method, or the like. And a wafer manufacturing (processing) step in which the single crystal ingot is sliced and at least one principal surface is mirror-finished.
- the manufactured mirror-finished polishing wafer is A device is formed using the device.
- the SOI wafer 50 has an SOI layer 52 (also referred to as a semiconductor layer or an active layer) for forming an element such as a single-crystal silicon layer. It has a structure formed on layer 54 (buried (BOX) oxide layer or simply oxide layer).
- the insulating layer 54 is formed on a supporting substrate 56 (also referred to as a substrate layer), and has a structure in which an SOI layer 52, an insulating layer 54, and a supporting substrate 56 are sequentially formed.
- the SOI layer 50 and the supporting substrate 56 are made of, for example, silicon and the insulating layer 54 is made of, for example, a silicon oxide film.
- the SOI layer 50 and the supporting substrate 56 are made of, for example, silicon and the insulating layer 54 is made of, for example, a silicon oxide film.
- the SIMOX method enables the thickness of the active layer (SOI layer) 52 to be the device active region to be determined and controlled by the acceleration voltage at the time of implanting oxygen ions.
- Force S, buried (B OX) Oxide film (insulating layer) 54 There are many problems such as the reliability of the active layer and the crystallinity of the active layer.
- an oxide film (insulating layer) 54 is formed on at least one of two single-crystal silicon mirror-surface wafers, bonded together without using an adhesive, and then subjected to a heat treatment (usually 1 hour). (100 ° C to 1200 ° C) to strengthen the bond.After that, one of the wafers is thinned by grinding or wet etching, and then the surface of the thin film is mirror-polished to form an SOI layer. Since the layer 52 is formed, there is an advantage that the reliability of the buried oxide film (insulating layer) 54 is high and the crystallinity of the SOI layer 52 is good. However, the S ⁇ I ⁇ wafer 50 bonded in this way is mechanically worked by grinding or polishing to make it thinner, so the thickness of the obtained 30 1 layer 52 is limited to its uniformity. There is.
- a method of manufacturing an SOI wafer a method of combining and separating ion-implanted wafers to produce an SOI wafer has recently been receiving attention.
- This method is also called ion implantation delamination method.
- two silicon wafers 52a and 56a are prepared (Fig. 8 (a), step 100).
- an oxide film (insulating layer) 54a is formed on one of the wafers 52a (called a bond wafer) (FIG. 8 (b), step 102), and the other silicon wafer 52a is formed.
- Hydrogen ions or rare gas ions are implanted from above (FIG. 8 (c), step 104) to form a microbubble layer (encapsulation layer) 58 inside the wafer.
- CMP polishing may be performed to remove the strain from the SII layer 52 or to make it thinner (FIG. 8 (g), step 112).
- polishing machines have been developed for the manufacture of such mirror-polished wafers and SOI wafers, but most of them have been improved by improving the polishing holding method (polishing head, and furthermore, the wafer holding board). Some of them have been improved with the one that holds the wafer on a soft holding surface such as a backing pad, the vacuum suction, and the template (retainer).
- a flexible thin ⁇ a suction holding plate disposed at the lower opening of the ⁇ a holding member suctions and supports the ⁇ a, and the ⁇ a holding member.
- the housing is suspended and supported by a stretchable tubular member and a highly flexible support member, and compressed air of a predetermined pressure is introduced into the closed chamber.
- a polishing work holding plate provided with a work holding plate main body having a large number of through holes for holding a work by vacuum suction is provided.
- a technique relating to a polishing head (a wafer holding method) in which a holding surface is covered with a film obtained by thermosetting a thermosetting resin applied to the holding surface, and the surface of the film is polished.
- Japanese Patent Application Laid-Open No. 2002-1133653 discloses a substrate holding apparatus for holding a semiconductor wafer to be polished and pressing it against a polishing surface on a polishing table.
- a top ring main body a retainer ring fixed to or integrally provided with the top ring main body and holding an outer peripheral edge of the semiconductor wafer, and provided within the top ring main body.
- a fluid chamber covered with an elastic film and supplied with a fluid.
- Japanese Patent Application Laid-Open No. 08-257,893 there is described in Japanese Patent Application Laid-Open No. Hei 11-1422 a polishing head which holds an outer peripheral portion of the wafer so that it can be elastically deformed in the thickness direction of the wafer.
- Japanese Patent Application Laid-Open No. 550/550 has a first space portion for pressing the carrier and a second space portion for pressing the retainer ring, and pressurized air is supplied to the first and second space portions to provide a central portion and an outer peripheral portion of the elastic sheet.
- this type of polishing machine 10 has a basic structure, a rotatable surface plate with a polishing cloth 12 attached to the upper surface. 14 and a pair of plates provided opposite to the surface plate 14 It has a polishing head 18 provided with a wafer holding plate 16 and a retainer ring 20 for holding an outer peripheral edge of the wafer W.
- a polishing agent supply pipe 22 is provided on a polishing cloth 12.
- a polishing apparatus having a structure without the retainer ring 20 is also conventionally used. It has been used since.
- a wafer having an SOI layer with excellent flatness can be manufactured by a method called ion implantation separation method shown in FIG. 8, but in order to make the SOI layer thinner, In some cases, polishing is performed, and conversely, the flatness of the SOI layer may be deteriorated (surface dripping).
- the present invention has been made in view of the above-mentioned problems of the related art, and provides a method and an apparatus for polishing wafers which can prevent surface sagging due to polishing and can manufacture wafers having high flatness, particularly SOI wafers. It is the purpose.
- a polishing method for wafers comprises: a rotatable platen having a polishing cloth adhered to an upper surface thereof; and a polishing machine provided with a wafer holding plate provided opposite to the platen.
- a polishing machine for holding the back surface of the wafer on the holding surface of the wafer holding plate and pressing the surface of the wafer against the polishing cloth for polishing, without changing the polishing apparatus.
- a polishing method comprising a polishing step of polishing the surface of the wafer until a total polishing allowance, wherein PT / JP2003 / 009658
- the process is divided into a plurality of divided polishing steps, and the wafer holding position in the subsequent divided polishing step is changed to a position different from the wafer holding position in the preceding divided polishing step. It is like that.
- the same polishing apparatus in other words, the same polishing head and the same wafer holding plate are used, and only the wafer holding position is changed to perform a kind of multi-stage polishing for re-polishing.
- variations in the holding surface of the wafer holding plate of the polishing head and distortion due to assembly can be reduced.
- the effect of the portion that cannot be mechanically improved due to the influence, in particular, the dripping and splash at the outer periphery of the wafer can be canceled out, and the wafer having a high flatness can be manufactured.
- the above-mentioned change of the wafer holding position is performed by rotating the wafer holding position by a predetermined rotation angle around the center of the wafer, for example, by removing the wafer from the wafer holding board, and removing the wafer from the wafer holding board. Alternatively, it may be performed by rotating both. In this way, in particular, the same position on the periphery of the wafer is not held again by the wafer holding plate. It is also possible to change the wafer holding position at any number of times and at any angle.However, the characteristics of the wafer shape obtained for each polishing head must be checked in advance and set appropriately according to the shape. preferable.
- the shape of the wafer tends to be in the shape of a clam.
- a part of the outer peripheral portion of the wafer W is sagged D, and the sagged D is similarly generated at the sagged D and the target position (a position rotated by 180 degrees).
- the part rotated 90 degrees there was a splash H, and the position of this splash H and the target were also the same.
- splash H refers to ⁇ a part of the outer periphery of the evaporator ⁇ a part that is slightly thicker than the For example, in FIG.
- the light-colored portion of the outer periphery of the wafer and the sag D are portions that are slightly thinner than the inside of the wafer at the outer periphery of the wafer, for example, FIG. ) (b) The dark portion of the outer periphery of the wafer in FIG.
- the wedge cycle of the outer peripheral portion of the aerial is set to an angle divided by the number n of divided steps in the multi-step divided polishing step. change.
- the period of the undulation at the outer periphery of the wafer is 180 ° in the case shown in FIG. 10
- (1) the change of the wafer holding position may be set to (1) 2 of the swell cycle of the outer periphery of the wafer.
- the number of divided polishing steps n in the divided polishing step is preferably an even number of two or more steps.
- the polishing allowance per one stage of the divided polishing step is set to a value obtained by dividing the total polishing allowance by the number n of the divided polishing stages.
- polishing head rotation speed and the polishing speed of the platen are used.
- the wafer itself may rotate. If the wafer itself rotates during polishing, variations in the holding surface of the polishing head will also be canceled out.
- the method of the present invention is a particularly effective method for polishing in which the back surface of the wafer is held and the front surface of the wafer is polished. Moreover, the method of the present invention can achieve a predetermined effect regardless of the type of the wafer holding plate and the holding method.
- the polishing apparatus used in the method of the present invention it is easy to perform a single wafer processing (a method in which one polishing head is held while holding one wafer). The same effect can be obtained by a polishing method in which a plurality of wafers are held on the head).
- the wafers are generally held in different polishing heads such as primary polishing, secondary polishing, and finish polishing, and are polished in multiple stages.
- the method of the present invention can be carried out on a polishing head used in any of such a plurality of steps. However, when such multi-stage polishing is performed, it is preferable to perform the polishing in the final polishing step.
- the secondary For example, from performing the polishing process 1 Even if it is affected by the polishing head of the secondary polishing machine, there is a high possibility that the shape of the specific part will not be deteriorated but equalized by using different polishing heads in the secondary polishing process. . However, in this case, the influence of the undulation of the polishing head of the secondary polishing apparatus remains. It is only necessary to remove such effects in the next step, but in some cases, it cannot be completely removed depending on the polishing allowance (amount of polishing). Therefore, taking into account the polishing allowance and the like in each step, it is appropriately set in which step the method of the present invention should be used.
- the method of the present invention is particularly effective when used in the production of SOI wafers, which have been receiving attention in recent years.
- reducing the thickness of the SOI layer has become an important issue.
- This thinning is performed by heat treatment or polishing.
- polishing when polishing is performed, how the wafer surface (SOI layer) originally processed to have high flatness can be polished thinly without breaking its shape. This process is important and is easily affected by the shape of the wafer holding part of the polishing head.
- a thin-film SOI wafer processed to a high flatness can be produced, which is particularly preferable.
- the polishing apparatus of the present invention includes a rotatable platen having a polishing cloth adhered to an upper surface thereof, and a polishing head provided opposite to the platen and provided with a wafer holding plate.
- the polishing apparatus is used in the polishing method of the present invention, and a mark is provided at a predetermined position of the polishing head. This is the marking.
- the polishing head should be marked so that the relative position between the predetermined position of the wafer (for example, a notch portion) and the predetermined position of the wafer holding plate of the polishing head can be confirmed. Side of ⁇ , part of the wafer holding plate, if you have a retainer ring, how part of the retainer ring, etc. It may be provided at a suitable position.
- the shape of the marking is arbitrary. If a polishing head having such a marking is used, the wafer holding position can be accurately changed.
- the polishing apparatus of the present invention is further provided with a wafer changing unit having a rotatable changing stage, which is transferred from the wafer holding plate to the changing stage when switching between a plurality of divided polishing steps, and holds the wafer. After the relative position between the repositioning stage and the wafer holding plate is rotated by a predetermined rotation angle, the wafer is returned from the repositioning stage to the wafer holding plate and held again, so that polishing can be performed again. Is preferred.
- the rotation of the relative position between the repositioning stage and the wafer holding plate is not limited to a mechanism for rotating the repositioning stage by a predetermined rotation angle.
- the polishing head side is also rotated by a predetermined rotation angle. It is also possible to use a mechanism that rotates both of them so that they have a predetermined rotation angle.
- the above-mentioned ⁇ as the wafer changing unit ⁇ includes a rotatable changing stage for detachably holding the wafer, a changing stage rotating mechanism for rotating the changing stage at a predetermined angle, and the polishing head. It is preferable to have a configuration having a polishing head moving mechanism for moving between the surface plate and the wafer changing unit.
- FIG. 1 is a schematic side view showing one embodiment of the polishing apparatus of the present invention.
- FIG. 2 is a graph showing the thickness distribution of the SOI layer on the outer periphery of the SOI wafer after polishing of the SOI wafer in Example 1.
- FIG. 3 is a graph showing the thickness distribution of the SOI layer in the diameter direction of the wafer after polishing the SOI wafer in Example 1.
- FIG. 4 is a rough graph showing the thickness distribution of the S ⁇ I layer on the outer periphery of the wafer after polishing of the SOI wafer in Comparative Example 1.
- FIG. 5 is a graph showing the thickness distribution of the SOI layer in the diameter direction of the wafer after polishing of the SII wafer in Comparative Example 1. '
- FIG. 6 is an explanatory top view showing an example of a method for evaluating the shape of wafers.
- FIGS. 7A and 7B are explanatory diagrams showing an example of the structure of the SOI wafer, wherein FIG. 7A is a top explanatory diagram and FIG. 7B is a sectional explanatory diagram.
- FIG. 8 is a flowchart showing a manufacturing procedure of the SOI wafer together with a schematic diagram.
- FIG. 9 is a schematic side view showing an example of a conventional polishing apparatus.
- FIG. 10 is an explanatory view showing an example of sagging and splash generated on the outer periphery of the polished wafer.
- (A) is a graph showing shading of the irregularities on the wafer surface
- (b) is a schematic diagram of (a).
- FIG. 1 is a schematic side view showing one embodiment of a polishing apparatus of the present invention used when carrying out the wafer polishing method of the present invention.
- 10a is a polishing apparatus of the present invention, and its basic structure is the same as that of the conventional polishing apparatus 10 shown in FIG.
- the same reference numerals are used for the same or similar members as in FIG.
- the polishing apparatus 10a includes a rotatable surface plate 14 having a polishing cloth 12 adhered to the upper surface thereof in the same manner as the polishing device 10 of FIG. 9, and a wafer provided opposite to the surface plate 14 Polishing head 18 with holding plate 16 and outer edge of wafer W And a retainer ring 20 for holding
- the wafer holding plate 16 has a through hole (not shown) for vacuum suction.
- reference numeral 28 denotes a rotating shaft of the platen 14
- reference numeral 30 denotes a driving shaft of the polishing head 18.
- the above-mentioned backing pad it can be held by synthetic resin, ceramics, an elastic body, or the like.
- a configuration without the above-mentioned retainer ring 20 can be employed, similarly to the case of the conventional polishing apparatus 10.
- the polishing method for wafers when performing a polishing step of performing polishing up to a predetermined polishing allowance without changing the polishing apparatus, that is, using the same polishing apparatus, at least before reaching the predetermined polishing allowance.
- the polishing is performed once by changing the wafer holding position.
- the polishing process is divided into a plurality of divided polishing processes, and the wafer holding position in the subsequent divided polishing process is changed to the preceding stage.
- the position is changed to a position different from the wafer holding position in the division polishing step.
- a mark 32 is made as a mark on a part of the wafer holding plate 16 of the polishing head 18 and a specific position of the wafer is mechanically or manually, for example, Hold the notch N (Fig. 6) by aligning it with that position. Based on the position of this marking 32, adjust the wafer holding position in the second and subsequent divided polishing steps.
- reference numeral 34 denotes an e-chamber change unit, and the above polishing apparatus 10 It is provided adjacent to a.
- the wafer transfer unit 34 has a transfer stage 36 for detachably holding the wafer W on its upper surface.
- the repositioning stage 36 is rotated by a repositioning stage rotation mechanism 40 via a shaft 38.
- reference numeral 42 denotes a polishing head moving mechanism, which moves the polishing head 18 between the surface plate 14 and the e-available unit 34.
- the above-mentioned e-wafer holding position can be automatically changed. For example, after the first stage of the division polishing, the polishing head 18 holding the wafer W is moved to the wafer changing unit 34, and the polishing head 18 and the wafer holding are maintained. With the position of the panel 16 fixed, deliver the wafer W onto the stage 36 of the e-ha reunit 34 and re-rotate the stage 36 at a fixed angle, and then turn it back to the polishing head 18 again. By holding again, the polishing head 18 can be moved onto the surface plate 14 to repeat the division polishing.
- the re-scaling stage 36 is operated so that the position of the e-wafer W can be suctioned without shifting. It is necessary to operate to rotate 36 exactly at an arbitrary angle.
- the configuration of the wafer reloading unit 34 is not particularly limited as long as the relative holding position of the wafer holding plate 16 and the wafer W can be accurately controlled. Various configurations can also be adopted for this.
- a mechanism that rotates the head 18 side by a predetermined rotation angle may be used, and both can be rotated to a predetermined rotation angle. 5 Example
- a plurality of wafers manufactured by the ion implantation delamination method were prepared as S O I wafers to be polished.
- the SOI wafer has a diameter of 300 mm, the supporting substrate is about 775 ⁇ m, the thickness of the oxide layer is about 145 nm, and the thickness of the SOI layer is about 340 nm.
- the case where the raw material is polished with a total polishing allowance of about 90 nm for the SOI layer will be described.
- the above SOI wafer was polished using F_R EX 300, Ebara Corporation.
- the polishing cloth used is a suede type polishing cloth of Ciegal7355fm (lattice groove 20 mm opening) manufactured by Toray Cortex Co., Ltd., and G390R RS manufactured by Fujimin Corporation as an abrasive. Was used.
- the polishing pressure is 240 g / cm 2 .
- the polishing allowance in the first-stage divided polishing was set to about 45 nm, and the divided polishing was performed.
- the e-holding position in the second-stage split polishing was 90 degrees from the e-holding position in the first-stage split polishing by 90 degrees around the center of the e-wafer. Moved.
- FIGS. 2 and 3 were obtained as the shape of the wafer after polishing.
- Figure 2 shows the values obtained by evaluating the thickness of the SOI layer at the outer periphery of the wafer (at a position of 5 mm around the periphery) at 4 ° intervals (0 ° at the notch) by ACUMAP II manufactured by ADE as shown in Fig. 6. is there.
- N indicates the notch portion of the wafer W
- A indicates the scanning direction for evaluating the outer circumferential waviness
- B indicates the scanning direction for evaluating the radial direction.
- Fig. 3 similarly shows the dia wafer thickness in the diameter direction measured at 4 mm intervals.
- the SOI I wafer to be polished was the same as that in Example 1 except that the SOI layer had a thickness of about 280 nm.
- the S O I wafer was polished under the same conditions as in Example 1.
- the wafer held on the polishing head polished the polishing target of about 90 nm in one polishing without changing its position.
- Figs. 4 and 5 were obtained for the wafer shape. These are values evaluated in the same manner as in Example 1. Fig. 4 shows the thickness distribution of the outer periphery of the wafer after polishing, and Fig. 5 shows the measurement of the diameter in the diameter direction of the wafer after polishing.
- the polishing head holding surface of the wafer holding plate is It was found that the effects of the parts that could not be mechanically improved due to the effects of variations and assembly-induced distortion were negated, and that a wafer with high flatness could be polished.
- the present invention is not limited to the above embodiment.
- the above embodiment is an example, and any embodiment having substantially the same configuration as the technical idea described in the claims of the present invention and exerting the same function and effect will be described.
- the number of stages of the wafer divided polishing step in the method of the present invention is not limited to two, and may be further increased. Further, the method of the present invention can be carried out using any type of polishing apparatus. Industrial applicability
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Mechanical Treatment Of Semiconductor (AREA)
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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EP03784489A EP1542267B1 (en) | 2002-08-09 | 2003-07-30 | Method and apparatus for polishing wafer |
US10/523,976 US7291055B2 (en) | 2002-08-09 | 2003-07-30 | Wafer polishing method and apparatus |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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JP2002232693A JP3978780B2 (ja) | 2002-08-09 | 2002-08-09 | ウエーハの研磨方法及び装置 |
JP2002-232693 | 2002-08-09 |
Publications (1)
Publication Number | Publication Date |
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WO2004015752A1 true WO2004015752A1 (ja) | 2004-02-19 |
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ID=31711843
Family Applications (1)
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PCT/JP2003/009658 WO2004015752A1 (ja) | 2002-08-09 | 2003-07-30 | ウェーハの研磨方法及び装置 |
Country Status (4)
Country | Link |
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US (1) | US7291055B2 (ja) |
EP (1) | EP1542267B1 (ja) |
JP (1) | JP3978780B2 (ja) |
WO (1) | WO2004015752A1 (ja) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
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KR100743821B1 (ko) * | 2003-02-25 | 2007-07-30 | 가부시키가이샤 섬코 | 실리콘 단결정 육성 방법, 실리콘 웨이퍼 제조 방법 및 soi 기판 제조 방법 |
US7312154B2 (en) * | 2005-12-20 | 2007-12-25 | Corning Incorporated | Method of polishing a semiconductor-on-insulator structure |
JP4862896B2 (ja) * | 2007-01-31 | 2012-01-25 | 信越半導体株式会社 | シリコンウエーハの面取り装置およびシリコンウエーハの製造方法ならびにエッチドシリコンウエーハ |
JP5929662B2 (ja) * | 2012-09-21 | 2016-06-08 | 信越半導体株式会社 | 研磨装置及びsoiウェーハの研磨方法 |
JP6056318B2 (ja) * | 2012-09-21 | 2017-01-11 | 信越半導体株式会社 | Soiウェーハの研磨方法 |
JP6421640B2 (ja) * | 2015-02-25 | 2018-11-14 | 株式会社Sumco | 半導体ウェーハの枚葉式片面研磨方法および半導体ウェーハの枚葉式片面研磨装置 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11188619A (ja) | 1997-12-25 | 1999-07-13 | Fujikoshi Mach Corp | ウェーハの研磨方法 |
WO1999041022A1 (en) | 1998-02-14 | 1999-08-19 | Strasbaugh | Accurate positioning of a wafer |
JP2000094316A (ja) * | 1998-09-18 | 2000-04-04 | Sony Corp | 平坦化研磨装置 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US2875769A (en) * | 1957-08-20 | 1959-03-03 | Apod Corp | Keratinaceous fiber dye of hydroquinone and either dihydroxyphenylalanine or dihydroxyphenylglycine and method of its use |
US4373991A (en) * | 1982-01-28 | 1983-02-15 | Western Electric Company, Inc. | Methods and apparatus for polishing a semiconductor wafer |
US4662811A (en) * | 1983-07-25 | 1987-05-05 | Hayden Thomas J | Method and apparatus for orienting semiconductor wafers |
EP0599299B1 (en) * | 1992-11-27 | 1998-02-04 | Kabushiki Kaisha Toshiba | Method and apparatus for polishing a workpiece |
US5762539A (en) * | 1996-02-27 | 1998-06-09 | Ebara Corporation | Apparatus for and method for polishing workpiece |
US5738568A (en) * | 1996-10-04 | 1998-04-14 | International Business Machines Corporation | Flexible tilted wafer carrier |
US6244946B1 (en) * | 1997-04-08 | 2001-06-12 | Lam Research Corporation | Polishing head with removable subcarrier |
JP4054119B2 (ja) * | 1998-09-11 | 2008-02-27 | 不二越機械工業株式会社 | ウェーハの貼付装置 |
US6367529B1 (en) * | 1998-05-01 | 2002-04-09 | Fujikoshi Kikai Kogyo Kabushiki Kaisha | Method of adhering wafers and wafer adhering device |
JP3995796B2 (ja) * | 1998-05-01 | 2007-10-24 | 不二越機械工業株式会社 | ウェーハの貼付方法及びその装置 |
JP2001036054A (ja) * | 1999-07-19 | 2001-02-09 | Mitsubishi Electric Corp | Soi基板の製造方法 |
US20010029155A1 (en) * | 2000-01-31 | 2001-10-11 | Applied Materials, Inc. | Multi-step conditioning process |
US6623329B1 (en) * | 2000-08-31 | 2003-09-23 | Micron Technology, Inc. | Method and apparatus for supporting a microelectronic substrate relative to a planarization pad |
-
2002
- 2002-08-09 JP JP2002232693A patent/JP3978780B2/ja not_active Expired - Fee Related
-
2003
- 2003-07-30 US US10/523,976 patent/US7291055B2/en not_active Expired - Lifetime
- 2003-07-30 EP EP03784489A patent/EP1542267B1/en not_active Expired - Lifetime
- 2003-07-30 WO PCT/JP2003/009658 patent/WO2004015752A1/ja active Application Filing
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11188619A (ja) | 1997-12-25 | 1999-07-13 | Fujikoshi Mach Corp | ウェーハの研磨方法 |
WO1999041022A1 (en) | 1998-02-14 | 1999-08-19 | Strasbaugh | Accurate positioning of a wafer |
JP2000094316A (ja) * | 1998-09-18 | 2000-04-04 | Sony Corp | 平坦化研磨装置 |
Non-Patent Citations (1)
Title |
---|
See also references of EP1542267A4 * |
Also Published As
Publication number | Publication date |
---|---|
JP2004072025A (ja) | 2004-03-04 |
EP1542267A1 (en) | 2005-06-15 |
EP1542267A4 (en) | 2008-10-15 |
US7291055B2 (en) | 2007-11-06 |
EP1542267B1 (en) | 2011-07-06 |
US20060068681A1 (en) | 2006-03-30 |
JP3978780B2 (ja) | 2007-09-19 |
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