WO2004008542A1 - Transistor haute frequence bipolaire et son procede de production - Google Patents

Transistor haute frequence bipolaire et son procede de production Download PDF

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Publication number
WO2004008542A1
WO2004008542A1 PCT/EP2003/006790 EP0306790W WO2004008542A1 WO 2004008542 A1 WO2004008542 A1 WO 2004008542A1 EP 0306790 W EP0306790 W EP 0306790W WO 2004008542 A1 WO2004008542 A1 WO 2004008542A1
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WO
WIPO (PCT)
Prior art keywords
collector
frequency transistor
bipolar high
zone
layer
Prior art date
Application number
PCT/EP2003/006790
Other languages
German (de)
English (en)
Inventor
Klaus Gnannt
Jakob Huber
Original Assignee
Infineon Technologies Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag filed Critical Infineon Technologies Ag
Publication of WO2004008542A1 publication Critical patent/WO2004008542A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/737—Hetero-junction transistors
    • H01L29/7371—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0821—Collector regions of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/732—Vertical transistors

Definitions

  • the present invention relates to a bipolar high-frequency transistor having a substrate, a semiconducting collector layer, a base layer and at least one emitter region, and a method for producing the same.
  • Such a high-frequency transistor is for example from DE 1951151 and from. von Münch, "Introduction to semiconductor technology", Teubner-Verlag, Stuttgart 1993, pages 208 and 209.
  • Typical structures and dimensions of the doping profiles are on the order of a few ⁇ m. Thick collector structures lead to a high collector-emitter blocking voltage UCEO, a low cut-off frequency F ⁇ and a low collector base capacitance C ⁇ g. The following relationship applies to the high-frequency gain G m :
  • the invention is based on the knowledge that the collector-base capacitance is composed of the capacitance of an active collector zone under the emitter fingers and the capacitance of a parasitic passive collector zone between the individual emitter fingers.
  • the overall collector base capacity can be reduced by making the passive collector zone thicker than the active collector zone.
  • the semiconducting intermediate layer adjoins the collector layer. This makes the semiconducting intermediate layer part of the collector.
  • the collector which is therefore thicker, has a reduced collector-base capacity.
  • the semiconducting intermediate layer is arranged between the substrate and the collector layer. This brings significant manufacturing advantages and an increase in the performance of the bipolar high-frequency transistor. " Typically, the first zone of the semi-conductive intermediate layer adjoins the second zone of the semi-conductive intermediate layer. This creates an intermediate layer with alternating first zones and second zones.
  • An embodiment of the arrangement according to the invention is when the first zone of the semiconducting intermediate layer has a different dopant concentration than the second zone of the semiconducting intermediate layer.
  • the first zone in the semiconducting intermediate layer has a different charge carrier concentration than the second zone of the semiconducting intermediate layer. This results in a different contribution of the two zones to the collector base capacity.
  • a preferred development of the arrangement according to the invention is when the first zone of the semiconducting intermediate layer has a higher dopant concentration than the second zone of the semiconducting intermediate layer.
  • the charge carrier concentration in the second zone of the semiconducting intermediate layer is lower than the charge carrier concentration in the first zone of the semiconducting intermediate layer. The contribution of the second zone to the collector base capacity is therefore less.
  • the first zone of the semiconducting intermediate layer and the part of the collector layer adjoining it form an active collector zone and the second zone of the semiconducting intermediate layer and the part of the collector layer adjoining it forms a passive collector zone.
  • the collector base capacity can thus be influenced by the passive collector zone.
  • the active collector zone typically lies opposite the emitter on the base layer and thus forms a desired inner transistor.
  • a further advantageous development of the arrangement according to the invention is when the substrate is a semiconductor substrate. This brings considerable manufacturing advantages.
  • a buried layer is introduced into the substrate.
  • This buried layer enables the arrangement according to the invention to be integrated into an integrated circuit because the collector can be led out electrically to the surface with the aid of the buried layer and a collector connection region.
  • a further embodiment of the arrangement according to the invention provides that a collector connection area is introduced in the collector layer. This allows the collector to be brought out electrically to the surface.
  • An alternative development of the manufacturing method according to the invention is when the semiconductor substrate is of a first conductivity type with a first dopant concentration. As a result, the substrate is part of the collector and the collector connection can be made via the substrate on the back of the substrate. This brings considerable manufacturing advantages and the performance of the bipolar high-frequency transistor is increased.
  • a further alternative embodiment of the production method according to the invention is when a buried layer of a first conductivity type with a first dopant concentration is introduced into the semiconductor substrate of a second conductivity type.
  • the buried layer is therefore part of the collector and can be contacted via a collector connection region to the surface of the bipolar high-frequency transistor.
  • the bipolar high-frequency transistor is therefore suitable for production in integrated circuits.
  • the first dopant concentration is higher than the second dopant concentration.
  • the charge carrier concentration in the substrate is higher than the charge carrier concentration in the semiconducting intermediate layer. The substrate can thus be used as an electrical connection for the actual collector.
  • the second dopant concentration is lower than the third dopant concentration.
  • charge carrier concentration in the semiconducting intermediate layer is lower than the charge carrier concentration in the introduced first zones. The contribution of the semiconducting intermediate layer to the collector base capacitance is thus less than the contribution of the introduced first zones to the collector base capacitance.
  • the first dopant concentration is approximately equal to the third dopant concentration.
  • the zones introduced in the semiconducting intermediate layer have roughly the same physical properties as the substrate and serve as an electrical connection for the active collector.
  • the second dopant concentration is lower than the fourth dopant concentration.
  • the semiconducting intermediate layer has a lower charge carrier concentration than the collector layer and thus reduces the total collector-base capacity.
  • the third dopant concentration higher than the fourth dopant concentration is higher than the charge carrier concentration of the collector layer.
  • the introduced first zones thus serve as electrical connections to the collector layer.
  • An alternative embodiment of the production method according to the invention is when the semiconducting intermediate layer and the collector layer are applied epitaxially. As a result, the semiconducting intermediate layer and the collector layer are grown with as few crystal defects as possible, which is very important for the functional properties of the transistor.
  • the emitter zone is generated over at least one zone in the semiconducting intermediate layer. This creates a desired inner bipolar transistor.
  • Figure 1 is a schematic cross-sectional view of a conventional bipolar radio frequency transistor.
  • FIG. 2 shows a schematic cross-sectional view of a preferred exemplary embodiment of the bipolar high-frequency transistor according to the invention.
  • FIG. 3 shows measurement results of the amplification of a preferred exemplary embodiment of the high-frequency transistor according to the invention in comparison to conventional bipolar high-frequency transistors as a function of the collector-base capacitance.
  • the bipolar high-frequency transistor shown in FIG. 1 comprises a highly doped substrate 1 made of an n-material.
  • a lightly doped epitaxial layer 3 has been grown on the substrate 1.
  • the substrate 1 forms a so-called “sub-collector”, which is electrically contacted from the rear to the outside by a contact 2.
  • the epitaxial layer 3, which also consists of an n-material, forms the active collector with a collector width W c .
  • a base region 4 made of a p-type material is formed in the epitaxial layer 3.
  • a plurality of base connections 5 are assigned to the base region 4.
  • a plurality of emitter regions 6, which are produced from an n-material, are also arranged in the base region 4.
  • the emitter regions 6 are formed entirely in the base region 4 and spaced apart from the base connections 5.
  • An npn transistor is formed by each individual emitter region 6, the base region 4 and the collector.
  • the epitaxial layer 3, the base region 4, the base connections 5 and the emitter regions 6 are covered by an oxide layer 7.
  • the oxide layer 7 is structured such that the base connections 5 are connected to the base contacts 8 via contact openings.
  • the oxide layer 7 is likewise structured in such a way that the emitter regions 6 are connected to emitter contacts 9 via contact openings.
  • the preferred exemplary embodiment of a bipolar high-frequency transistor according to the invention in FIG. 2 has a highly doped substrate 10 made of n-material. Typical values of the n-
  • Doping in the substrate 10 are n> 1 ⁇ lO cm ⁇ 3.
  • On this substrate 10 is a very lightly doped, about 0.5 micron thick semi-conductive intermediate layer is applied from n-type material 12th
  • This semiconducting intermediate layer 12 is typically applied epitaxially and has n-doping values of approximately 10 1 ⁇ cm-3.
  • First zones 13 are introduced in this semiconducting intermediate layer 12. These first zones 13 are with Implanted locally into the semiconducting intermediate layer 12 with the aid of conventional photographic technology. These local implantations are with n-dopants such.
  • the semiconducting intermediate layer 12 is healed.
  • the regions between the first zones 13 in the semiconducting intermediate layer 12 form the second zones 23.
  • the preferred exemplary embodiment in FIG. 2 shows a collector layer 14 made of n-material on the semiconducting intermediate layer 12 and the zones 13 introduced therein.
  • This collector layer 14 typically becomes Epitaxially applied 1 to 2 ⁇ m thick, and has a dopant concentration of 1 x 10 ⁇ cm ⁇ 3 to 50 x 10 ⁇ 6 cm ⁇ 3. The concentration is selected according to the properties required for U CEO and F t .
  • a base layer 15 made of p-material is introduced into the collector layer 14. This base layer 15 is introduced after oxidation of the collector layer surface with subsequent trough etching. The base layer 15 is implanted with n-dopants and then healed.
  • the emitter regions 18 in FIG. 2 are completely introduced into the base layer 15.
  • the base connections 19 are likewise completely introduced into the base layer 15.
  • the emitter regions 18 are expediently introduced by implantation of n-dopants, while the base connections 19 are carried out by implantation of p-dopants.
  • the emitter regions 18 as well as the base connections 19 are implanted through contact openings 17. These contact openings 17 are produced by structuring the dielectric layer 16 deposited on the surface. After the implantation of the emitter regions 18 and the base connections 19, a healing step takes place.
  • the contour connections 20 for the emitter regions 18 and for the base connections 19 in FIG. 3 are produced by structuring a metallization level.
  • FIG. 2 An exemplary active collector zone within the bipolar high-frequency transistor is identified in FIG. 2 by the collector width W c .
  • the bipolar high-frequency transistor V50 according to the invention has a lower collector-base capacity than conventional bipolar high-frequency transistors ET2023 and LS2059 with different collector thicknesses.
  • the gain Gms calculated from the S parameter measurement at the slice level with a measuring frequency of 0.5 Ghz, is significantly improved in the V50 compared to the conventional bipolar high-frequency transistors ET2023 and LS2059.
  • the present invention is not limited to the exemplary embodiment described with reference to FIG. 2.
  • an example was described in FIG. 2 using an npn transistor, it is obvious that the bipolar high-frequency transistor according to the invention would also be used for pnp transistors. It is also obvious that the bipolar high-frequency transistor according to the invention can also be applied to a transistor construction in which the sub-collector consists of a buried layer and the collector connection is pulled out upwards. The invention is also applicable to a double poly transistor.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bipolar Transistors (AREA)

Abstract

L'invention concerne un transistor haute fréquence bipolaire et son procédé de production. Ce transistor haute fréquence bipolaire comprend un substrat (10), une couche intermédiaire semi-conductrice (12), une couche collecteur (14), une couche de base (15) et au moins une zone émetteur (18). La couche intermédiaire semi-conductrice (12) est divisée en au moins une première zone (13) et au moins une deuxième zone (23).
PCT/EP2003/006790 2002-07-16 2003-06-26 Transistor haute frequence bipolaire et son procede de production WO2004008542A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10232176.0 2002-07-16
DE2002132176 DE10232176A1 (de) 2002-07-16 2002-07-16 Bipolarer Hochfrequenztransistor und Verfahren zur Herstellung desselben

Publications (1)

Publication Number Publication Date
WO2004008542A1 true WO2004008542A1 (fr) 2004-01-22

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Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4082571A (en) * 1975-02-20 1978-04-04 Siemens Aktiengesellschaft Process for suppressing parasitic components utilizing ion implantation prior to epitaxial deposition
DE2805008A1 (de) * 1978-02-06 1979-08-09 Siemens Ag Hochfrequenztransistor
US4725874A (en) * 1979-03-26 1988-02-16 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having protected edges
JPH02159726A (ja) * 1988-12-14 1990-06-19 Sony Corp バイポーラトランジスタの製造方法
JPH0499329A (ja) * 1990-08-18 1992-03-31 Nec Corp 半導体装置の製造方法
EP0481202A1 (fr) * 1990-10-15 1992-04-22 Hewlett-Packard Company Structure de transistor à capacité collecteur-substrat réduite
JPH0521444A (ja) * 1991-07-15 1993-01-29 Fujitsu Ltd バイポーラトランジスタの構造及び製造方法
EP0666600A2 (fr) * 1994-02-02 1995-08-09 ROHM Co., Ltd. Transistor bipolaire de puissance
JP2000195965A (ja) * 1998-12-24 2000-07-14 Sony Corp 半導体装置およびその製造方法

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4082571A (en) * 1975-02-20 1978-04-04 Siemens Aktiengesellschaft Process for suppressing parasitic components utilizing ion implantation prior to epitaxial deposition
DE2805008A1 (de) * 1978-02-06 1979-08-09 Siemens Ag Hochfrequenztransistor
US4725874A (en) * 1979-03-26 1988-02-16 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having protected edges
JPH02159726A (ja) * 1988-12-14 1990-06-19 Sony Corp バイポーラトランジスタの製造方法
JPH0499329A (ja) * 1990-08-18 1992-03-31 Nec Corp 半導体装置の製造方法
EP0481202A1 (fr) * 1990-10-15 1992-04-22 Hewlett-Packard Company Structure de transistor à capacité collecteur-substrat réduite
JPH0521444A (ja) * 1991-07-15 1993-01-29 Fujitsu Ltd バイポーラトランジスタの構造及び製造方法
EP0666600A2 (fr) * 1994-02-02 1995-08-09 ROHM Co., Ltd. Transistor bipolaire de puissance
JP2000195965A (ja) * 1998-12-24 2000-07-14 Sony Corp 半導体装置およびその製造方法

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 014, no. 414 (E - 0975) 7 September 1990 (1990-09-07) *
PATENT ABSTRACTS OF JAPAN vol. 016, no. 332 (E - 1236) 20 July 1992 (1992-07-20) *
PATENT ABSTRACTS OF JAPAN vol. 017, no. 292 (E - 1376) 4 June 1993 (1993-06-04) *
PATENT ABSTRACTS OF JAPAN vol. 2000, no. 10 17 November 2000 (2000-11-17) *

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DE10232176A1 (de) 2004-02-05

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