WO2004003742A1 - 情報処理装置および方法、記録媒体、並びにプログラム - Google Patents
情報処理装置および方法、記録媒体、並びにプログラム Download PDFInfo
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- WO2004003742A1 WO2004003742A1 PCT/JP2003/008186 JP0308186W WO2004003742A1 WO 2004003742 A1 WO2004003742 A1 WO 2004003742A1 JP 0308186 W JP0308186 W JP 0308186W WO 2004003742 A1 WO2004003742 A1 WO 2004003742A1
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/60—Software deployment
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/40—Transformation of program code
- G06F8/54—Link editing before load time
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/60—Software deployment
- G06F8/65—Updates
- G06F8/654—Updates using techniques specially adapted for alterable solid state memories, e.g. for EEPROM or flash memories
Definitions
- the present invention relates to an information processing apparatus and method, a recording medium, and a program.
- a program is easily and continuously stored in a plurality of storage sections controlled by different CPUs. and was so that can be written, the information processing apparatus and method, recording medium, and c a program
- the new program or data can be recorded on a flash memory card by controlling the CPU of the video display device.
- the data is read from a medium or the like and stored (installed / restored) at a predetermined address position in a storage unit such as a RAM controlled by the CPU.
- the present invention has been made in view of such a situation, and in an information processing apparatus having a plurality of CPUs and storage units, a program can be easily stored in a plurality of storage units controlled by different CPUs. , To enable continuous writing.
- An information processing apparatus includes: a first acquisition unit that acquires an instruction regarding storage of software supplied from a main control unit; a request unit that requests software from the main control unit; Second acquisition means for acquiring the software supplied in accordance with the condition, and storage control means for controlling the storage unit and storing the software acquired by the second acquisition means. .
- the instruction may include information on software and information on a storage unit that stores the software.
- a storage unit setting unit that selects a storage unit specified by the instruction obtained by the first obtaining unit from the plurality of storage units and sets the storage unit to store the software obtained by the obtaining unit.
- the storage control means can cause the storage unit set by the storage unit setting means to store software.
- the software stored in the storage unit under the control of the storage control unit is normal. It is possible to further comprise a checking means for checking whether or not this is the case, and a supply means for supplying the result of checking by the checking means to the main control unit.
- the main control unit determines that the storage processing of the software in the storage unit is normally completed based on the confirmation result supplied by the supply unit, the main control unit controls the display unit, and the storage processing is completed normally. Information indicating that the operation has been performed can be displayed on the display unit.
- the main control unit when determining based on the confirmation result supplied by the supply unit that the storage process of the software in the storage unit is not completed normally, controls the display unit, and an error occurs in the storage process. Information indicating that the event has occurred can be displayed on the display unit.
- the storage medium in which the software is stored is a removable memory card, and the main control unit updates the program or data stored in the plurality of storage units using the program or data obtained from the memory card You can do so.
- the storage control unit compares the software purge information acquired by the second acquisition unit with the software version information stored in the storage unit. It is possible to control and store the software acquired by the second acquisition means.
- An information processing method includes a request step of requesting software from a main control unit, an acquisition control step of controlling acquisition of software supplied in response to a request in the processing of the request step, And a storage control step of controlling the storage unit based on the instruction, and storing software whose acquisition has been controlled by the processing of the acquisition control step.
- the program of the recording medium includes: a request step for requesting software from the main control unit; an acquisition control step for controlling acquisition of software supplied in response to a request in the processing of the request step;
- the storage unit is controlled based on the instruction supplied from the storage unit, and the software whose acquisition is controlled by the processing of the acquisition control step is executed.
- a storage control step of storing is
- a program according to the present invention includes a request step for requesting software from the main control unit, an acquisition control step for controlling acquisition of software supplied in response to a request in the processing of the request step, and a program supplied from the main control unit. And a storage control step of controlling the storage unit based on the instruction and storing the software whose acquisition has been controlled by the processing of the acquisition control step.
- an instruction regarding storage of software supplied from the main control unit is obtained, and the software supplied in response to a request to the main control unit is obtained.
- the obtained software is stored in the storage unit.
- the information processing device may be a digital camera having a plurality of control units and a storage unit, a mobile phone, a television receiver, or a microcomputer incorporated in other devices.
- FIG. 1 is a block diagram showing a configuration example of an image display device to which the present invention is applied.
- FIG. 2 is a diagram showing a configuration example of a storage area of the first flash ROM of FIG.
- FIG. 3 is a diagram showing a detailed configuration example of the ID information area of FIG.
- FIG. 4 is a diagram illustrating a configuration example of a storage area of a semiconductor memory.
- FIG. 5 is a diagram showing an example of the relationship between programs stored in the storage area of the first flash ROM in FIG.
- FIG. 6 is a flowchart illustrating the startup processing by the first CPU in FIG.
- FIG. 7 is a flowchart illustrating details of the ID information confirmation processing executed in step S3 of FIG.
- FIG. 8 is a flowchart illustrating the upgrade processing by the first CPU in FIG.
- FIG. 9 is a flowchart following FIG. 8 for explaining the upgrade processing by the first CPU in FIG.
- FIG. 10 is a diagram showing an example of a GUI screen for mounting.
- FIG. 11 is a diagram showing an example of the GUI screen for when not mounted.
- FIG. 12 is a diagram showing an example of the GUI screen for completion.
- FIG. 13 is a diagram illustrating an example of an error GUI screen.
- FIG. 14 is a flowchart illustrating the details of the rewriting process performed in step S63 of FIG.
- FIG. 15 is a flowchart following FIG. 14 for explaining the details of the rewriting process executed in step S63 of FIG.
- FIG. 16 is a flowchart for explaining the write processing by the second CPU in FIG.
- FIG. 17 is a flowchart illustrating a user program execution process by the first CPU in FIG.
- FIG. 18 is a diagram showing an example of a screen displayed on the display unit in FIG.
- FIG. 19 is a block diagram illustrating a configuration example of a personal computer to which the present invention has been applied.
- FIG. 20 is a diagram illustrating an example of an information processing system to which the present invention has been applied.
- FIG. 1 is a diagram showing a configuration example of an image display device to which the present invention is applied.
- the image display device 1 that displays moving images and still images, such as JPEG (Joint Photographic Experts Group), etc., is input from an input terminal or is connected to an electrical device such as a flash memory. It processes image data such as JPEG image data stored in the semiconductor memory 2 which is composed of a non-volatile memory that can be rewritten in a personal computer, and displays a still image or a moving image on a display or the like.
- JPEG Joint Photographic Experts Group
- the first CPU (Central Processing Unit) 11 of the image display device 1 is a semiconductor memo
- the image data obtained through the memory card interface 22 from the memory 2 is subjected to image processing such as decoding, and the processed image data is supplied to the graphic controller 23.
- the first CPU 11 controls each unit connected via the bus. Further, the first CPU 11 generates GUI (Graphical User Interface) information and supplies it to the graphic controller 23.
- GUI Graphic User Interface
- the first CPU 11 is connected to the second CPU 31 via the communication bus 15 and the control bus 16 and exchanges control information and various data.
- the first CPU 11 includes a program stored in a first flash ROM (Read Only Memory) 12 connected via a bus and a first EEPR0M (Electronically Erasable and Programmable (Read Only Memory) 14 is loaded into SDRAM (Synchronous Dynamic Random Access Memory) 13 which is also connected via a bus, and image processing and various parts are performed using those programs and data. And the like.
- a program stored in a first flash ROM (Read Only Memory) 12 connected via a bus
- a first EEPR0M Electrically Erasable and Programmable (Read Only Memory) 14 is loaded into SDRAM (Synchronous Dynamic Random Access Memory) 13 which is also connected via a bus, and image processing and various parts are performed using those programs and data. And the like.
- the first CPU 11 is stored in the first flash R0M12 and the first EEPR0M 14 using a program or data obtained from the semiconductor memory 2 via the memory card interface 22 as described later. Program and data can be updated.
- the first flash R0M12 is an electrically rewritable non-volatile memory, and stores a program executed in the first CPU 11.
- the SDRAM 13 is controlled by the first CPU 11 and temporarily stores the program stored in the supplied first flash ROM 12 and the data stored in the first EEPR0M14.
- the first EEPR0M14 is an electrically rewritable nonvolatile memory, and stores data such as correction values required for image processing by the first CPU 11. Further, the image display device 1 is provided with a memory card slot 21 in which a semiconductor memory 2 can be mounted. Semiconductor correctly installed in memory card slot 21 PT / JP2003 / 008186
- the memory 2 is electrically connected to the memory card interface 22 and is controlled by the memory card interface 22.
- the memory card interface 22 is controlled by the first CPU 11 and monitors the memory card slot 21 to check whether the semiconductor memory 2 is correctly mounted in the memory card slot 21. It reads data stored in the semiconductor memory 2 properly inserted in the memory card slot 21 and supplies the data to the first CPU 11.
- the graphic controller 23 generates image data corresponding to the image displayed on the display unit 26 using the image data and the GUI information supplied from the first CPU 11 and supplies the image data to the scaling device 24.
- the scaling device 24 is controlled by the second CPU 31 and is supplied with image data supplied from the graphic controller 23 or supplied from outside the image display device 1 via the external image signal input terminal 27.
- the image data is subjected to a resolution conversion process or the like, to generate image data that can be displayed on the display unit 26, and supplied to the display device controller 25.
- the display device controller 25 supplies the image data supplied from the scaling device 24 to the display unit 26, and controls the display unit 26 to display an image corresponding to the supplied image data.
- the display unit 26 includes a display such as an LCD (Liquid Crystal Display) or a CRT (Cathode Ray Tube), is controlled by the display device controller 25, and displays an image corresponding to the supplied image data.
- a display such as an LCD (Liquid Crystal Display) or a CRT (Cathode Ray Tube)
- LCD Liquid Crystal Display
- CRT Cathode Ray Tube
- the second CPU 31 performs scaling by using a program stored in the second flash ROM 32 and data related to image processing such as brightness and color stored in the second EEPR0M 34. Controls device 24 to control image display.
- the second CPU 31 executes various processes based on a user instruction input from the input unit 33. Further, the second CPU 31 has a built-in ROM (not shown) and stores a boot-only program. As described later, the second CPU 31 can update the information stored in the second flash R0M32 or the second EEPR0M34 by executing the startup-only program.
- the second flash R0M32 like the first flash ROM 12, is an electrically rewritable non-volatile memory, and stores a program executed in the second CPU 31.
- the input unit 33 includes a channel button, a menu operation button, and the like (not shown).
- the input unit 33 is operated by a user, inputs an instruction from the user, and supplies the instruction to the second CPU 31.
- the second EEPR0M34 like the first EEPR0M14, is an electrically rewritable nonvolatile memory, and stores data necessary for image processing by the second CPU 31.
- the semiconductor memory 2 is a memory card composed of an electrically rewritable non-volatile memory such as a flash memory typified by, for example, a Memory Stick (trademark).
- the semiconductor memory 2 in addition to the JPEG image data for displaying the corresponding image on the display unit 26 of the image display device 1, a program stored in the first flash R0M12 and the second flash ROM 32, and Data and the like stored in the first EEPR0M 14 and the second EEPR0M 34 are recorded.
- the first CPU 11 acquires these programs and data as described later, and Write to 1 Flash R0M1 2 or 1st EEPR0M14.
- the semiconductor memory 2 stores programs and data recorded in the second flash R0M32 and the second EEPR0M34
- the first CPU 11 supplies those programs and data to the second CPU 31 as described later. Control the second CPU31 Then, it is written to the second flash R0M32 or the second EEPR0M34.
- FIG. 2 is a diagram showing a configuration example of a storage area of the first flash ROM 12 shown in FIG.
- the storage area of the first flash ROM 12 is, for example, when the power of the image display device 1 is turned on, or in a state similar thereto, that is, when a hardware reset is performed,
- a boot program area 71 that stores a boot program to be executed by the first CPU 11
- an ID information area 7 that stores ID information that specifies which of a later-described upgrade program and a user program is to be executed 2.
- An upgrade program area 73 that stores an upgrade program for updating (upgrading) a user program described later
- a user program area 74 that stores a program that executes processing related to the display of JPEG image data. It consists of.
- the first flash ROM 12 and the SDRAM 13 are stored in the memory space managed by the first CPU 11 by the first CPU 11, for example, “FF000000 (H;)” and “00000000 (H)”. Address areas different from each other are allocated.
- address areas of “FF000000 (H)” to “FF003FFF (H)” are assigned to the boot program area 71, and the boot programs stored in the boot program area 71 are Referring to the ID information stored in the ID information area as described later, the upgrade program stored in the upgrade program area 73 or the user program area 74 is stored based on the information. Specify one of the user programs and execute it on the first CPU 11 (Reset the software).
- Address areas of “FF004000 (H)” to “FF005FFF (H;)” are assigned to the ID information area 72, and as described later, the upgrade program stored in the upgrade program area 73 or In addition, information related to selection of a user program stored in the user program area 74 is stored.
- the address area of “FF006000 (H)” to “FF007FFF (H)” is assigned to the upgrade program area 73, and the upgrade program stored in the upgrade program area 73 Is executed by the first CPU 11 to update the user program stored in the user program area 74 or the upgrade program itself, as described later.
- Address areas FF008000 (H) to FF1EFFF (H) are allocated to the user program area 74, and the user programs stored in the user program area 74 are stored in the first CPU 11 Executed to execute processing related to display of JPEG image data.
- FIG. 3 is a diagram showing a detailed configuration example of the ID information area 72 of FIG.
- the execution program selection determination information 101 stored in the ID information area 72 is composed of 16 bytes of data, and the first CPU that executes the startup program stored in the startup program area 71 11 can select either the upgrade program stored in the upgrade program area 73 or the user program stored in the user program area 74 as the program to be started. Contains such information.
- the first CPU 11 executing the startup program stored in the startup program area 71 selects one of the upgrade program and the user program based on the execution program selection determination information 101. And execute it (perform software reset).
- the stored program normality determination information 102 is composed of 16 bytes of data, and different types of software are recorded in the upgrade program area 73 in Fig. 2. 3 008186
- the 1 CPU 1 1 on the basis of the stored program normal decision information 1 0 2, the up-grade program region 7 3 in FIG. 2, determines whether a program or data that can not be run as ⁇ Tsu upgrade program is stored I do.
- the version information 103 is composed of 4-byte data, and includes version information of the upgrade program stored in the upgrade program area 73 of FIG.
- the checksum information 104 is composed of four bytes of data and includes information for determining whether the data of the upgrade program stored in the update program area 73 of FIG. 2 is normal. I have.
- the program creation date information 105 is composed of 4-byte data, and includes information on the upgrade program creation date stored in the upgrade program area 73 of FIG.
- the target model judgment information 106 and the target microcomputer judgment information 107 consist of 16 bytes of data, and are different from the stored program normal judgment information 102 in the upgrade program area 73 in Fig. 2 . It contains information for determining whether or not software of the different type is recorded.
- the ID checksum information 108 is composed of 4-byte data, and includes information on the upgrade program area 73, including the above-described storage program normality determination information 102 to the target microcomputer determination information 107, as described above. It contains information to confirm whether or not has been destroyed for any reason.
- the ID checksum information 108 is stored at addresses “FF00405C (H)” to “FF00405F (H)”, and the address “FF004010 (H)” To “FF00405B (H)” to confirm whether the information in the area is normal.
- the stored program normality determination information 1 1 2 consists of 16 bytes of data, and whether different types of software are recorded in the user program area 74 in Fig. 2 3 008186
- the first CPU 11 determines, based on the stored program normality determination information 112, whether a program or data that cannot be executed as a user program is stored in the user program area 74 of FIG. .
- the version information 113 includes 4-byte data and includes version information of the user program stored in the user program area 74 of FIG.
- the checksum information 1 14 consists of 4 bytes of data and includes information for determining whether or not the user program data stored in the user program area 74 of FIG. 2 is normal. .
- the program creation date information 115 is composed of 4-byte data, and includes information on the creation date of the user program stored in the user program area 74 of FIG.
- the target model judgment information 1 16 and the target microcomputer judgment information 1 17 consist of 16 bytes of data, and differ from the stored program normal judgment information 1 1 2 in the user program area 74 of FIG. It contains information to determine if the type of software is recorded.
- the ID checksum information 118 consists of 4 bytes of data, and includes information on the user program area 74, including the above-mentioned stored program normal judgment information 112 to the target microcomputer judgment information 117, as described above. It contains information to confirm whether or not has been destroyed for any reason.
- the ID checksum information 118 is stored in the addresses “FF0040AC (H)” to “FF0040AF (H)”, and the address “FF004060 (H ) j to the information of the area from “FF0040AB (H)” to confirm whether the information is normal or not.
- FIG. 4 is a diagram illustrating a configuration example of a storage area of the semiconductor memory 2.
- the storage program normality judgment information 15 1 stored in the storage area of the semiconductor memory 2 is composed of 16 bytes of data. It contains information for determining whether or not the type of software is recorded. That is, the first CPU 11 determines whether a program that cannot be executed by the image display device 1 or data that cannot be processed is stored in the storage area of the semiconductor memory 2 based on the stored program normality determination information 112. judge.
- the version information 152 includes 4-byte data, and includes software version information stored in the storage area of the semiconductor memory 2.
- the checksum information 153 consists of 4 bytes of data and includes information for determining whether software stored in the storage area of the semiconductor memory 2 has been broken for some reason. I have.
- the program creation date information 154 is composed of 4-byte data, and includes information on software creation S stored in the storage area of the semiconductor memory 2.
- the target model judgment information 15 5 and the target microcomputer judgment information 15 6 each consist of 16 bytes of data, and differ from the storage area of the semiconductor memory 2 like the stored program normal judgment information 102. It contains information for determining whether or not software of the different type is recorded.
- the ID checksum information 157 is composed of 4 bytes of data, and includes the storage program normal judgment information 15 1 to the target microcomputer judgment information 156 described above, and is stored in the storage area of the semiconductor memory 2. It contains information to confirm whether or not each piece of software information has been destroyed for any reason.
- the software binary data 158 is program data stored in the storage area of the semiconductor memory 2 and written (installed) in the image display device 1.
- FIG. 5 is a diagram showing an example of the relationship between programs stored in the storage area of the first flash ROM 12 shown in FIG.
- the startup program 201 is stored in the startup program area 71 of FIG.
- the upgrade program 202 is a program stored in the upgrade program area 73 of FIG. 2
- the user program 203 is stored in the user program area 74 of FIG. It is a program.
- the hardware is reset, for example, when the power of the image display device 1 is turned on, the first CPU 11 executes the boot program 20 stored in the boot program area 71 of the first flash R0M 12. Execute 1.
- the first CPU 11 that has executed the startup program 201 performs a startup process, as described later, based on the content of the execution program selection determination information 101 in the ID information area 72 shown in FIG. Select either the upgrade program 202 or the user program 203, copy it to the SDRAM 13 and execute it (perform a soft-to-air reset).
- the first CPU 11 that has executed the upgrade program 202 performs an upgrade process as described below, and writes (installs) the software recorded in the semiconductor memory 2 to a predetermined position. Then, when the processing is completed, the first CPU 11 performs a hardware reset so that the startup program 201 is executed. At this time, the first CPU 11 updates the execution program selection judgment information 101 in the ID information area 72 so that the user program 203 is selected.
- the first CPU 11 executing the user program 203 controls the memory card interface 22 while performing image processing corresponding to the program, and the program to be written is recorded in the memory card slot 21. It monitors whether or not the semiconductor memory 2 is mounted. If it is determined that the semiconductor memory 2 is mounted, a hardware reset is performed so that the startup program 201 is executed. At this time, the first CPU 11 updates the execution program selection determination information 101 in the ID information area 72 so that the upgrade program 202 is selected.
- the first CPU 11 executes the start-up program 201, the upgrade program 202, and the user program 203, and writes the programs and data recorded in the semiconductor memory 2. . 6
- step S1 the first CPU 11 sets an internal register for the SDRAM 13 and performs an initialization process so that the SDRAM 13 can be controlled to record data. .
- step S2 the first CPU 11 is connected to the first CPU 11 and has a first flash ROM 12, a first EEPR0M 14, a memory card interface 22, and a graphic controller. Similarly, set and initialize internal registers for peripheral devices such as 23.
- step S3 the first CPU 11 that has initialized the peripheral device executes ID information confirmation processing for confirming the ID information stored in the ID information area 72 of the first flash ROM 12.
- ID information confirmation processing for confirming the ID information stored in the ID information area 72 of the first flash ROM 12.
- the ID information confirmation processing selects and executes either the upgrade program stored in the upgrade program area 73 of the first flash ROM 12 or the user program stored in the user program area 74.
- the first CPU 11 that has copied the program to the SDRAM 13 performs a software reset in step S4, executes the selected program, and ends the startup processing.
- the first CPU 11 that has been hardware reset copies the upgrade program or user program to the SDRAM 13 and performs a software reset to execute the copied program.
- step S21 the first CPU 11 refers to the ID information storage area 72 of the first flash ROM 12.
- step S22 the first CPU 11 executes the execution program of the ID information area 72. It is determined whether the program selection determination information 101 is normal.
- the execution program selection judgment information 101 specifies the upgrade program stored in the upgrade program area 73 or the user program stored in the user program area 74. If the first CPU 11 determines that the upgrade program has been selected, the first CPU 11 proceeds to step S23 and determines whether or not the upgrade program has been selected as the program to be executed based on the execution program selection determination information 101. Set.
- step S24 the ID information area 72 Based on the stored program normality determination information 102 of 2, it is determined whether or not the selected upgrade program is a correct type of program.
- the first CPU 11 proceeds with the process to step S25 and, based on the ID checksum information 108, stores the ID information in the ID information area 72. It is determined whether the ID information corresponding to the selected upgrade program, which is composed of the stored program normality determination information 102 to the target microcomputer determination information 107, is normal.
- the first CPU 11 stores the ID information in the upgrade program area 73 of the first flash ROM 12 in step S26. Copy the existing upgrade program to SDRAM 13
- step S 27 When the first CPU 11 copies the upgrade program to the SDRAM 13, in step S 27, based on the checksum information 104 in the ID information storage area 72, the copied upgrade program is normal. It is determined whether or not there is. If it is determined that the copied upgrade program has been destroyed for some reason and is not normal, the first CPU 11 returns the process to step S24 and repeats the subsequent processes. If it is determined that the copied upgrade program is normal, the first CPU 11 ends the ID information confirmation processing, and advances the processing to step S4 in FIG. By the way, in step S23, when it is determined that the user program is selected and the upgrade program is not selected based on the execution program selection determination information 101, the first CPU 11 executes the processing in step S23. Proceed to 8.
- step S28 the first CPU 11 determines whether the selected user program is a correct type program based on the stored program normality determination information 112.
- the first CPU 11 proceeds with the process to step S29 and stores the ID information area 72 in the ID checksum information 118. It is determined whether or not the ID information corresponding to the selected user program, which is composed of the program normality determination information 112 and the target microcomputer determination information 117, is normal.
- the first CPU 11 stores the ID information in the user program area 74 of the first flash ROM 12 in step S30. Copy the existing user program to SDRAM 13.
- step S 31 When the first CPU 11 copies the user program to the SDRAM 13, in step S 31, based on the checksum information 114 of the ID information storage area 72, whether the copied user program is normal or not. Determine whether or not.
- the first CPU 11 returns the process to step S24 and repeats the subsequent processes.
- step S22 when it is determined that the execution program selection determination information 101 is not normal due to some reason S, the first CPU 11 proceeds with the process to step S32, and After performing the processing, the ID information confirmation processing ends. In this case, the first CPU 11 omits the process of step S4 in FIG. 6 and ends the startup process.
- step S24 If it is determined in step S24 that the selected upgrade program is not the correct type of program, the first CPU 11 proceeds to step S32, performs error processing, and checks the ID information. The process ends. Also in this case, the first CPU 11 omits the process of step S4 in FIG. 6 and ends the startup process.
- step S25 if it is determined in step S25 that the ID information corresponding to the selected upgrade program is not normal, the first CPU 11 proceeds to step S32 and performs the error processing. Then, the ID information confirmation processing ends. Also in this case, the first CPU 11 omits the process of step S4 in FIG. 6 and ends the startup process.
- step S28 determines in step S31 that the copied user program is not normal. In the same manner as described above, the process returns to step S24, and the subsequent processes are repeated.
- step S29 when it is determined that the ID information corresponding to the selected user program is not normal, the first CPU 11 returns the process to step S24 and repeats the subsequent processes.
- the first CPU 11 performs the ID information confirmation processing, and the first flash ROM Copy the upgrade program or user program to the SDRAM 13 while checking the contents of the ID information area 72 of 12.
- the program copied to the SDRAM 13 is reset by software in step S4 in FIG. 6, and is executed by the first CPU 11.
- the first CPU 11 performs the upgrade process.
- the upgrade process by the first CPU 11 will be described with reference to the flowcharts of FIGS.
- FIGS. 10 to 13 are referred to as needed.
- step S51 the first CPU 11 controls the memory card interface 22 to monitor the state of the memory card slot 21 and checks the state of the memory card slot 21. It is determined whether a change has been detected.
- the memory card interface 22 transmits the information to the first CPU. 1 supply to 1.
- the first CPU 11 determines whether or not the state of the memory card slot 21 has changed based on the information supplied from the memory card interface 22.
- the first CPU 11 proceeds to step S 52, and based on the information, the first CPU 11 proceeds to step S 52. 21. It is determined whether or not the semiconductor memory 2 is mounted on 1.
- the first CPU 11 proceeds with the process to step S 53, generates a GUI for installation, and executes the graphic controller 23 and scaling.
- the screen is supplied to the display unit 26 via the device 24 and the display device controller 25, and the screen to be displayed is switched to the GUI screen for mounting.
- the display unit 26 that has acquired the GUI for mounting is controlled by the display device controller 25 to display, for example, a GUI screen for mounting as shown in FIG. 10 on a display.
- the button 2 11 A displayed as “Write” is in an operable state (active), and the user must operate the input unit 3 3. By operating the button 211A, it is possible to instruct the start of writing (upgrade start).
- the first CPU 11 which has switched the display screen to the GUI for mounting, advances the processing to step S58.
- step S52 If it is determined in step S52 that the semiconductor memory 2 is not installed in the memory card slot 21, the first CPU 11 proceeds with the process to step S54 and generates a GUI for when no memory is installed. Then, the screen is supplied to the display unit 26 via the graphic controller 23, the scaling device 24, and the display device controller 25, and the screen to be displayed is switched to the GUI screen when not mounted.
- the display unit 26 that has acquired the GUI for when not mounted is controlled by the display device controller 25 to display a GUI screen for when not mounted, for example, as shown in FIG. 11 on the display.
- buttons 22 1 A displaying “Home” are in an operable state (active), and the user operates the input unit 3 3
- the user instructs to stop the processing related to writing, displays the “Home J screen” which is a GUI screen that displays a predetermined basic menu on the display, and performs other processing. Can be selected.
- the first CPU 11 that has switched the display screen to the GUI for non-mounted state advances the processing to step S58.
- step S51 information on the state of the memory card slot 21 has not been obtained from the memory card interface 22 and the memory card interface 22 has detected a change in the state of the memory card slot 21. If it is determined that it has not been performed, the first CPU 11 proceeds with the process to step S55.
- step S55 the first CPU 11 determines whether or not the error-time GUI or the completion-time GUI is displayed on the display unit 26.
- Write (Upgrade 1) the first CPU 11 generates the GUI for completion, and the display unit 2 is displayed via the graphic controller 23, the scaling device 24, and the display device controller 25. Supply to 6. Display that has acquired the GUI for completion
- the display device controller 25 is controlled by the display device controller 25 to display, for example, a GUI screen for completion as shown in FIG. 12 on the display.
- the button 2 31 A displayed as “0K” is in an operable state (active), and the user operates the input section 33. By doing so, it is possible to confirm the completion of writing by operating the button 2 3 1 ⁇ .
- the first CPU 11 generates a GUI for an error and sends it via the graphic controller 23, the scaling device 24, and the display device controller 25. It is supplied to the display unit 26.
- the display unit 26 that has acquired the GUI for error is controlled by the display device controller 25 to display a GUI screen for error, for example, as shown in FIG. 13 on the display.
- the button 2 41 A displayed as “0K” is in an operable state (active), and the user must operate the input section 33.
- the user can operate the button 2 41 ⁇ and confirm that an error has occurred in writing.
- step S55 the first CPU 11 determines whether or not the error GUI or the completion GUI as described above is displayed on the display unit 26, and displays the same. If it is determined that the request has not been received, the first CPU 11 proceeds to step S58.
- step S56 the first CPU 11 controls the second CPU 31 to
- Monitor 3 to determine whether a user operation has been detected.
- the first CPU 11 The second CPU 31 is caused to execute a process of monitoring the input unit 33 via the communication bus 15.
- the second CPU 31 monitors the input unit 33, detects whether or not the user has operated the input unit 33, and notifies the first CPU 11 of the fact via the communication bus 15. .
- the first CPU 11 determines whether a user operation has been detected based on the information.
- the first CPU 11 returns the process to step S51, and repeats the subsequent processes. If it is determined that the user operation has been detected, the first CPU 11 advances the process to step S57, deletes the error GUI or the completion GUI displayed on the display unit 26, and deletes the GUI. Is initialized. The first CPU 11 that has initialized the GUI returns the process to step S51 and repeats the subsequent processes.
- the first CPU 11 operates the input unit 33 to Repeat steps S51, S55, and S56 until you operate 2 3 1 A or button 2 41 A, and wait.
- the first CPU 11 displays the GUI screen 2 3 for completion displayed on the display unit 26. 1 or GUI screen for error 2 4 1 is deleted.
- step S53 when the display screen of the display unit 26 is switched to the GUI screen 2 1 1 for mounting, in step S54, the display screen of the display unit 26 is When the screen is switched to the GUI screen 221, or when it is determined in step S55 that the GUI screen 231 for completion or the GUI screen 241 for error is not displayed on the display unit 26,
- the first CPU 11 advances the process to step S58.
- step S58 similarly to step S56, the second CPU 31 is controlled to monitor the input unit 33, and the first CPU 11 determines whether or not a user operation has been detected. Is determined.
- the first CPU 11 returns the process to step S51 and repeats the subsequent processes.
- the first CPU 11 proceeds to step S61 of FIG. 9 and performs the processing of step S52.
- the memory card interface 22 is controlled to determine whether or not the semiconductor memory 2 is mounted on the memory card slot 21.
- the first CPU 11 proceeds to step S62, and the file to be written to the image display device 1 is stored in the storage area of the mounted semiconductor memory 2. Determine whether it exists.
- the first CPU 11 that has completed the rewriting process returns the process to step S51 in FIG. 8, and repeats the subsequent processes.
- step S62 If it is determined in step S62 that no software binary data or ID information has been recorded in the storage area of the semiconductor memory 2 and that the target file does not exist, the first CPU 11 proceeds to step S62. Proceed to S64 to display the temporary error GUI on the display unit 26.
- the first CPU 11 displaying the GUI for error on the display unit 26 returns the process to step S51 in FIG. 8, and repeats the subsequent processes.
- step S61 if it is determined that the semiconductor memory 2 is not installed in the memory card slot 21, the first CPU 11 advances the process to step S65, where the ID of the first flash ROM 12 is The contents of the execution program selection judgment information 101 stored in the information area 72 are rewritten so that the user program is selected and executed.
- step S66 the first CPU 11 performs a hardware reset. To complete the upgrade process.
- the first CPU 11 executing the upgrade program 202 of FIG. 5 performs the upgrade process as described above, and writes the software stored in the storage area of the semiconductor memory 2 to the image display device 1. (install) .
- step S81 the first CPU 11 determines whether to install the target file in the storage area of the first flash R0M12.
- the programs and data stored in the storage area of the semiconductor memory 2 are stored in the first flash ROM 12, the first EEPR0M 14, the second flash ROM 32, or the second EEPR0M 34 of the image display device 1. Is written (installed).
- the writing (installation) destination is specified by the target model determination information 155 stored in the storage area of the semiconductor memory 2 shown in FIG.
- step S81 the first CPU 11 first installs programs and data stored in the storage area of the semiconductor memory 2 in the first flash ROM 12 based on the target model determination information 1555. It is determined whether or not.
- the first CPU 11 proceeds to step S82.
- the target file is read from the semiconductor memory 2 mounted on the memory card slot 21, supplied to the SDRAM 13, and held.
- the first CPU 11 specifies an area of the SDRAM 13 that is different from the area where the copied upgrade program is stored, as the area for storing the target file.
- step S83 the first CPU 11 checks the target file held in the SDRAM 13 and determines whether or not the reading has been normally performed.
- step S84 Erases data stored in the area specified as the storage location of the target file in the storage area of the R0M12.
- step S85 the first CPU 11 writes the target file held in the SDRAM 13 into the first flash ROM 12 based on the target microcomputer determination information 156 in FIG. Write (install) in the specified area.
- the first CPU 11 that has written the target file proceeds to step S86, and determines whether or not writing (installation) has been performed normally based on the checksum information 1553 in FIG. .
- step S87 If it is determined that the writing (installation) has been performed normally, the first CPU 11 proceeds with the process to step S87, generates a GUI for completion, and executes the graphic controller 23, the scaling device 2 4, and the display device controller 25 is supplied to the display unit 26 to display the GUI screen 231 for completion shown in FIG.
- the first CPU 11 displaying the GUI screen 2 31 for completion completes the rewriting process and returns the process to step S51 in FIG.
- step S83 If it is determined in step S83 that the target file copied to the SDRAM 13 has been destroyed for some reason and reading has not been performed normally, the first CPU 11 Advances the process to step S88.
- step S86 if it is determined in step S86 that writing of the target file to the first flash ROM 12 has not been performed normally, the first CPU 11 proceeds with the process to step S88.
- step S88 the first CPU 11 generates a GUI for an error and supplies it to the display unit 26 via the graphic controller 23, the scaling device 24, and the display device controller 25. Display the error GUI screen 2 41 shown in Fig. 13.
- the first CPU 11 displaying the error GUI screen 2 41 ends the rewriting process and returns to the step S51 in FIG.
- the first CPU 11 executes the processing in step S89.
- the first CPU 11 proceeds to step S90, and proceeds to step S90.
- the target file is read from the semiconductor memory 2 inserted in the memory card slot 21, supplied to the SDRAM 13, and held.
- the first CPU 11 specifies, as an area for storing the target file, an area of the SDRAM 13 that is different from the area in which the copied upgrade program is stored.
- step S91 the first CPU 11 checks the target file held in the SDRAM 13 and determines whether or not reading has been normally performed.
- the first CPU 11 advances the process to step S92 and stores the data in the storage area of the first EEPROM 14 Deletes the data stored in the area specified as the storage location of the target file.
- step S93 the first CPU 11 writes the target file held in the SDRAM 13 into a predetermined file in the first EEPROM 14 based on the target microcomputer determination information 156 in FIG. Write to the area (install).
- the first CPU 11 that has written the target file proceeds to step S944, and determines whether or not the writing (installation) has been normally performed based on the checksum information 1553 in FIG. .
- step S95 If it is determined that the writing (installation) has been performed normally, the first CPU 11 proceeds to step S95, generates a GUI for completion, and executes the graphic controller 23, the scaling device. 24 and display device controller 25 8186
- the first CPU 11 displaying the GUI screen 2 31 for completion completes the rewriting process and returns the process to step S51 in FIG.
- step S91 If it is determined in step S91 that the target file copied to the SDRAM 13 has been destroyed for some reason and reading has not been performed normally, the first CPU 11 Then, the process proceeds to step S96.
- step S94 determines whether the target file has been correctly written to the first flash R0M12. If it is determined in step S94 that the target file has not been correctly written to the first flash R0M12, the first CPU 11 proceeds with the process to step S96.
- step S96 the first CPU 11 generates a GUI for an error and supplies it to the display unit 26 via the graphic controller 23, the scaling device 24, and the display device controller 25.
- the GUI screen for error 24 1 shown in FIG. 13 is displayed.
- the first CPU 11 displaying the error GUI screen 2 41 ends the rewriting process and returns to the step S51 in FIG.
- step S89 If it is determined in step S89 that the program data stored in the storage area of the semiconductor memory 2 is not to be installed in the first EEPR0M14, the first CPU 11 executes the processing. Proceed to step S101 of step 15.
- step S101 of FIG. 15 the first CPU 11 uses the semiconductor memory based on the target model determination information 1555 similarly to the case of steps S81 and S89 of FIG. 14. It is determined whether to install the programs and data stored in the second storage area in the second flash ROM 32.
- the first CPU 11 advances the process to step S102.
- the memory card interface 22 is controlled and the semiconductor memory 2 installed in the memory card slot 21 Read the file, supply it to SDRAM13, and hold it.
- the first CPU 11 specifies an area of the SDRAM 13 that is different from the area where the copied upgrade program is stored, as the area for storing the target file.
- step S103 the first CPU 11 checks the target file held in the SDRAM 13 and determines whether or not reading has been normally performed.
- the first CPU 11 advances the process to step S 104, controls the second CPU 31, and Causes the CPU 31 to execute a boot-only program stored in a built-in ROM (not shown).
- the first CPU 11 controls the second CPU 31 via the control bus 16, causes the second CPU 31 to execute the boot-only program, and sets the program to be installed in the second flash R0M32. Software reset.
- the second CPU 31 that has been software-reset executes the boot-only program and starts preparations for a write process to the second flash R0M32. When the preparation is completed, the second CPU 31 requests the target file from the first CPU 11 via the communication bus 15.
- step S105 the first CPU 11 determines whether or not the request for the target file has been obtained, and waits until it determines that the request has been obtained.
- step S 106 If it is determined that the request for the target file has been obtained from the second CPU 31, the first CPU 11 proceeds to step S 106, and transfers the requested target file to the second CPU 3 via the communication bus 15.
- Supply 1
- the second CPU 31 supplied with the target file writes the acquired target file at a predetermined address position of the second flash R0M32 (installs). Then, the second CPU 31 refers to the target file written in the second flash R0M32, determines whether or not the first CPU 1 has been installed normally, and transmits the determination result via the communication bus 15 to the first CPU 1 Supply 1
- step S107 the first CPU 11, which has obtained the determination result, obtains the determination result. 3 008186
- step S108 If it is determined that the installation to the second flash ROM 32 has been performed normally, the first CPU 11 proceeds with the process to step S108, generates a GUI for completion, and The data is supplied to the display unit 26 via the scaling device 24 and the display device controller 25, and the GUI screen 231 for completion shown in FIG. 12 is displayed.
- the first CPU 11 displaying the GUI screen 2 31 for completion completes the rewriting process and returns the process to step S51 in FIG.
- step S107 If it is determined in step S107 that the target file has not been properly installed on the second flash R0M32, the first CPU 11 proceeds to step S109.
- the GUI for error is generated and supplied to the display unit 26 via the graphic controller 23, the scaling device 24, and the display device controller 25, and the error GUI screen shown in Fig. 13 is displayed. Display 2 4 1.
- the first CPU 11 displaying the error GUI screen 2 41 ends the rewriting process and returns to the step S51 in FIG.
- step S101 it was determined that the target file stored in the storage area of the semiconductor memory 2 was data, and that the target file was to be installed in the second EEPR0M 34 and not to be installed in the second flash ROM 32.
- the first CPU 11 advances the process to step S110.
- step S110 the first CPU 11 controls the memory card interface 22 to install the target file in the second EEPR0M 34, and controls the semiconductor memory mounted in the memory card slot 21. From 2, the target file is read, supplied to SDRAM 13, and held. At this time, the first CPU 11 specifies, as an area for storing the target file, an area of the SDRAM 13 that is different from the area in which the copied upgrade program is stored. Then, in step S111, the first CPU 11 checks the target file held in the SDRAM 13 and determines whether or not the reading has been performed normally.
- the first CPU 11 proceeds with the process to step S 112 and controls the second CPU 31 to control the second CPU 31. 1. Execute a boot-only program stored in the built-in ROM (not shown).
- the first CPU 11 controls the second CPU 31 via the control bus 16, causes the second CPU 31 to execute the boot-only program, and sets the program to be installed in the second EEPR0M34. Perform a software reset.
- the software-reset second CPU 31 executes the boot-only program, and starts preparation for the writing process on the second EEPROM 34. When the preparation is completed, the second CPU 31 requests the target file from the first CPU 11 via the communication bus 15.
- step S113 the first CPU 11 determines whether or not the request for the target file has been acquired, and waits until it is determined that the request has been acquired.
- step S 114 If it is determined that the request for the target file has been obtained from the second CPU 31, the first CPU 11 proceeds to step S 114, and transfers the requested target file to the second CPU 31 via the communication bus 15.
- the second CPU 31 supplied with the target file writes the acquired target file to a predetermined address position of the second EEPR0M34 (installs). Then, the second CPU 31 refers to the target file written in the second EEPR0M34, determines whether or not the installation has been normally performed, and supplies the determination result to the first CPU 11 via the communication bus 15 .
- step S115 the first CPU 11 that has obtained the determination result determines whether or not the target file has been normally installed based on the obtained determination result.
- the first CPU 11 advances the process to step S116, generates a GUI for completion, and displays the GUI 26 via the Dramatic controller 23, the scaling device 24, and the display device controller 25. To display the GUI screen 2 31 for completion shown in Figure 12.
- the first CPU 11 displaying the GUI screen 2 31 for completion completes the rewriting process and returns the process to step S51 in FIG.
- step S111 If it is determined in step S111 that the reading has not been performed normally, and if in step S115 the supply of the target file to the second CPU 31 has not been performed normally, If it is determined, the first CPU 11 advances the process to step S117, generates a GUI for error, and displays the GUI via the graphic controller 23, the scaling device 24, and the display device controller 25. It is supplied to the display unit 26 to display the GUI screen 2 41 for errors shown in FIG.
- the first CPU 11 displaying the error GUI screen 2 41 ends the rewriting process and returns to the step S51 in FIG.
- the first CPU 11 performs the processing according to the specified installation destination, and installs the target file.
- the target file is installed in the second flash ROM 32 or the second EEPR0M 34 corresponding to the second CPU 31, the first CPU 11 transmits the second file via the control bus 16. Controls CPU 31 to perform processing.
- the image display device 1 can easily install the supplied program in a plurality of storage units controlled by different CPUs.
- the first CPU 11 copies the update program stored in the first flash R0M 12 to the SDRAM 13 and executes it. Therefore, even if the target file is the upgrade file itself, Can be installed in flash ROM12. At this time, the L CPU 11 is executing the old upgrade program copied to the SDRAM 13 and executing the new upgrade program that has been installed by performing a software reset.
- the CPU 11 controls the second CPU 31 via the control bus 16, causes the second CPU 31 to execute the boot-only program, and installs the program in the second flash R0M32 or the second EEPR0M34. And perform a software reset.
- the software-reset second CPU 31 executes the boot-only program and starts the writing process to the second flash R0M32 or the second EEPR0M34.
- the write processing by the second CPU 31 will be described with reference to the flowchart in FIG.
- the second CPU 31 is connected to the second CPU 31, such as the second flash R0M32, the input unit 33, the second EEPR0M 34, and the scaling device 24. Set and initialize internal registers for peripheral devices.
- step S132 the second CPU 31 sets the device to which the target file is to be written to the device designated by the first CPU 11, that is, any one of the second flash ROM 32 and the second EEPR0M34. Set crab.
- step S133 the second CPU 31 which has set the write destination device requests the first CPU 11 via the communication bus 15 for a file to be installed.
- the first CPU 11 requested for the target file detects the request in the processing of step S105 or step S113 in FIG. 15 and detects step S106 or step S114.
- the requested file is supplied to the second CPU 31 via the communication bus 15 by the processing of (1).
- step S134 the second CPU 31 determines whether or not the target file requested by the first CPU 11 has been obtained, and waits until it determines that the file has been obtained.
- step SI35 If it is determined that the target file has been acquired, the second CPU 31 executes the process. Proceed to step SI35, and write (install) the acquired target file to the write destination device set in step S132, that is, either the second flash ROM 32 or the second EEPR0M 34. .
- the second CPU 31 Upon writing the target file, the second CPU 31 checks in step S136 whether the written target file is normal, and in step S137, checks the result of the check. Then, the data is supplied to the first CPU 11 via the communication bus 15 and the write processing ends.
- the second CPU 31 is reset by software to the first CPU 11 and executes the write processing.
- the image display device 1 can easily install the supplied program in a plurality of storage units controlled by different CPUs.
- the upgrade program 202 is executed by the first CPU 11, and when the hardware reset is performed in step S ⁇ b> 66 in FIG. 9, the first CPU 11 becomes as shown in FIG. 5.
- Run the boot program 201 as shown.
- the first CPU 11 causes the execution program selection determination information 101 stored in the ID information area 72 of the first flash R0M12 to select the user program. Therefore, the first CPU 11 executing the boot program 201 executes the user program stored in the user program area 74 of the first flash ROM 12 in step S30 of FIG. 20 3 is copied to SDRAM 13, and a software reset is performed in step S 4 of FIG. 6 to execute the user program 203 copied to SDRAM 13.
- the first CPU 11 executing the user program controls the memory card interface 22 to monitor a change in the state of the memory card slot 21 while performing predetermined processing relating to image processing.
- the first CPU 11 executes step S 5 1 of FIG. 8 in step S 15 1.
- the memory card interface 22 is controlled to monitor the state of the memory card slot 21 and determine whether or not a change in the state of the memory card slot 21 is detected.
- the first CPU 11 proceeds to step S 15 2, and proceeds to step S 52. Similarly, it is determined whether or not the semiconductor memory 2 is mounted in the memory card slot 21 based on the information.
- step S 15 3 If it is determined that the semiconductor memory 2 is installed in the memory card slot 21, the first CPU 11 proceeds to step S 15 3, and performs the same processing as in step S 62 in FIG. It is determined whether or not a file to be written to the image display device 1 exists in the storage area of the mounted semiconductor memory 2.
- step S 154 the execution program selection determination information 101 stored in the ID information area 72 of the first flash R0M 12 is read. Rewrite the contents so that the upgrade program 202 is selected and executed.
- step S155 the first CPU 11 performs a hardware reset, and ends the user program execution processing.
- step S151 if it is determined in step S151 that a change in the state of the memory card slot 21 has not been detected, the first CPU 11 proceeds with the process to step S156.
- step S152 If it is determined in step S152 that the semiconductor memory 2 is not mounted in the memory card slot 21, the first CPU 11 advances the process to step S156.
- step S153 determines whether the target file does not exist in the storage area of the semiconductor memory 2 mounted on the memory card slot 21, the first CPU 11 executes the processing in step S155. Proceed to 6.
- step S156 the first CPU 11 controls each unit to execute the user program. Processing related to predetermined image processing defined in RAM 203 is performed.
- step S156 the first CPU 11 controls the memory card interface 22, the graphic controller 23, and the like, and supplies information to the second CPU 31.
- the GUI data is supplied to the display unit 26.
- FIG. 18 is a diagram showing an example of a screen displayed on the display unit 26 by the process of step S156.
- a GUI screen 2 51 is a screen that displays a list of thumbnail images corresponding to the JPEG image data input to the image display device 1.
- the display unit 26 is controlled by the display device controller 25 to display a GUI screen 251 as shown in FIG. 18 on the display.
- step S156 may be processing other than the processing described above, and may be any processing defined in the user program 203.
- the first CPU 11 having completed the processing of step S156 returns the processing to step S151, and repeats the subsequent processing.
- the first CPU 11 executing the user program 203 executes the predetermined process in step S156, and the target file to be installed in steps S151 to S153 is Judgment is made as to whether or not it has been prepared, and if it has been prepared, the processing in steps S154 and S155 sets the startup program 201 to select the upgrade program before resetting the hardware. And run the startup program 201.
- step S151 If the target file to be installed is not prepared (if it is determined in step S151 that a change in the state of the memory card slot 21 has not been detected, then in step S152, the semiconductor memory If it is determined that No. 2 has not been inserted, and if it is determined in step S 153 that the target file does not exist), the first CPU 11 executes the processing in step S 156 repeat.
- the first CPU 11 executes the user program while checking whether the target file to be installed has been prepared. This allows the image 6
- the user of the display device 1 can easily perform the installation process.
- the first CPU 11 performs the hardware reset and the software reset so that the upgrade program 202 and the user program 203 are continuously executed through the start program 201.
- other CPUs can be controlled according to the set installation destination, so that multiple programs can be easily written consecutively. .
- the target file to be installed is supplied to the image display device 1 in a state recorded in the semiconductor memory 2.
- the present invention is not limited to this.
- a communication medium such as a network may be used.
- it may be supplied via a personal computer.
- a first flash R0M12 and a first EEPR0M14 are connected to the first CPU 11 one by one, and a second flash ROM 32 and a second flash ROM 32 are connected to the second CPU 31.
- the second EEPR0M 34 are described as being connected one by one.
- the present invention is not limited to this.
- a plurality of flash ROMs may be connected to the first CPU 11 or a plurality of EEPR0Ms may be connected. May be connected. The same applies to the second CPU 31.
- the first flash R0M12, the first EEPR0M14, the second flash ROM 32, and the second EEPR0M34 have been described as being configured separately.
- the present invention is not limited to this, and all or some of them may be integrated. Further, these may be integrated with other parts such as the first CPU 11 and the second CPU 31.
- the program executed in the first CPU 11 is stored in the first flash R0M12, and the first CPU 11 is stored in the first EEPR0M14.
- the first flash R0M12 and the first EEPR0M14 any data may be stored.
- the first flash ROM 12 may store not only programs but also data.
- the present invention is not limited to this. It may be individual.
- the present invention is applicable to any information processing device controlled by a plurality of CPUs.
- the present invention can be applied to a personal computer having a plurality of CPUs.
- FIG. 19 is a diagram showing an example of a personal computer to which the present invention is applied.
- the first CPU 301 of the personal computer 300 stores the program stored in the first ROM 302 or the first flash ROM 304 or the storage unit 344 Various processing is executed according to the program loaded in the first RAM 303.
- the first RAM 303 and the first flash R0M 304 also appropriately store data necessary for the first CPU 301 to execute various processes.
- the storage area of the first flash R0M 304 has the same configuration as that shown in FIG. 2, and a startup program area 71 for storing the startup program 201, and stores information about programs and data. It consists of an ID information area 72 to be stored, an upgrade program area 73 to store the upgrade program 202, and a user program area 74 to store the user program.
- the first CPU 301, the first ROM 302, the first RAM 303, and the first flash ROM 304 are interconnected via a bus 310.
- the second CPU 321 of the personal computer 300 is a program stored in the second R0M 322 or the second flash ROM 324, or Various processes are executed according to the program loaded from the storage section 343 to the second RAM 323.
- 2nd RAM 3 2 3 and 2nd Flash ROM 3 2 4 Also, like the first RAM 303 and the first flash R0M 304, data necessary for the second CPU 321 to execute various processes is stored as appropriate.
- the second flash R0M 324 has the same configuration as that of the first flash ROM 304, as shown in FIG. 2, and has a boot program area 71, which stores the boot program 201, ID information area for storing information on program data 7
- It comprises an upgrade program area 73 for storing the upgrade program 202 and a user program area 74 for storing the user program.
- bus 330 is mutually connected via a bus 330.
- an input / output interface 340 is also connected to the bus 310 and the bus 330.
- the input / output interface 340 includes an input section 341 including a keyboard and a mouse, a display including a CRT (Cathode Ray Tube) and an LCD (Liquid Crystal Display), and an output section 344 including a speaker and the like. 2.
- a storage unit 344 composed of a hard disk, etc., and a communication unit 344 composed of a modem, terminal adapter, or LAN adapter are connected.
- the storage unit 343 stores data and programs for executing various processes, and is controlled by the first CPU 301 or the second CPU 321 as needed, and Supply data and programs to 303 or the second RAM 323.
- a drive 350 is connected to the input / output interface 34 ⁇ as necessary, such as a magnetic disk 35 1, an optical disk 35 2, a magneto-optical disk 35 3, or a semiconductor memory 354.
- the computer programs, which are mounted as appropriate and read from them, are installed in the storage unit 343, the first flash R0M304, or the second flash R0M324, as necessary.
- the drive 350 corresponds to the memory card slot 21 in FIG. 1, and the magnetic disk 351, the optical disk 352, and the magneto-optical disk storing programs and data to be installed are stored. 3 5 3 or semiconductor memory 3 5 4 etc. A recording medium is mounted.
- the input / output interface 340 corresponds to the memory card interface 22 in FIG. 1, and is controlled by the first CPU 301 or the second CPU 321 to monitor the status of the drive 350. Then, it is determined whether or not the above-described recording medium is mounted on the drive 350, and the information is supplied to the first CPU 301 or the second CPU 321.
- the processing to be executed is preliminarily shared, so that different processing is executed and different parts are controlled.
- the first CPU 301 and the second CPU 321 of the personal computer 300 in FIG. 19 have the same configuration as each other, and the processing to be executed is not shared in advance.
- either the first CPU 301 or the second CPU 321 may correspond to the first CPU 11 in FIG. That is, the startup processing shown in FIG. 6 and the upgrade processing shown in FIGS. 8 and 9 are executed by either one of the first CPU 301 and the second CPU 321. Alternatively, it may be executed by both.
- the first CPU 301 when associating the first CPU 301 with the first CPU 11 in FIG. 1, the first CPU 301 includes a start program 201 and an upgrade program 202 as shown in FIG. , And execute the user program 203.
- the L CPU 301 executes the startup processing described with reference to the flowchart of FIG. 6 and the ID information confirmation processing described with reference to the flowchart of FIG.
- the upgrade process described with reference to the flowcharts of FIGS. 8 and 9, the rewrite process described with reference to the flowcharts of FIGS. 14 and 15, and the flowchart of FIG. The same processing as the user program execution processing described above is performed, and the supplied program and data are installed in the first flash ROM 304.
- the first CPU 301 controls the second CPU 321, and causes the second CPU 3221 to execute a boot-only program stored in advance in the second ROM 3222 or the like. 6
- the same processing as the writing processing described with reference to the flowchart is executed.
- the second CPU 321 can install the supplied program and data in the second flash OM 324.
- the first CPU 301 continuously executes the upgrade program 202 and the user program 203 via the startup program 201 by performing a hardware reset and a software reset. Also, in the upgrade process, other CPUs can be controlled according to the set installation destination, so that multiple programs can be easily written consecutively. Can be.
- the program data stored in the recording medium such as the magnetic disk 351, the optical disk 352, the magneto-optical disk 353, and the semiconductor memory 354 is stored in the first flash ROM 304.
- the flash memory is installed in the second flash ROM 324.
- the present invention is not limited to this, and the flash memory 324 may be installed in the storage unit 343.
- programs and data to be installed may be supplied not through the recording medium but through the communication unit 344.
- a part of the internal configuration of the personal computer 300 shown in FIG. 19 may be configured as another personal computer.
- a plurality of personal computers as shown in FIG. May be configured as an information processing system communicably connected to each other.
- a personal computer 401 is connected to a personal computer via a network 402 represented by an Internet LAN (Local Area Network) or the like. It is connected to the null computer 403.
- the personal computer 401 can communicate with the personal computer 403 via the network 402.
- the CPU (not shown) of the personal computer 401 of FIG. 20 is made to correspond to the first CPU 301 of FIG. 19, and the CPU (not shown) of the personal computer 400 of FIG. In correspondence with the second CPU 321 in FIG. 19, the CPU power activation program 201, the upgrade program 202, and the user program 203 of the personal computer 401 are executed.
- the CPU (not shown) of the personal computer 401 installs programs and data stored in a recording medium (not shown) attached to a drive (not shown) in a storage unit (not shown).
- the CPU (not shown) of the personal computer 403 is controlled via the network 402 to execute the boot-only program, so that the writing described with reference to the flowchart of FIG. 16 is performed.
- the same processing as the processing is executed, and further, the program data is supplied via the network 402, and the program data is installed in a storage unit (not shown).
- the CPU (not shown) of the personal computer 401 can execute the upgrade program 202 and the user program 203 continuously through the start program 201. Further, since the CPU of another personal computer 403 can be controlled via the network 402, a plurality of programs and data can be easily written continuously.
- the information processing system described above is connected to the network 402.
- the description has been made so as to be constituted by two connected personal computers 401 and 403, the present invention is not limited to this, and any number of personal computers may be included in the information processing system.
- the above processing can be executed by hardware, but can also be executed by software.
- the programs that make up the software execute various functions by installing a computer built into dedicated hardware or installing various programs. It can be installed, for example, on a general-purpose personal computer from a network or a recording medium.
- this recording medium is provided separately from the main body of the apparatus, and is distributed to provide a program to a user.
- Optical disk 352 (including CD-ROM (Compact Disk-Read Only Memory), DVD (Digital Versatile Disk)), magneto-optical disk 3 5 3 (MD (Mini- Disk), or package media consisting of semiconductor memories 2 and 354, etc., as well as programs that are provided to the user in a state that they are pre-installed in the device body. It is composed of a ROM (not shown) built in the 1 CPU 11, the second CPU 31, the first CPU 301, and the second CPU 321, and the like.
- steps for describing a program to be recorded on a recording medium are not limited to processing performed in chronological order according to the described order, but are not necessarily performed in chronological order. Alternatively, it also includes processing that is executed individually.
- system represents the entire device configured by a plurality of devices.
- the information processing apparatus and method of the present invention the recording medium, and the producer According to the program, the program can be rewritten.
- a program can be easily and continuously written to a plurality of storage units controlled by different CPUs.
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Security & Cryptography (AREA)
- Quality & Reliability (AREA)
- Stored Programmes (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP03738549A EP1519270A4 (en) | 2002-06-28 | 2003-06-27 | INFORMATION PROCESSING UNIT AND METHOD, RECORDING MEDIUM AND PROGRAM |
US10/519,088 US20060190421A1 (en) | 2002-06-28 | 2003-06-27 | Information processing apparatus and method, recording medium, and program |
KR1020047020384A KR100945994B1 (ko) | 2002-06-28 | 2003-06-27 | 정보 처리 장치 및 방법, 및 기록 매체 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002190001A JP2004030539A (ja) | 2002-06-28 | 2002-06-28 | 情報処理装置および方法、記録媒体、並びにプログラム |
JP2002-190001 | 2002-06-28 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2004003742A1 true WO2004003742A1 (ja) | 2004-01-08 |
Family
ID=29996867
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2003/008186 WO2004003742A1 (ja) | 2002-06-28 | 2003-06-27 | 情報処理装置および方法、記録媒体、並びにプログラム |
Country Status (6)
Country | Link |
---|---|
US (1) | US20060190421A1 (ja) |
EP (1) | EP1519270A4 (ja) |
JP (1) | JP2004030539A (ja) |
KR (1) | KR100945994B1 (ja) |
CN (1) | CN100409192C (ja) |
WO (1) | WO2004003742A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100440148C (zh) * | 2005-08-24 | 2008-12-03 | 松下电器产业株式会社 | 信息处理设备及在其非易失性存储器中写入数据的方法 |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7228377B2 (en) * | 2003-06-06 | 2007-06-05 | Renesas, Technology Corp. | Semiconductor integrated circuit device, IC card, and mobile terminal |
JP2007026318A (ja) * | 2005-07-20 | 2007-02-01 | Nec Corp | 携帯電話機、プログラム作成方式、プログラム更新方式、プログラム作成方法及びプログラム更新方法 |
JP2008139360A (ja) * | 2006-11-30 | 2008-06-19 | Teac Corp | オーディオ再生装置 |
JP5166955B2 (ja) * | 2008-04-24 | 2013-03-21 | キヤノン株式会社 | 情報処理装置、情報処理方法、及び、情報処理プログラム |
JP6468168B2 (ja) * | 2015-11-05 | 2019-02-13 | 株式会社デンソー | 電子制御装置 |
CN108597470B (zh) * | 2018-05-08 | 2021-01-01 | Tcl华星光电技术有限公司 | 显示装置驱动系统及方法和显示装置 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0844556A2 (en) | 1996-11-26 | 1998-05-27 | Murata Kikai Kabushiki Kaisha | Software updating method |
JPH10260845A (ja) * | 1997-03-19 | 1998-09-29 | Fujitsu Ltd | ファームウェアの更新処理機能を有するマルチcpuシステム |
JP2000311087A (ja) * | 1999-04-28 | 2000-11-07 | Matsushita Electric Ind Co Ltd | データ伝送装置 |
JP2001125789A (ja) * | 1999-10-27 | 2001-05-11 | Tamura Electric Works Ltd | プログラムダウンロード方法 |
JP2001202238A (ja) * | 2000-01-18 | 2001-07-27 | Nec Corp | プロセッサおよびプロセッサマイクロコードアップデート方法 |
JP2001319267A (ja) * | 2000-05-09 | 2001-11-16 | Sanden Corp | 自動販売機の制御システム |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
ATE197097T1 (de) * | 1993-03-31 | 2000-11-15 | Siemens Ag | Verfahren und anordnung zum neu- bzw. nachladen von prozessorsteuerprogrammen |
-
2002
- 2002-06-28 JP JP2002190001A patent/JP2004030539A/ja active Pending
-
2003
- 2003-06-27 US US10/519,088 patent/US20060190421A1/en not_active Abandoned
- 2003-06-27 WO PCT/JP2003/008186 patent/WO2004003742A1/ja active Application Filing
- 2003-06-27 KR KR1020047020384A patent/KR100945994B1/ko not_active IP Right Cessation
- 2003-06-27 CN CNB038153580A patent/CN100409192C/zh not_active Expired - Fee Related
- 2003-06-27 EP EP03738549A patent/EP1519270A4/en not_active Withdrawn
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0844556A2 (en) | 1996-11-26 | 1998-05-27 | Murata Kikai Kabushiki Kaisha | Software updating method |
JPH10260845A (ja) * | 1997-03-19 | 1998-09-29 | Fujitsu Ltd | ファームウェアの更新処理機能を有するマルチcpuシステム |
JP2000311087A (ja) * | 1999-04-28 | 2000-11-07 | Matsushita Electric Ind Co Ltd | データ伝送装置 |
JP2001125789A (ja) * | 1999-10-27 | 2001-05-11 | Tamura Electric Works Ltd | プログラムダウンロード方法 |
JP2001202238A (ja) * | 2000-01-18 | 2001-07-27 | Nec Corp | プロセッサおよびプロセッサマイクロコードアップデート方法 |
JP2001319267A (ja) * | 2000-05-09 | 2001-11-16 | Sanden Corp | 自動販売機の制御システム |
US20010044675A1 (en) | 2000-05-09 | 2001-11-22 | Naoto Matsumoto | System for controlling vending machine |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100440148C (zh) * | 2005-08-24 | 2008-12-03 | 松下电器产业株式会社 | 信息处理设备及在其非易失性存储器中写入数据的方法 |
Also Published As
Publication number | Publication date |
---|---|
JP2004030539A (ja) | 2004-01-29 |
CN100409192C (zh) | 2008-08-06 |
CN1666181A (zh) | 2005-09-07 |
EP1519270A4 (en) | 2008-03-19 |
US20060190421A1 (en) | 2006-08-24 |
KR100945994B1 (ko) | 2010-03-09 |
EP1519270A1 (en) | 2005-03-30 |
KR20050013577A (ko) | 2005-02-04 |
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