Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • G06F13/38—Information transfer, e.g. on bus
  • G06F13/40—Bus structure
  • G06F13/4063—Device-to-bus coupling
  • G06F13/4068—Electrical coupling
  • G06F13/4086—Bus impedance matching, e.g. termination
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
  • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
  • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

• the present invention is directed generally to data communication. More particularly, the present invention relates to methods and arrangements for reducing power consumed at the terminating end of a parallel data communication circuit.
• a typical system might include a number of modules that interface to and communicate over a parallel data communication line (sometimes referred to as a data channel); for example, in the form of a cable, a backplane circuit, a bus structure internal to a chip, other interconnect, or any combination of such communication media.
• a sending module would transmit data over the bus synchronously with a clock on the sending module. In this manner, the transitions over the parallel signal lines leave the sending module in a synchronous relationship with each other and/or to the clock on the sending module.
• the parallel data interconnect At the other end of the parallel data interconnect, the data is received along with a clock signal; the receive clock is typically derived from or is synchronous with the clock on the sending module.
• the rate at which the data is passed over the parallel signal lines is sometimes referred to as the (parallel) "bus rate.”
• the voltage-biased termination minimizes discontinuities at communication-media junctions as can occur with most high-frequency signaling implementations, and also provides an appropriate signal level when the parallel communication bus is idle. Because these goals are directed to preserving signal integrity for the overall communication process, many industry recommendations include specific requirements for the type and location of the termination.
• bus terminations are typically implemented to draw power.
• SST_2 signaling described in EIA/JEDEC Standard STUB Series Terminated Logic For 2.5 Volts (SSTL_2) EIA/JESD8-9 suggests a biased termination that would be typically implemented using a resistor for each bus line, with one resistor end connected to the bus line and the other end connected to a voltage-reference node.
• SSTL_2 EIA/JEDEC Standard STUB Series Terminated Logic For 2.5 Volts
• EMI electromagnetic interference
• improving data communication over parallel busses permits more practicable and higher-speed parallel bussing applications which, in turn, can directly lead to higher-powered, higher-functioning circuits that preserve data integrity and are sensitive to needs for reducing implementation space and power consumption.
• an example embodiment of the present invention significantly decreases power consumed for the parallel data transmission while maintaining data integrity.
• the present invention reduces power consumption at the receiving module and thereby reduces EMI and reduces the number of power pins (or, more generally, power nodes) required for the parallel data communication.
• the need for a power-termination switching circuit is avoided and certain implementations of the invention improve communication efficiency and integrity.
• One embodiment of the present invention is directed to a parallel data communication arrangement in which digital data is transferred in parallel from a first module to a second module over a communication channel including a plurality of parallel data-carrying lines.
• a termination circuit is located at the second module, and the termination of the parallel data-carrying lines at the second module is provided by resistive coupling to each of the parallel data-carrying lines and therefrom, providing a reference voltage using the data on the parallel data-carrying lines.
• the data is sent over the parallel data-carrying lines with the data encoded to include approximately the same number of logical ones and logical zeroes, so that the reference voltage is substantially biased at a stable voltage level by the data on the parallel data-carrying lines.
• each of the parallel data-carrying lines is connected to one of two inputs of a differential receiver at the second module.
• the other input of the differential receiver is maintained at a reference voltage set midway between the respective voltage levels defining the logical ones and logical zeroes.
• this reference voltage can be defined at a very precise stable level by using the parallel data-carrying lines to define the reference voltage and ensuring that the number of logical ones and logical zeroes is always the same.
• Yet another particular example embodiment involves a parallel data communication arrangement in which digital data is transferred in parallel over a communication channel to a receiving module having termination at each end of the parallel bus' data lines.
• the termination circuit reduces power consumption at the receiving module by using resistive circuits respectively coupled to selected parallel data-carrying lines.
• the other ends of the resistive circuits are interconnected to provide a reference voltage using the data on the parallel data-carrying lines.
• the communication approach uses data sets encoded so that each data set includes the same number of ones and zeroes; in this manner the reference voltage is always at midpoint and useful in providing definition to the data-carrying lines without requiring a power termination circuit.
• Other example embodiments of the present invention are respectively directed to the encoding, decoding and system-processing aspects of such interfaces.
• Fig. 1 is a diagram of a parallel data communication arrangement in which digital data is transferred in parallel from a first module to a second module over a communication channel including a plurality of parallel data-carrying lines terminating at the second module, according to the present invention
• Fig. 2 is a diagram of another parallel data communication line arrangement, according to an example implementation of the present invention, that can incorporate the arrangement of Fig. 1.
• the present invention is believed to be generally applicable to methods and arrangements for transferring data between two modules (functional blocks) intercoupled by a parallel data communication path.
• the invention has been found to be particularly advantageous for high-speed data transfer applications requiring or benefiting from reductions in circuit-implementation space and power consumption. Examples of such applications include, among others, SSTL (stub series transceiver/terminated logic), RSL (Rambus Signaling Logic) interfaces, closely-connected applications such as where the parallel data communication path intercouples the two modules on a single-chip, off-board high-speed communication between chips typically situated immediately adjacent each other on the same printed circuit board such as on a reference-chip development platform of the type disclosed in U.S. Patent Application Serial No.
• a parallel data communication arrangement passes digital data on a parallel data bus between a pair of circuit modules.
• the data is coded so that the number of ones and the number of zeroes in each transmitted data set is at least approximately (i.e., almost or exactly) the same.
• a termination circuit located at the receiving module, is used to resistively couple each of the bus' data lines to a common node.
• the resistively-coupled data lines can be used to maintain the common node at a reference voltage.
• This reference voltage can then be used to provide a bias for the bus lines even when the bus is not active.
• the encoding is implemented so that the number of ones and the number of zeroes in each transmitted data set is exactly the same for all data transmitted over the parallel bus. Examples of such balanced coding are provided in the above-mentioned patent document entitled, "Parallel Communication Based On Balanced Data-Bit Encoding" (VLSI.295PA). This approach assures that the reference voltage, as defined at the common node, does not fluctuate.
• This stable voltage can be achieved by using the parallel data-carrying lines to define the reference voltage and ensuring that the number of logical ones and logical zeroes is always the same.
• the common node can be resistively coupled to each of the parallel data- carrying lines.
• this approach is highly advantageous for applications in which the logic sign of the data received via the parallel data-carrying lines is sensed using a differential receiver having its other input maintained at the reference voltage set midway between the respective voltage levels defining the logical ones and logical zeroes.
• the encoding is implemented so that the number of ones and the number of zeroes in each transmitted data set is at least approximately the same for all data transmitted over the parallel bus.
• Examples of such coding are readily obtained by varying the balanced coding approaches to include additional or alternative codes that slightly imbalance the ration of zeroes to ones. This approach is useful, for example, where more codes are needed or where the number of data lines is odd.
• Fig. 1 illustrates another example embodiment of the present invention in which a clock is used to define the rate at which the data is synchronously passed between a transmit module 110 and a receive module 112.
• each of the modules 110 and 112 being part of a respective communication node that includes the reciprocal set of transmit and receive modules.
• the embodiment shown in Fig. 1 is a differential clock, using two lines 1 16 and 118 to pass the differential clock signal for synchronous communication of data passed on the associated data-carrying bit lines (120, 121, 122, etc.) of the parallel bus.
• the communication channel between the transmit module 110 and the receive module 112 includes a total of N lines, where N equals two more than the number of associated data- carrying bit lines.
• each RT should equal the board impedance.
• R T should be selected at 50 Ohms and with 1% precision.
• the resistance value of R T is set equal to the calculated line impedance.
• V T the side of the resistance opposite the bus line is the common node denoted V T in Fig. 1.
• the capacitors 140, 142, and 144 in Fig. 1 are conventional for such termination.
• the capacitors 140 and 142 are used between the common node and ground for the 18 bus lines sharing a common node and the capacitor 144 is used between the generated reference voltage (at node 148) and ground, with each capacitor being equal to 0.1 ⁇ Farads.
• each termination resistor is located within 0.5 inch before the ball on the receiving package and not greater than 0.5 inch from the connecting data line.
• each termination resistor is located within 2 inches after the ball on the receiving package and not greater than 0.5 inch from the connecting data line with the common node effectively defining the end of each data line.
• Various approaches to the arrangement shown in Fig. 1 are advantageous in terms of power savings.
• none of the data-carrying bus lines require a termination power supply. It will be appreciated that such a midpoint level is self adjusted by the aggregate voltage levels of the data on the data-carrying bus lines.
• Fig. 2 illustrates a parallel-data communication line arrangement 210, according to another example implementation of the present invention.
• the arrangement passes 210 uses a data- value encoding approach in which data values are encoded by circuit 211 and then passed, from a sending module 212 to a receiving module 214, using parallel data lines 216 and 218 along with clock lines 222.
• the clock lines 222 provide the data-communication rate and synchronization between sending and receiving modules 212 and 214.
• a processor or other decode circuit 230 uses a reciprocal algorithm, lookup table or equivalent circuit to decode the data value back to its 6-bit data value.
• the arrangement 210 is directed to an application involving 6-bit code (“6b") groups, 8-bit code (“8b”) groups, and 12-bit data clock (12b DC) groups.
• the 12b DC groups efficiently encode communications of data or commands of 12 signals. In some cases, it may be advantageous to use smaller groups.
• a 12b DC group includes a differential clock pair and two 6b8b encodes, for a total of 18 pins between the sending module 212 and the receiving module 214.
• One half of the 12b DC group includes one 6b8b encoder and a differential clock pair, for a total of 10 pins.
• Un-encoded differential pairs can also be used to transport signals. These differential pairs can share the clock signal used with one half of a 12b DC group, or the differential pairs can have their own clock pair.
• each of the bus lines is terminated as shown in Fig. 1.
• the common-node voltage VT does not require a power supply
• the common-node voltage V T is naturally centered between the high and low voltage outputs of the transmit module
• power consumption is minimized when the outputs are disconnected or inoperative
• a very low power idle state is provided when all outputs are driven to zero.
• the present invention should not be considered limited to the particular examples described above.
• Various modifications, equivalent processes, as well as numerous structures to which the present invention may be applicable fall within the scope of the present invention such as multi-chip or single-chip arrangements that can be implemented using a similarly constructed one-way or two-way interface for communication between the chip-set arrangements.
• the precision of the termination can vary and is dependent on the specified design; for example, in an 8b- 1 Ob encoded bus application (8b- 1 Ob being common in the serial Ethernet arrangements), some codes are not balanced. Such variations may be considered as part of the claimed invention, as fairly set forth in the appended claims.

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• Engineering & Computer Science (AREA)
• General Engineering & Computer Science (AREA)
• Theoretical Computer Science (AREA)
• Computer Hardware Design (AREA)
• Physics & Mathematics (AREA)
• General Physics & Mathematics (AREA)
• Dc Digital Transmission (AREA)
• Logic Circuits (AREA)
• Power Sources (AREA)

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• 2001
  • 2001-05-31 US US09/871,160 patent/US6859883B2/en not_active Expired - Lifetime
• 2002
  • 2002-05-28 WO PCT/IB2002/001918 patent/WO2003107194A2/en not_active Ceased
  • 2002-05-28 EP EP02733069A patent/EP1407366B1/en not_active Expired - Lifetime
  • 2002-05-28 DE DE60215175T patent/DE60215175T2/de not_active Expired - Lifetime
  • 2002-05-28 JP JP2004513944A patent/JP2005520458A/ja active Pending

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