WO2003073519A1 - Diode emettrice de lumiere - Google Patents

Diode emettrice de lumiere Download PDF

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Publication number
WO2003073519A1
WO2003073519A1 PCT/JP2003/001359 JP0301359W WO03073519A1 WO 2003073519 A1 WO2003073519 A1 WO 2003073519A1 JP 0301359 W JP0301359 W JP 0301359W WO 03073519 A1 WO03073519 A1 WO 03073519A1
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WO
WIPO (PCT)
Prior art keywords
layer
current
type
light emitting
emitting diode
Prior art date
Application number
PCT/JP2003/001359
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English (en)
Japanese (ja)
Inventor
Masanobu Takahashi
Masato Yamada
Original Assignee
Shin-Etsu Handotai Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shin-Etsu Handotai Co., Ltd. filed Critical Shin-Etsu Handotai Co., Ltd.
Publication of WO2003073519A1 publication Critical patent/WO2003073519A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H01L33/145—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure

Definitions

  • the present invention relates to a light emitting diode.
  • a light emitting diode generally has a light emitting layer portion and a conductive electrode for applying a light emission drive voltage to the light emitting layer portion. Then, in order to improve the light extraction efficiency, a current diffusion layer and a current blocking layer may be formed between the light emitting layer portion and the current-carrying electrode.
  • FIG. 4 shows an example of a light emitting diode 23 having a current diffusion layer and a current blocking layer.
  • the light emitting layer 19 has a double-headed junction structure composed of an n-type cladding layer 13, an active layer 14, and a p-type cladding layer 15 on the n-type single crystal substrate 12 in this order.
  • a p-type current diffusion layer 16 is formed between the p-type cladding layer 15 and the current-carrying electrode 17 via an n-type buffer layer 21. Further, an ⁇ -type current blocking layer 18 is formed between the current spreading layer 16 and the p-type cladding layer 15.
  • the current is diffused so as to be uniformly supplied to the light emitting layer portion 19 in the plane. Therefore, relatively intense light is emitted even from a region of the light emitting layer portion 19 that is not covered by the current-carrying electrode 17.
  • the ⁇ -type current blocking layer 18 has a different conductivity type from the ⁇ -type current diffusion layer 16 and the ⁇ -type cladding layer 15, as shown in FIG. In order to avoid this, the energizing current flows to the area of the light emitting layer portion 19 that is not covered by the energizing electrode 17, and the light emission from the area that is not covered by the energizing electrode 17 is preferentially performed. Since light emission from the region is not easily blocked by the current-carrying electrode 17 and is easily extracted to the outside, the ⁇ -type current diffusion layer 16 and the ⁇ -type current blocking layer 18 are combined. 9
  • FIG. 5 shows an example of a method for manufacturing the light emitting diode 23.
  • G a A or the like on the n-type single-crystalline substrate 1 2 made by s (A 1 u G a! _ U) o. 5X I n 0. 49 P ( where, 0 ⁇ u ⁇ 1) at a mixed crystal comprising n-type clad layer 1 3, (A 1 V G a x _ v) o. 51 I n 0. 49 P ( However, 0 ⁇ v ⁇ 0.
  • the A1 compositions u, v, and w of the A1GaInP layers constituting the light-emitting layer section 19 satisfy the relationship of v ⁇ u and v ⁇ w.
  • the light emitting diode 23 is obtained.
  • the n-type dopant diffuses from the n-type current blocking layer 18 into a part of the p-type cladding layer 15, for example.
  • majority carriers (holes) in the p-type cladding layer 15 are compensated, and the carrier concentration is reduced, so that the brightness of the light emitting diode 23 is reduced.
  • the n-type inversion layer 15a is formed on the p-type cladding layer 15, and the light emission driving voltage for causing the light emitting diode 23 to emit light increases. Therefore, the desired luminous efficacy In order to obtain a light emitting diode having a high efficiency and a light emitting drive voltage, it is necessary to take measures for forming the n-type current blocking layer 18 so that the formation of the n-type inversion layer 15a is not remarkable. Leads to a decline.
  • the present invention has been made in view of the above problems, and an object of the present invention is to provide a light emitting diode capable of controlling a current flow in a current diffusion layer without forming a current blocking layer having a different conductivity type from the surroundings. Make it an issue. Disclosure of the invention
  • a current diffusion layer is formed between a current-carrying electrode and a light-emitting layer portion, and a current suppression layer that prevents a current flow based on a light-emitting drive voltage. They are of the same conductivity type and form a hetero barrier interface with the current diffusion layer.
  • the conduction type of the current suppression layer and the current diffusion layer are the same, and instead of forming a current blocking layer having a different conduction type from the surroundings, a gap is formed between the current suppression layer and the current diffusion layer.
  • a barrier interface By forming a barrier interface, it is intended to function as a current suppression layer. Since a layer having a different conductivity type from that of the surroundings is not used as the configuration of the current suppressing layer, the dopant is diffused into a layer below the current suppressing layer during the formation of the current suppressing layer, and the carrier concentration in the lower layer is reduced. An undesirable inversion layer is not formed.
  • the luminance of the light emitting diode does not decrease and the light emitting drive voltage does not increase due to the decrease in the carrier concentration or the formation of the inversion layer. Therefore, no special measures are required to prevent the formation of the inversion layer, and the production is easy.
  • the current suppression layer forms a hetero barrier interface at the boundary with the current diffusion layer. Thereby, in the current flowing through the current diffusion layer, at the portion where the current diffusion layer and the current suppressing layer are in contact, the current barrier and the light emitting layer portion are formed due to the energy barrier formed at the interface with the metal barrier. The flow of the conduction current between and is hindered near the current suppression layer.
  • the current flowing in the current spreading layer can be controlled and spread even if the current suppressing layer has the same conductivity type as the current spreading layer, and the function of the current suppressing layer is as follows. It can be fully demonstrated.
  • the current suppressing layer has a shape corresponding to the current-carrying electrode, and is preferably formed immediately below the current-carrying electrode.
  • FIG. 1 is a conceptual diagram showing the structure of a light emitting diode of the present invention.
  • FIG. 2A is a diagram illustrating an example of an energy band near a current suppression layer.
  • FIG. 2B is a diagram showing an example of an energy band in the vicinity of the current suppression layer, similarly.
  • FIG. 3 is a diagram illustrating a method for manufacturing a light emitting diode of the present invention.
  • Fig. 4 is a conceptual diagram showing the structure of a conventional light emitting diode.
  • FIG. 5 is a diagram illustrating a conventional method for manufacturing a light emitting diode.
  • FIG. 6 is a diagram illustrating a problem in a conventional light emitting diode. BEST MODE FOR CARRYING OUT THE INVENTION
  • FIG. 1 is a conceptual diagram showing a light emitting diode 1 according to one embodiment of the present invention.
  • the light emitting diode 1 has a current-carrying electrode 7 formed substantially at the center of the surface. Further, an n-type buffer layer 11 is formed on the n-type single crystal substrate 2, and a light-emitting layer section 9, a current suppressing layer 8, and a current diffusion layer 6 are further laminated thereon in this order.
  • the light emitting layer portion 9 includes a p-type cladding layer 5 as a first conductivity type cladding layer, an active layer 4 and a second
  • An n-type clad layer 3 as a conductive type clad layer has a double-headed junction structure in which the n-type clad layer 3 is laminated in this order, and a current suppressing layer 8 is in contact with a p-type clad layer 5 as a first conductive type clad layer. It is formed.
  • a back surface electrode 10 is formed on the back surface of the n-type single crystal substrate 2.
  • the thickness of the current diffusion layer 6 is preferably set in the range of 2 ⁇ to 15 ⁇ . If it is less than 2 ⁇ , it is not preferable because the current cannot be sufficiently diffused from the current-carrying electrode 7 to the light-emitting layer 9. On the other hand, if it exceeds 15 ⁇ , the above effect is only saturated, and it takes a long time to manufacture and increases the manufacturing cost.
  • the current suppression layer 8 is of the same conductivity type as the ⁇ -type cladding layer 5 and the ⁇ -type current diffusion layer 6, and is ⁇ -type in the present embodiment (hereinafter also referred to as ⁇ -type current suppression layer 8). Do).
  • the ⁇ -type single crystal substrate 2 and the ⁇ -type buffer layer 11 of the light-emitting diode 1 are composed of GaAs.
  • 0 ⁇ v ⁇ 0 7, v ⁇ u, v ⁇ w) active layer 4 is composed of, and. (A l w G ai - w) 0.
  • a p-type cladding layer 5 composed of 0 ⁇ w ⁇ l
  • a p-type current spreading layer 6 are arranged as A l x G ai — x A s (where 0 ⁇ 1).
  • the p-type current suppression layer 8 is composed of (A l y G ai — y ) 2 In n ⁇ _ ⁇ ⁇ (where 0 ⁇ y ⁇ l, 0 ⁇ z ⁇ 1, w ⁇ y). ing. If such a compound semiconductor is used in each layer, a large heterobarrier interface is formed between the p-type current diffusion layer 6 and the p-type current suppression layer 8 by forming the p-type current suppression layer 8.
  • p-type current suppressing layer 8 A l z l ni - Z P ( However, 0 ⁇ z ⁇ 1) it is preferable to constitute at.
  • no inversion layer is formed between the p-type cladding layer 5 and the p-type current suppression layer 8.
  • the current-carrying electrode 7 and the light-emitting layer 9 Since the conduction current hardly conducts in the region where the p-type current suppression layer 8 is disposed, it is possible to control the flow of the conduction current by changing the shape of the current suppression layer and its forming position. it can.
  • the p-type current suppression layer 8 is formed in a shape corresponding to the current-carrying electrode 7 and formed in a region directly below the current-carrying electrode 7, strong light emission is extracted from a region other than the current-carrying electrode 7, thereby improving light extraction efficiency I do. Further, by changing the composition of the active layer 4, the emission wavelength can be appropriately changed between 550 and 660 nm.
  • the band structure near the hetero-barrier interface formed between the P-type current diffusion layer 6 and the P-type current suppression layer 8 is, for example, as shown in FIG. 2A.
  • the energy at the upper end of the valence band of the p-type current suppression layer 8 is lower than the energy at the upper end of the valence band of the p-type current diffusion layer 6. Due to this, a large energy barrier E for holes is formed at the interface between the p-type current diffusion layer 6 and the p-type current suppression layer 8 to form a hetero-barrier interface.
  • the p-type cladding layer 5 and the p-type current diffusion layer 6 are in direct contact. Therefore, as shown in FIG. 2B, when current conduction in a region where the p-type current suppression layer 8 is not formed is taken into consideration, a barrier against holes is formed in the p-type cladding layer 5 from the p-type current diffusion layer 6. It is better not to cause it.
  • the energy at the upper end of the valence band of the p-type cladding layer 5 is substantially equal to the energy at the upper end of the valence band of the p-type current spreading layer 6, or the valence of the P-type cladding layer 5
  • the energy at the upper end of the electron band is preferably set higher than the energy at the upper end of the valence band of the p-type current diffusion layer 6.
  • the band gap energy E g2 of the P-type current suppressing layer 8 is changed to the band gap energy E g 1 of the ⁇ -type current diffusion layer 6 and the p-type cladding layer.
  • a method of setting the bandgap energy Eg3 larger than 5 can be exemplified. It is necessary to adjust the composition of each layer so as to satisfy the condition. With such a configuration, the boundary between the p-type current suppressing layer 6 and the p-type current spreading layer 8 can be a hetero-barrier interface, and the current can be reduced without forming a layer having a different conductivity type. The function as the suppression layer 6 can be achieved.
  • p-type current suppressing layer 8 ((A 1 y G a !
  • a 1 Composition in the (yz) is increased, and P-type current diffusion layer 6 (A 1 X G in the child small a 1 composition (x) in a i_ x a s), it is possible to increase the hetero barrier for holes to be formed between the p-type current suppressing layer 8 and the p-type current diffusion layer 6.
  • the P-type current suppressing layer 8 it is preferable to use a layer having a thickness such that carriers (holes) from the p-type current diffusion layer 6 do not pass through the light emitting layer 9 due to a tunnel phenomenon. More specifically, it is preferable to set the distance to 0.05 m or more and 1 or less. If the thickness is less than 0.05 ⁇ m, the carrier will pass through due to the tunnel phenomenon, which is not preferable. Costs rise. .
  • an n-type GaAs buffer layer 11 is formed on the first main surface of an n-type GaAs single-crystal substrate 2, which is a compound semiconductor single-crystal substrate lattice-matched with an AlGaInP mixed crystal. For example, 0.5 ⁇ m epitaxial growth.
  • an 11-type 1 GaInP cladding layer 3 of 1111, a non-doped A1GaInP active layer 4 of 0.6 im, and a type 1 GaIn The P cladding layer 5 is epitaxially grown in this order.
  • Group II elements such as Mg and Zn can be used as the p-type dopant
  • Si can be used in addition to group VI elements such as S and Se.
  • Epitaxial growth of each of these layers is performed by metalorganic vapor phase epitaxy.
  • MOVPE Metalorganic Vapor Phase Epitaxy
  • MBE molecular beam epitaxy
  • the p-type current suppression layer 8 is formed by the method shown in FIG. That is, on the entire surface of the p-type cladding layer 5, the p-type current suppression layer 8 made of A1GaInP is epitaxially grown. Thereafter, an extra region 8a is removed by photolithography so that only a desired region remains (in the present embodiment, only a region immediately below the current-carrying electrode 7). After that, the p-type current diffusion layer 6 made of A1GaAs is epitaxially grown, and then the current-carrying electrode 7 is formed immediately above the p-type current suppression layer 8 to form an element. Diode 1 can be obtained.
  • the p-type A 1 GaInP current suppressing layer 8 is formed between the p-type A 1 GaInP current suppressing layer 8 and the p-type A 1 A barrier.
  • the majority carriers (holes) in the p-type cladding layer 5 are not compensated, and the majority carrier (hole) concentration in the p-type cladding layer 5 must be maintained at an intended level.
  • the light emitting diode 1 having good luminous efficiency can be obtained.
  • the inversion layer is not formed, the light emission driving voltage does not increase.
  • the case where the p-type current suppression layer 8 and the p-type current diffusion layer 6 are formed on the p-type cladding layer 5 has been described. Has the same effect. Furthermore, the current suppressing layer 8 is formed in contact with the p-type cladding layer 5 only on the surface of the p-type cladding layer 5 and immediately below the current-carrying electrode 7, but the present invention is not limited to this.
  • the current suppressing layer 8 may be formed so as to be included in the current diffusion layer 6 or may be formed in a region other than the region immediately below the current-carrying electrode 7.

Abstract

L'invention concerne une diode (1) émettrice de lumière comprenant une unité de couche (9) émettrice de lumière, une électrode d'électrification (7) et une couche de diffusion (6) de courant, une couche de restriction (8) de courant étant en couches dans l'ordre précité entre l'électrode d'électrification (7) et l'unité de couche (9) émettrice de lumière. L'unité de couche (9) émettrice de lumière possède une structure d'hétéro-jonction double formée par stratification d'une couche gaine (5) de type p, d'une couche active (4) et d'une couche gaine (3) de type n dans l'ordre mentionné à partir du côté de l'électrode d'électrification (7). La couche de restriction (8) de courant présente une forme correspondant à l'électrode (7) et est formée directement en-dessous de ladite électrode (7) via la couche de diffusion (6) de courant. La couche de restriction (8) de courant est de type p et présente le même type conducteur que la couche gaine (5) de type p et la couche de diffusion (6) de courant, et forme une interface de barrière hétéro avec ladite couche de diffusion (6) de courant. En conséquence, l'invention permet de produire une diode émettrice de courant de fabrication facile possédant des couches de diffusion et de restriction de courant.
PCT/JP2003/001359 2002-02-28 2003-02-10 Diode emettrice de lumiere WO2003073519A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2002053729A JP2003258295A (ja) 2002-02-28 2002-02-28 発光ダイオード
JP2002-053729 2002-02-28

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160064603A1 (en) * 2014-08-26 2016-03-03 Toshiba Corporation Light Emitting Diodes With Current Confinement

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04212479A (ja) * 1990-08-20 1992-08-04 Toshiba Corp 半導体発光ダイオード
EP0727827A2 (fr) * 1995-02-15 1996-08-21 Mitsubishi Cable Industries, Ltd. Dispositif semi-conducteur émetteur de lumière
US20020020842A1 (en) * 2000-04-21 2002-02-21 Kazuaki Sasaki Semiconductor light-emitting device and method for manufacturing thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04212479A (ja) * 1990-08-20 1992-08-04 Toshiba Corp 半導体発光ダイオード
EP0727827A2 (fr) * 1995-02-15 1996-08-21 Mitsubishi Cable Industries, Ltd. Dispositif semi-conducteur émetteur de lumière
US20020020842A1 (en) * 2000-04-21 2002-02-21 Kazuaki Sasaki Semiconductor light-emitting device and method for manufacturing thereof

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JP2003258295A (ja) 2003-09-12
TW200306018A (en) 2003-11-01

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