WO2003069743A1 - Embase et dispositif a semiconducteur - Google Patents

Embase et dispositif a semiconducteur Download PDF

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Publication number
WO2003069743A1
WO2003069743A1 PCT/JP2002/012870 JP0212870W WO03069743A1 WO 2003069743 A1 WO2003069743 A1 WO 2003069743A1 JP 0212870 W JP0212870 W JP 0212870W WO 03069743 A1 WO03069743 A1 WO 03069743A1
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WO
WIPO (PCT)
Prior art keywords
solder
film
submount
thickness
semiconductor device
Prior art date
Application number
PCT/JP2002/012870
Other languages
English (en)
Japanese (ja)
Inventor
Makoto Imamura
Takashi Ishii
Teruo Amoh
Kenjiro Higaki
Akira Sasame
Yasushi Tsuzuki
Original Assignee
Sumitomo Electric Industries, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries, Ltd. filed Critical Sumitomo Electric Industries, Ltd.
Priority to AU2002349516A priority Critical patent/AU2002349516A1/en
Publication of WO2003069743A1 publication Critical patent/WO2003069743A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492—Bases or plates or solder therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
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    • H01L2924/01—Chemical elements
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    • H01L2924/01023—Vanadium [V]
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    • H01L2924/01024—Chromium [Cr]
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    • H01L2924/01029—Copper [Cu]
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    • H01L2924/01—Chemical elements
    • H01L2924/01049—Indium [In]
    • H—ELECTRICITY
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    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01073—Tantalum [Ta]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
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    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10329—Gallium arsenide [GaAs]
    • H—ELECTRICITY
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    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/022—Mountings; Housings
    • H01S5/0235—Method for mounting laser chips
    • H01S5/02355—Fixing laser chips on mounts
    • H01S5/0237—Fixing laser chips on mounts by soldering

Definitions

  • the present invention relates to a submount and a semiconductor device, and more particularly to a submount on which a semiconductor laser element is mounted and a semiconductor device using the submount.
  • FIG. 12 is a schematic cross-sectional view for explaining a conventional method of manufacturing a semiconductor device. A conventional method for manufacturing a semiconductor device will be described with reference to FIG.
  • a submount 103 for mounting a semiconductor laser element 102 is prepared.
  • the submount 103 is composed of a substrate 104 containing aluminum nitride (A 1 N), and a laminated film 105 (T ⁇ /) of a film containing titanium (T i) and a film containing platinum (Pt) formed on the substrate 104.
  • solder barrier film 107 It is composed of a solder barrier film 107 and a solder 108 formed on the solder barrier film 107 and containing gold (Au) tin (Sn) based solder.
  • the method for forming the TiZPt laminated films 105 and 11 106, the solder barrier film 107 and the solder 108 on the submount 103 is based on a conventional film forming method such as vapor deposition, sputtering or plating, and photolithography.
  • a pattern Jung method such as a lithography method or a metal mask method can be used.
  • the semiconductor laser element 102 is mounted at a predetermined position on the solder 10 as indicated by an arrow 114 while the solder 108 of the submount 103 is heated and melted. (Perform the die bond process ). Thereafter, the solder 108 is cooled and solidified. As a result, the laser element 102 is adhesively fixed on the submount 103 by the solder 108. Thereafter, by connecting and fixing the back surface of the submount 103 to a heat sink (not shown) by soldering or the like, a semiconductor device having a semiconductor laser element can be obtained.
  • the conventional semiconductor device manufactured by the process shown in FIG. 12 has the following problems. That is, when the semiconductor laser device 102 (see FIG.
  • FIG. 13 is a schematic sectional view for explaining a problem of the conventional semiconductor device.
  • a bottom-emitting semiconductor laser device 102 (see FIG. 13) having excellent heat dissipation properties has been used.
  • the laser beam oscillating part (light emitting part) is formed on the lower surface side of the semiconductor laser element 102 (the joint part with the solder 108 (see FIG. 13)).
  • the light emitting portion that generates heat closer to the submount 103 as described above, a semiconductor device having excellent heat radiation characteristics can be obtained. .
  • the present invention has been made to solve the above problems, and an object of the present invention is to provide a submount and a submount capable of preventing solder from rising onto an end face of a semiconductor laser device. An object of the present invention is to provide a semiconductor device using the submount.
  • the width WS and thickness d of the solder film may be determined so as to satisfy the relationship of (3 7 XW / 600—14 / 1 5) ⁇ d ⁇ 6. .
  • the submount may further include a solder barrier film formed between the submount substrate and the solder film.
  • a solder barrier film formed between the submount substrate and the solder film.
  • the submount includes an adhesion film formed between the submount substrate and the solder barrier film so as to be in contact with the surface of the submount substrate, a diffusion prevention film formed on the adhesion layer, and a diffusion prevention film. And an electrode film formed thereon, and the solder barrier film may be disposed on the electrode film.
  • the semiconductor element mounted on the solder film and the submount substrate can be reliably connected, the reliability of the semiconductor device using the submount can be improved.
  • the adhesion film may include titanium, the diffusion prevention film may include platinum, the electrode film may include gold, and the solder barrier film may include platinum.
  • the solder film may include a gold-tin solder.
  • the above-mentioned materials are particularly suitable when used as the materials of the respective films, so that the reliability of the submount can be effectively improved.
  • the submount substrate may include aluminum nitride.
  • the length of the solder film in the direction substantially perpendicular to the width WS of the solder film is LS
  • the length of the semiconductor device in the direction substantially perpendicular to the width WC of the semiconductor device is LC
  • L (LC-LS )
  • the length LS and the thickness d of the solder film may be determined so as to satisfy the relationship of ⁇ 8.
  • the semiconductor device includes the above submount and a semiconductor element mounted on a solder film of the submount, and the semiconductor element is a semiconductor laser element.
  • FIG. 1 is a schematic sectional view showing Embodiment 1 of a semiconductor device according to the present invention.
  • FIG. 2 is a schematic sectional view for explaining a method of manufacturing the semiconductor device shown in FIG.
  • FIG. 3 is a schematic diagram showing a planar shape of the laser element and the solder as viewed from the arrow 40 side in FIG.
  • Figure 4 shows a graph that shows the relationship between the evaluation value W or L and the solder thickness d. It is a figure showing a rough.
  • FIG. 5 is a schematic sectional view showing Embodiment 2 of the semiconductor device according to the present invention.
  • FIG. 6 is a schematic sectional view for explaining a method of manufacturing the semiconductor device shown in FIG.
  • FIG. 7 is a schematic sectional view showing Embodiment 3 of a semiconductor device according to the present invention.
  • FIG. 8 is a schematic sectional view showing Embodiment 4 of a semiconductor device according to the present invention.
  • FIG. 9 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device shown in FIG.
  • FIG. 10 is a schematic sectional view showing the structure of a sample of Example 1 of the semiconductor device according to the present invention.
  • FIG. 11 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device shown in FIG.
  • FIG. 12 is a schematic sectional view for explaining a conventional method for manufacturing a semiconductor device.
  • FIG. 13 is a schematic cross-sectional view for explaining a problem of the conventional semiconductor device.
  • FIG. 1 is a schematic sectional view showing Embodiment 1 of a semiconductor device according to the present invention.
  • First Embodiment A semiconductor device according to a first embodiment of the present invention will be described with reference to FIG.
  • the semiconductor device 1 has a structure in which a laser element 2 using a gallium arsenide (Ga As) semiconductor or the like is mounted on a submount 3.
  • a heat sink may be connected to the submount 3 on the side opposite to the surface on which the laser element 2 is mounted.
  • the submount 3 includes a substrate 4, a Ti / Pt laminated film 5 formed of a titanium (T i) film and platinum (Pt) formed on the upper surface of the substrate 4, and a T i ZP t A gold (Au) film 6 formed on the laminated film 5, a solder barrier film 7 formed on the Au film 6, a solder for bonding between the solder barrier film 7 and the laser element 2. 8 and from Become. On the upper surface of the Au film 6, a bonding pad portion 9 is formed in a region adjacent to the solder barrier film.
  • the width of the solder barrier film 7 is smaller than the width of the laser element 2.
  • the outer peripheral portion 10 of the solder 8 covers the upper surface and the end surface of the solder barrier film 7 and is in contact with the upper surface of the Au film 6.
  • the end face 11 of the outer periphery 10 of the solder 8 is inclined with respect to the surface of the Au film 6.
  • the width of the solder barrier film 7 and the width of the solder 8 are smaller than the width of the laser element 2, as can be seen from the manufacturing method described later. Therefore, it is possible to suppress the occurrence of a phenomenon that a part of the solder 8 rises on the end face of the laser element 2. For this reason, it is possible to suppress the occurrence of defects such as inability to oscillate laser light in the laser element 2 due to the rise of the solder 8.
  • ceramic, semiconductor, or metal may be used as the material of the substrate 4 forming the submount 3.
  • the ceramic material constituting the substrate 4 for example, aluminum nitride (A 1 N), acid I arsenide aluminum (A 1 2 0 3), carbide Kei element (S i C), nitride Kei element (S i 3 N 4 ) Those containing, as main components, etc. can be mentioned.
  • a semiconductor as a material forming the substrate 4 for example, silicon (Si) can be cited.
  • the metal constituting the substrate 4 for example, copper (Cu), tungsten (W), molybdenum (Mo), iron (Fe), alloys containing these, and composite materials may be used. it can.
  • the substrate 4 it is preferable to use a material having high thermal conductivity.
  • the thermal conductivity of the substrate 4 is preferably 10 OWZmK or more, and more preferably 17 OWZmK or more.
  • the thermal expansion coefficient of the substrate 4 is close to the thermal expansion coefficient of the material forming the laser element 2.
  • there are gallium arsenide (GaAs) -based and indium phosphide (InP) -based materials as materials for forming the laser element 2.
  • the thermal expansion coefficient of the substrate 4 is preferably 1 ⁇ 10— / ⁇ or less, more preferably 5 ⁇ 1 cr 6 ZK or less.
  • the submount 3 having excellent heat dissipation can be realized.
  • the through hole may be formed therein.
  • a high melting point metal particularly, tungsten (W) or molybdenum (Mo) can be preferably used.
  • the above-mentioned conductors include metal such as tungsten and molybdenum, as well as transition metals such as titanium (Ti), glass components, and the material of the base material forming the substrate 4 (for example, aluminum nitride (A1N) ) May be included.
  • the surface roughness of the substrate 4 is preferably 1 m or less in Ra, and more preferably 0.1 ⁇ or less in Ra.
  • the flatness of the substrate 4 is preferably 5 ⁇ or less, more preferably 1 ⁇ or less. If Ra exceeds 1 zm and the flatness exceeds 5 ⁇ , a gap is created between the submount 3 and the laser element 2 when the laser element 2 is joined, and the effect of cooling the laser element 2 is reduced. There is. Note that flatness refers to the magnitude of deviation of a planar feature from a geometrically correct plane, and is specified in the JIS standard (JIS B 0621).
  • the Ti film (the film containing titanium (T i)) constituting the Ti / Pt laminated film 5 is formed so as to be in contact with the upper surface of the substrate 4 and has good adhesion to the substrate 4. It is a so-called adhesion layer made of various materials.
  • the above-mentioned titanium (T i) furthermore, chromium (Cr), nickel chromium alloy (NiCr), tantalum (Ta), and compounds thereof are used. it can.
  • the platinum (Pt) film constituting the Ti / Pt laminated film 5 is a so-called diffusion prevention layer (diffusion prevention film) formed on the upper surface of the Ti film.
  • the material of the diffusion preventing layer include the above-mentioned platinum (Pt), palladium (Pd), nickel chromium alloy (NiCr), tungsten titanium (TiW), nickel (Ni), Molybdenum (Mo) can be used.
  • the Au film 6 is a so-called electrode Usually, a film mainly composed of Au is used.
  • the adhesion layer (adhesion film) and the diffusion prevention layer (diffusion prevention film) on the substrate 4 the reliability of the semiconductor device 1 using the submount 3 (see FIG. 1) is improved. be able to.
  • titanium is used as the material of the adhesion layer
  • platinum is used as the material of the diffusion prevention layer
  • gold is used as the material of the electrode layer (electrode film)
  • these materials are particularly suitable for the adhesion layer and the diffusion layer. Since it exhibits excellent characteristics as a prevention layer and an electrode layer, a highly reliable semiconductor device 1 (see FIG. 1) can be obtained.
  • solder barrier film 7 platinum (Pt), nickel chromium alloy (NiCr), nickel (Ni), or the like can be used.
  • the material of the solder 8 is gold tin (AuSn) solder, gold germanium (AuGe) solder, lead tin (PbSn) solder, indium tin (In Sn) solder, silver
  • An alloy solder such as a tin (AgSn) -based solder, or a laminate of these alloy solders or a metal constituting the above-described alloy solder can be used.
  • AuSn gold-tin
  • solder 8 the composition ratio of gold (Au) is 65% by mass to 85% by mass or gold (Au) is 5% by mass to 20% by mass. /. The following is preferred.
  • the above-described Ti / Pt laminated film 5, Au film 6, solder barrier film 7, and solder 8 are hereinafter also referred to as metallized layers.
  • a conventionally used film forming method can be appropriately used.
  • a thin film forming method such as an evaporation method or a sputtering method, or a plating method can be used.
  • a patterning method for forming the above-mentioned Tino Pt laminated film 5, Au film 6, solder barrier film 7, and solder 8 so as to have a predetermined pattern a photolithography method, a metal mask, and the like are used. Method can be used.
  • the thickness of the titanium (T i) film as the adhesion layer constituting the above-mentioned TiZPt laminated film 5 is preferably from 0.0111 to 1. ⁇ .
  • the thickness of the platinum (Pt) film as the diffusion preventing layer constituting the Ti / Pt laminated film 5 is preferably not less than 0.1 ⁇ and not more than 1.5 ⁇ .
  • the thickness of the Au film 6 as an electrode layer is preferably from 1 ⁇ to 1 O / m.
  • the thickness of the solder barrier film 7 is preferably 0.0 l / zm or more and 1.5 / zm or less.
  • the thickness of the solder 8 is preferably not more than 0.1 ⁇ m or less.
  • the laser element 2 may be a laser light emitting element using, for example, a GaAs-based semiconductor, an InP-based semiconductor, or a GaN-based semiconductor, that is, an IIIV compound semiconductor. Further, the laser element 2 may be either a top emission type or a bottom emission type.
  • a bottom-emitting laser element 2 (a method in which the light-emitting portion of the laser element 2 is formed on the side surface opposite to the joint between the laser element 2 and the solder 8) is used, the light emitting portion serving as a heat-generating portion is used. Since the portion is arranged closer to the substrate 4, the heat dissipation of the semiconductor device 1 can be improved.
  • a bottom-emission type laser element 2 is used, the probability of occurrence of a defect due to the rise of the solder 8 to the side face of the laser element 2, which has been cited as a conventional problem, is increased. Is particularly remarkable.
  • the surface of the laser element 2 metallized layer is formed such silicon oxide film (S i 0 2) insulating layer, such as and a gold (A u) electrode layer such. It is preferable that the thickness of the gold (Au) layer as the electrode layer is not less than 0.1 and not more than 10 ⁇ in order to ensure good wettability with the solder 8.
  • the semiconductor device shown in FIG. 1 may be connected to a heat sink using solder or the like. Specifically, after forming an adhesion layer or a diffusion prevention layer on the back surface of the substrate 4 opposite to the surface on which the Ti / Pt laminated film 5 is formed, a sheet is formed on the back surface of the substrate 4. A heat sink is arranged via a solder in a shape. The heat sink and the board 4 are connected and fixed by the solder arranged on the back side of the board 4.
  • the solder for joining the heat sink and the substrate 4 may be a sheet-like solder (solder foil) as described above, or may be arranged in advance on the surface of the heat sink. Good.
  • a solder layer may be formed on a metallized layer such as a diffusion preventing layer on the back surface of the substrate 4 in advance.
  • the laser element 2 and the heat sink are simultaneously bonded to the substrate 4.
  • metal or ceramic can be used as the material of the heat sink.
  • Metals that constitute the heat sink include, for example, copper (Cu), tungsten (W), molybdenum (Mo), iron (Fe) and these metals. Alloys and composites can be used.
  • the surface of the heat sink is preferably subjected to a surface treatment for forming a film containing nickel (Ni), gold (Au), and a metal containing these metals.
  • a vapor deposition method, a plating method, or the like can be used as a surface treatment method.
  • the heat conductivity of the heat sink is preferably high.
  • the heat conductivity of the heat sink is preferably 10 OWZmK or more.
  • FIG. 2 is a schematic sectional view for explaining a method of manufacturing the semiconductor device shown in FIG. A method for manufacturing the semiconductor device shown in FIG. 1 will be described with reference to FIG.
  • a submount 3 for mounting the laser element 2 is prepared.
  • the method for forming the TiZPt laminated film 5, the Au film 6, the solder barrier film 7, and the solder 8 on the submount 3 is based on conventional film forming methods such as vapor deposition, sputtering, or plating, and photolithography.
  • a pattern jungling method such as a lithography method or a metal mask method can be used.
  • the width WS of the solder 8 is smaller than the width WC of the laser element 2.
  • the thickness d of the solder 8 is determined so as to satisfy a predetermined condition described later.
  • the width WS of the solder 8 is smaller than the width WC of the laser element 2
  • the width of the solder barrier film 7 is the width WS of the solder 8 or the width WC of the laser element 2. It can be larger or smaller.
  • the laser element 2 is mounted on the solder 8 as shown by an arrow 14 in a state where the solder 8 is melted. Then, the solder 8 is cooled. Thus, the semiconductor device 1 as shown in FIG. 1 can be obtained.
  • FIG. 3 is a schematic diagram showing a planar shape of the laser element 2 and the solder 8 as viewed from the arrow 40 side in FIG.
  • the evaluation value W and the thickness d of the solder 8 satisfy the relationship shown in FIG. Figure 4 shows the relationship between the evaluation value W or L and the solder thickness d. It is a figure showing a graph showing a relation.
  • the point is located.
  • the evaluation value W ( ⁇ ⁇ ), the thickness d ( ⁇ ⁇ ) of the solder 8 and the power, and W —30 ⁇ 0.3 d ⁇ l,-30 m W ⁇
  • W —30 ⁇ 0.3 d ⁇ l,-30 m W ⁇
  • the width WS and thickness d of the solder 8 must be determined so as to satisfy the relationship 8 (the relationship where the above points are plotted in the area shown as area A in FIG. 4).
  • the evaluation value W (that is, the width WS of the solder 8 and the width WC of the laser element 2) and the thickness of the solder 8 are set so that the above-mentioned point is located in the area shown in the area B of FIG. d is determined.
  • the evaluation value W, the thickness d of the solder 8, and the force W 0.3 d ⁇ 0.3 ⁇ d 1, 1 10 m ⁇ W ⁇ 20 0 / xm 0.3 ⁇ d ⁇ (W / 1 4 + 1 2/7), if 20 um ⁇ W ⁇ 60 ⁇ (3 7 XWZ6 0 0 — 1 4/1 5) ⁇ d ⁇ (W / 1 4 + 1 2/7 ),
  • the width WS and the thickness d of the solder 8 are set to satisfy the relationship of (3 7 XW / 6 0 0-1 4/1 5) ⁇ d ⁇ 6 for 60 m and 80 m. It may be determined.
  • the bonding between the laser element 2 and the submount 3 by the solder 8 can be performed more reliably, and at the same time, the probability of occurrence of a defect caused by the rise of the molten solder 8 on the end face of the laser element 2 can be further reduced.
  • a semiconductor device 1 capable of reliably performing laser oscillation can be obtained.
  • the length of the solder 8 in the direction substantially perpendicular to the width WS of the solder 8 is LS, and the width of the laser element 2 in the direction substantially perpendicular to the width WC of the laser element 2.
  • the molten solder 8 can be prevented from flowing more than necessary to the end of the laser element 2 in the length LS direction of the solder 8. Therefore, it is possible to reduce the probability of occurrence of a defect that a part of the molten solder 8 goes up on the end face of the laser element 2 in the length direction of the solder 8. In addition, the bonding strength between the laser element 2 and the submount 3 is insufficient, and the probability of occurrence of defects due to an increase in thermal resistance between the laser element 2 and the submount 3 can be reduced.
  • the evaluation value L and the solder thickness d are determined so that the point determined by the evaluation value L and the solder thickness d is located within the area shown in the area B in FIG. Is done.
  • L ⁇ 80 ⁇ (37 XL / 6 00-14 / 15) ⁇ d ⁇ 6 the length of the solder 8 LS and The thickness d may be determined.
  • the laser element 2 and the submount 3 can be more reliably joined by the solder 8. Further, the probability of occurrence of a defect that a part of the melted solder 8 rises on the end face of the laser element 2 in the length direction of the solder 8 can be reduced more effectively. Further, the probability of occurrence of defects due to insufficient bonding strength between the laser element 2 and the submount 3 and an increase in thermal resistance between the laser element 2 and the submount 3 can be further reduced.
  • FIG. 5 is a schematic sectional view showing Embodiment 2 of the semiconductor device according to the present invention.
  • the reference numerals in FIG. 5 correspond to those in FIG. Second Embodiment A semiconductor device according to a second embodiment of the present invention will be described with reference to FIG.
  • the semiconductor device 1 has basically the same structure as the semiconductor device shown in FIG. 1, but the ratio of the size (width) of the laser element 2 to the solder barrier film 7 and the solder 8 is small. It is different from the semiconductor device shown in FIG. That is, the laser element 2, the solder barrier film 7, and the solder 8 are configured to have widths substantially equal to each other.
  • FIG. 6 is a schematic sectional view for explaining a method of manufacturing the semiconductor device shown in FIG. With reference to FIG. 6, a method of manufacturing the semiconductor device shown in FIG. 5 will be described.
  • the width WS of the solder 8 and the width WC of the laser element 2 are equal. Then, at this time, the thickness d of the solder 8 is determined such that a point whose position is determined by the evaluation value W and the value of the thickness d is plotted in the area A of the graph shown in FIG. Specifically, the thickness d of the solder 8 has a value in a range from 0.3 ⁇ to 2.9 m. More preferably, the thickness d of the solder 8 is not less than 0.3 ⁇ and not more than 1 so that the above point is plotted in the region B in FIG. Even in this case, the same effect as that of the semiconductor device according to the first embodiment of the present invention can be obtained. (Embodiment 3)
  • FIG. 7 is a schematic sectional view showing Embodiment 3 of a semiconductor device according to the present invention.
  • the reference numerals in FIG. 7 correspond to those in FIG. Third Embodiment A semiconductor device according to a third embodiment of the present invention will be described with reference to FIG.
  • the semiconductor device 1 basically has the same structure as the semiconductor device shown in FIG. 1, but the width WS of the solder barrier film 7 and the solder 8 is wider than the width WC of the laser element 2.
  • the thickness of the solder 8 is relatively thinner than the thickness of the solder 8 of the semiconductor device shown in FIG. That is, the evaluation value W determined from the thickness d of the solder 8 before mounting the laser element 2 on the submount 3 (see FIG. 6), the width WS of the solder 8 and the width WC of the laser element 2
  • the relationship shown in Fig. 4 satisfies the relationship plotted inside the area A of the graph, more preferably inside the area B, as shown in Fig.
  • the width WS of the solder 8 is It may be wider than 2 WC.
  • the value of the width WS of the solder 8 must be equal to or less than the width of the laser element 2 (WC + 60; xm). Also in this case, it is possible to suppress the solder 8 from rising onto the end face of the laser element 2 as in the first embodiment of the present invention.
  • FIG. 8 is a schematic sectional view showing Embodiment 4 of a semiconductor device according to the present invention.
  • the reference numerals in FIG. 8 correspond to those in FIG. Fourth Embodiment A semiconductor device according to a fourth embodiment of the present invention will be described with reference to FIG.
  • semiconductor device 1 basically has the same structure as the semiconductor device shown in FIG. 1, but the thickness of solder 8 is relatively thinner than that of the semiconductor device shown in FIG. I'm wearing Also in this case, as long as the relationship between the evaluation value W shown in FIG. 4 and the thickness d of the solder 8 (see FIG. 4) is satisfied, like the semiconductor device shown in FIG. The solder 8 can be prevented from rising.
  • FIG. 9 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device shown in FIG.
  • the thickness of the solder 8 is thinner than the thickness of the solder 8 shown in FIG. 1, so that the end of the solder 8 is attached to the end of the lower surface of the laser element 2. Has not reached. Therefore, it is possible to more reliably prevent the solder 8 from rising onto the end face of the laser element 2.
  • Examples of the present invention and samples of Comparative Examples were prepared, and solder bumps occurred on the side wall surface of the laser element for each sample. An appearance inspection was conducted to visually confirm whether or not each sample was emitted, and a luminescence inspection was performed to confirm whether each sample emitted laser light normally.
  • FIG. 10 is a schematic cross-sectional view showing a configuration of a sample of Example 1 of a semiconductor device according to the present invention.
  • FIG. 11 is a schematic cross-sectional view for explaining a method of manufacturing the semiconductor device shown in FIG.
  • the semiconductor device 1 has a structure in which a submount 3 on which a laser element 2 is mounted is connected to a heat sink 22.
  • a titanium (T i) film 18 as an adhesion layer is formed on the upper surface of the substrate 4 made of an aluminum nitride (A 1 N) sintered body.
  • the size of the substrate 4 is, for example, 1.2 mm in width, 1.5 mm in length, and 0.3 mm in thickness.
  • the thickness of the Ti film 18 is 0.1 ⁇ .
  • a platinum ( ⁇ t) film 19 is formed as a diffusion preventing layer. ? 1;
  • the thickness of the film 19 is 0.2 ⁇ ⁇ .
  • the Ti film 18 and the Pt film 19 form the Ti / Pt laminated film 5.
  • an Au film 6 as an electrode layer is formed on this Pt film 19.
  • the thickness of the Au film 6 is 0.6 xm.
  • a solder barrier film 7 made of platinum (Pt) is formed on the upper surface of the Au film 6.
  • the width of the solder barrier film 7 is smaller than the width of the laser element 2 and the thickness of the solder 8 is sufficiently large, as shown in FIG. It may cover and contact the upper surface of the Au film 6.
  • the width of the laser element 2 was 0.3 mm and the length was 1. Omm.
  • the width is 0.6 mm and the length is 1.3 mm.
  • the width and length of the solder 8 are appropriately changed for each sample as shown in Table 2 described later. ing.
  • the width and length of the solder barrier film 7 were the same as the width and length of the solder 8 for each sample.
  • solder barrier film 7 On the solder barrier film 7, a solder 8 is disposed. The thickness and the planar shape of the solder 8 are appropriately changed depending on the sample as described later.
  • the laser element 2 is bonded and fixed to the submount 3 by solder 8.
  • As the laser element 2 a semiconductor laser element using a GaAs chip is used.
  • a TiZPt / Au laminated film 20 is formed on a lower surface opposite to the upper surface on which the Ti film 18 is formed. Specifically, a 0.1 ⁇ thick titanium (Ti) film is formed on the lower surface of the substrate 4, and a 0.2 ⁇ thick platinum (Pt) film is formed on the Ti film. Then, a gold (Au) film having a thickness of 6 ⁇ m is formed on the Pt film.
  • the solder 21 is arranged on the surface of the TiZPt / Au laminated film 20 opposite to the surface facing the substrate 4 (on the Au film). Below the submount 3, a heat sink 22 is disposed via solder 21. The size of the heat sink 22 is 2 mm in width, 6 mm in length, and 1.5 mm in thickness. The solder 21 is used for bonding and fixing the heat sink 22 and the submount 3.
  • a copper tungsten (CuW) alloy is used as a material of the heat sink 22 .
  • a laser element 2 a laser element using a gallium arsenide (GaAs) semiconductor is used.
  • GaAs gallium arsenide
  • the semiconductor device shown in FIG. 10 can be manufactured basically by performing the steps shown in Table 1 below. The method of manufacturing the semiconductor device shown in FIG. 10 will be described with reference to Table 1 and FIG.
  • a substrate manufacturing step (see Table 1) is first performed as a first step.
  • the size of the substrate can be, for example, 50 mm in width, 50 mm in length, and 0.4 mm in thickness.
  • a substrate larger in size than the substrate 4 of the submount 3 (see FIG. 11) is prepared, a required structure is formed on the surface of the substrate, and the substrate is cut (see Table 1).
  • Submount 3 (see Fig. 11) can be obtained by cutting and splitting with.
  • the substrate to be the substrate 4 of the submount 3 is manufactured based on a normal substrate manufacturing method.
  • a sintered body of aluminum nitride (A1N) (see Table 1) is used.
  • A1N aluminum nitride
  • Table 1 As a method of manufacturing the substrate 4 made of a ceramic such as an aluminum nitride sintered body, an ordinary method of manufacturing a ceramic structure can be applied.
  • the material of the substrate 4 may be ceramics other than aluminum nitride, or a semiconductor substrate or a metal substrate.
  • a plane polishing step for polishing the surface of the substrate made of the aluminum nitride sintered body manufactured in the first step, the substrate manufacturing step.
  • polishing is performed until the surface roughness of the aluminum nitride substrate to be the substrate 4 (see FIG. 11) becomes 0.05 ⁇ in Ra.
  • a polishing method in this polishing step a commonly used polishing method can be applied.
  • a polishing method such as polishing with a grinder, sand blast, or polishing with sandpaper / abrasive grains can be used.
  • the third step is a patterning process (see Table 1).
  • a resist film is formed on the substrate surface in a region other than the region where the film 18, the Pt film 19, and the Au film 6 are to be formed by using a photolithography method.
  • an adhesion layer deposition step is performed. Specifically, a Ti film to be a Ti film 18 (see FIG. 11) as an adhesion layer is deposited on the substrate surface.
  • the thickness of the Ti film formed at this time can be, for example, 0.1 zm. Note that chromium, nickel chromium, tantalum, and compounds thereof can be used for the adhesion layer in addition to Ti. Further, the thickness of the adhesion layer (Ti film 18) is preferably 0.01 111 or more and 1.0 / zm or less.
  • a Pt film 19 as a diffusion preventing layer is formed on the Ti film to be a Ti film 18 (see FIG. 11) as an adhesion layer.
  • a diffusion prevention layer deposition process to form a film see Table 1.
  • the thickness of the Pt film for example, a value of 0.2 Aim can be used.
  • the diffusion preventing layer palladium, nickel chromium, tungsten titanium, nickele, molybdenum, or the like can be used in addition to Pt described above.
  • the thickness of the diffusion prevention layer (Pt film 19) ′ is preferably 0.01 to 111 / 1.5 / im.
  • an electrode layer deposition step of forming an Au film to be the Au film 6 (see FIG. 11) as an electrode layer is performed (see Table 1).
  • the thickness of the Au film can be, for example, 0.6 / im.
  • the thickness of the electrode layer (Au film 6) is preferably not less than 0.1 / zm and not more than 10 ⁇ .
  • the Ti film 18 as the adhesion layer, the Pt film 19 as the diffusion preventing layer, and the Au film 6 as the electrode layer (see Fig. 11) were formed by a sputtering method other than evaporation. For example, a normal film forming method can be applied.
  • a backside vapor deposition step of forming a Ti / Pt Au laminated film 20 (see FIG. 11) on the backside of the substrate 4 is performed (see Table 1).
  • the thickness of the Ti film constituting the TiZPtZAu laminated film is 0.1 ⁇ ⁇
  • the thickness of the Pt film is 0.2 ⁇ m
  • the thickness of the Au film is 0.6 ⁇ .
  • the Ti film in the Ti / PtZAu laminated film 20 the same material as the adhesive layer formed in the adhesive layer deposition step of the fourth step can be used, and the thickness thereof is set to 0. 01/1111 or more and 1. ⁇ or less.
  • the same material as the material used as the above-described diffusion preventing layer can be used, and the thickness thereof is not less than 0.1 L / m. It can be less than 5 m.
  • the thickness of the Au film in the Ti ⁇ tZAu laminated film 20 can be 0.1 ⁇ or more and 10 ⁇ or less, similarly to the above-mentioned electrode layer.
  • steps similar to the third to seventh steps may be performed. That is, when the TiZPtZAu laminated film 20 having a predetermined pattern is formed on the back side of the substrate 4, the photolithography method is used in advance similarly to the case where the Ti film 18, the Pt film 19 and the Au film 6 are formed. A resist film having a pattern is formed on the back surface of the substrate 4 by using After forming a film to be the / VtAu laminated film 20, a lift-off process for removing the resist film described above may be performed. Further, in order to form the Ti / PtZAu laminated film 20 having a predetermined pattern, a metal mask method may be used.
  • a solder barrier layer forming step of forming a solder barrier film 7 is performed (see Table 1).
  • a solder barrier film 7 made of platinum (Pt) is formed on the Au film 6 (see FIG. 11) by using a metal mask method.
  • the thickness of the solder barrier film 7 is set to 0.2 ⁇ .
  • nickel chromium, Eckel, or the like can be used in addition to platinum. Further, it is preferable that the thickness of the solder barrier film 7 is not less than 0.1 ⁇ and not more than 1.5 ⁇ .
  • solder barrier film 7 instead of the metal mask method as described above, a pattern jungling method using a photolithography method as shown in the third step to the seventh step in Table 1, or another method. A method may be used. Even in this way, the solder barrier film 7 having a predetermined pattern can be formed.
  • solder layer forming step of forming solder 8 on the solder barrier film 7 is performed.
  • the width WS and thickness d (see Fig. 11) of the solder 8 are appropriately changed depending on the sample.
  • the material constituting the solder 8 may be AuGe-based solder, PbSn-based solder, InSn-based solder, AgSn-based solder or These laminates can be used.
  • the thickness d (see FIG. 11) of the solder 8 can be set to 0.1 ⁇ or more and 10 ⁇ or less.
  • solder 8 having a predetermined pattern As a method for forming the solder 8 having a predetermined pattern, a metal mask method or a photolithography method as shown in the third to seventh steps of the method for manufacturing a semiconductor device according to the present invention shown in Table 1 may be used. Good.
  • a cutting step for cutting the substrate is performed.
  • the submount 3 shown in FIG. 11 can be obtained.
  • a laser element bonding step is performed (see Table 1). Specifically, as shown in FIG. 11, the laser element 2 is arranged as shown by an arrow 14 on the solder 8 melted by heating. In this way, the laser element 2 which is a chip using Ga As is joined to the submount 3 by the solder 8.
  • the laser element 2 may be a laser element using InP or GaN other than the element using GaAs, and a metallized layer such as an insulating layer and an electrode layer may be formed on the surface. May be formed.
  • a step of bonding the submount 3 on which the laser element 2 is mounted to the heat sink 22 (see FIG. 11) and a wire bonding step (see Table 11) 1).
  • a sheet-like solder 21 is arranged between the submount 3 and the heat sink 22.
  • the heat sink 22 is moved relative to the submount 3 in the direction indicated by the arrow 23, and the solder 21 is melted.
  • the submount 3 and the heat sink 22 are joined by the solder 21.
  • a gold (Au) wire is wire-bonded to an electrode or the like formed on the surface of the laser element 2.
  • a CuW alloy is used as the material of the heat sink 22.
  • copper (Cu), tungsten (W), molybdenum (Mo), iron (Fe), alloys of these metals, and composite materials can be used as the material of the heat sink 22.
  • solder 21 a sheet-like solder may be arranged between the submount 3 and the heat sink 22 as described above, or the solder 21 may be arranged on the upper surface of the heat sink 22 in advance. Further, the solder 21 may be arranged on the lower surface of the Ti / Pt / Au laminated film 20 of the submount 3.
  • a laminated film made of a nickel (Ni) film and a gold (Au) film is formed on the surface of the heat sink 22 joined to the solder 21.
  • the reason for forming such a laminated film is to improve the wettability of the solder 21 on the surface of the heat sink 22.
  • sample IDs 1 to 23 were obtained as shown in Table 2 below.
  • 20 samples having the same structure were produced.
  • an appearance inspection and a luminescence inspection were performed. The results are also shown in Table 2.
  • the columns of I, LS, WC, WS, d, and W indicate the length of the laser element 2 (see Fig. 3), the length of the solder 8 (see Fig. 3), and the width of the laser element 2, respectively. It shows the solder 8 width (see Fig. 11), the thickness of the solder 8 (see Fig. 11), and the evaluation value.
  • the column of good appearance shows the results of the appearance inspection. For example, the description of 20 Z 20 in the column of good appearance for sample ID 1 means that 20 out of 20 samples For 0 samples (ie, all samples), no defect was found in which the solder 8 (see FIG. 10) rose on the end face of the laser element 2.
  • the sample of the example of the present invention can obtain a normal semiconductor device that can oscillate laser light with a higher probability than the comparative example.
  • Table 3 The items described in Table 3 are basically the same as Table 2. As can be seen from Table 3, it can be seen that the example of the present invention obtains a non-defective product (a semiconductor device capable of normally performing laser light oscillation) with a higher probability than the comparative example.
  • a non-defective product a semiconductor device capable of normally performing laser light oscillation

Abstract

L'invention concerne une embase permettant à la brasure de passer au-dessus de la bordure d'un dispositif laser à semiconducteur et un dispositif à semiconducteur. Une embase destinée au montage d'un dispositif à semiconducteur (2) sur celui-ci comprend un substrat d'embrase (4), et une pellicule à brasure (8) formée sur le substrat d'embase (4), la largeur WS (νm) et l'épaisseur d (νm) de la pellicule à brasure étant déterminées de manière à satisfaire aux conditions suivantes : 0,3 ≤ d ≤1 lorsque W = -30 νm, 0,3 ≤ d ≤ (7xW/110+32/11) lorsque -30 νm < W < 30 νm, (37xW/600-1,55) ≤ d ≤ (7xW/110+32/11) lorsque 30 νm < W ≤ 80 νm et (37xW/600-1,55) ≤ d ≤ 8 lorsque 80 νm < W ≤ 90 νm. WC représente la largeur (νm) du dispositif à semiconducteur à monter sur le film à brasure et W représente une valeur d'évaluation (νm) définie par 2W = (WC-WS).
PCT/JP2002/012870 2002-02-18 2002-12-09 Embase et dispositif a semiconducteur WO2003069743A1 (fr)

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AU2002349516A AU2002349516A1 (en) 2002-02-18 2002-12-09 Sub-mount and semiconductor device

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JP2002040643A JP3779218B2 (ja) 2002-02-18 2002-02-18 サブマウントおよび半導体装置

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JP3982284B2 (ja) * 2002-03-06 2007-09-26 住友電気工業株式会社 サブマウントおよび半導体装置
JP4811629B2 (ja) * 2004-07-12 2011-11-09 ソニー株式会社 半導体レーザ装置
US7795732B2 (en) * 2005-02-07 2010-09-14 Kabushiki Kaisha Toshiba Ceramic wiring board and process for producing the same, and semiconductor device using the same
JP2008141172A (ja) * 2006-11-10 2008-06-19 Ricoh Printing Systems Ltd 半導体レーザ装置、光走査装置および画像形成装置
JP2013093341A (ja) * 2010-02-26 2013-05-16 Sanyo Electric Co Ltd 電子デバイス
JP2011222675A (ja) 2010-04-07 2011-11-04 Mitsubishi Electric Corp 半導体装置及びその製造方法
CN105518887B (zh) * 2013-09-05 2018-01-02 松下知识产权经营株式会社 发光装置
JP6305127B2 (ja) * 2014-03-12 2018-04-04 三菱電機株式会社 半導体レーザ光源
JP2018206788A (ja) * 2017-05-30 2018-12-27 富士通株式会社 電子装置及び電子装置の製造方法
WO2019180773A1 (fr) * 2018-03-19 2019-09-26 三菱電機株式会社 Procédé de fabrication de dispositif à semiconducteurs

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JPH04186688A (ja) * 1990-11-17 1992-07-03 Seiko Epson Corp 半導体レーザ装置
JPH0513820A (ja) * 1991-07-02 1993-01-22 Omron Corp 半導体装置
JPH05190973A (ja) * 1992-01-14 1993-07-30 Toshiba Corp 半導体レーザ用サブマウント
US5285463A (en) * 1991-12-03 1994-02-08 Rohm Co., Ltd. Semiconductor device

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Publication number Priority date Publication date Assignee Title
JPH04186688A (ja) * 1990-11-17 1992-07-03 Seiko Epson Corp 半導体レーザ装置
JPH0513820A (ja) * 1991-07-02 1993-01-22 Omron Corp 半導体装置
US5285463A (en) * 1991-12-03 1994-02-08 Rohm Co., Ltd. Semiconductor device
JPH05190973A (ja) * 1992-01-14 1993-07-30 Toshiba Corp 半導体レーザ用サブマウント

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