WO2003067596A3 - Halbleiterspeicherzelle mit einem graben und einem planaren auswahltransistor und verfahren zu ihrer herstellung - Google Patents

Halbleiterspeicherzelle mit einem graben und einem planaren auswahltransistor und verfahren zu ihrer herstellung Download PDF

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Publication number
WO2003067596A3
WO2003067596A3 PCT/DE2003/000284 DE0300284W WO03067596A3 WO 2003067596 A3 WO2003067596 A3 WO 2003067596A3 DE 0300284 W DE0300284 W DE 0300284W WO 03067596 A3 WO03067596 A3 WO 03067596A3
Authority
WO
WIPO (PCT)
Prior art keywords
implantation
trenches
trench
memory cell
semiconductor memory
Prior art date
Application number
PCT/DE2003/000284
Other languages
English (en)
French (fr)
Other versions
WO2003067596A2 (de
Inventor
Johann Alsmeier
Original Assignee
Infineon Technologies Ag
Johann Alsmeier
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Johann Alsmeier filed Critical Infineon Technologies Ag
Priority to KR1020047012083A priority Critical patent/KR100585440B1/ko
Publication of WO2003067596A2 publication Critical patent/WO2003067596A2/de
Publication of WO2003067596A3 publication Critical patent/WO2003067596A3/de
Priority to US10/913,797 priority patent/US7256440B2/en

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H10B12/0385—Making a connection between the transistor and the capacitor, e.g. buried strap

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Manufacturing & Machinery (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Semiconductor Memories (AREA)
  • Element Separation (AREA)

Abstract

Ein Graben (12) einer Halbleiterspeicherzelle (1) besitzt einen Isolationskragen (44), welcher auf nur einer Seite (50) zum Substrat (42) hin geöffnet ist. Auf der anderen Seite (52) ist der Isolationskragen (44, 47, 55) bis zu dem Isolationsdeckel (62) hochgezogen. Eine Shallow Trench Isolation ist daher nicht notwendig. Der einseitig vergrabene Kontakt (70) wird gebildet durch Schrägimplantation, beispielsweise mit N2 oder Argon, wobei die Implantation aus einer fest vorgegebenen Richtung mit einem Neigungswinkel zwischen 15 und 40° erfolgt. Die Implantationssubstanzen bewirken unterschiedliche Ätz- oder Oxidationseigenschaften etc. des implantierten Materials. In Kombination mit diesem Verfahren wird ein neues Layout für die Halbleiterspeicherzelle (1) ermöglicht, bei dem die Strukturen zur Bildung der aktiven Gebiete sich über mehrere benachbarte Halbleiterspeicherzellen erstreckende lange Linien (31) bilden. Dadurch wird auf vorteilhafte Weise das Problem strikter Overlay-Toleranzen zwischen den Gräben 12 und den Strukturen 31 zur Bildung der aktiven Gebiete gelöst. Desweiteren wird eine schachbrettmusterartige Anordnung der Gräben (12, 13) gebildet, welche das Problem der lithographischen Strukturbreitenkontrolle benachbarter Gräben löst.
PCT/DE2003/000284 2002-02-07 2003-01-31 Halbleiterspeicherzelle mit einem graben und einem planaren auswahltransistor und verfahren zu ihrer herstellung WO2003067596A2 (de)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1020047012083A KR100585440B1 (ko) 2002-02-07 2003-01-31 반도체 메모리 셀의 제조 방법
US10/913,797 US7256440B2 (en) 2002-02-07 2004-08-06 Semiconductor memory cell having a trench and a planar selection transistor and method for producing the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10205077.5 2002-02-07
DE10205077A DE10205077B4 (de) 2002-02-07 2002-02-07 Halbleiterspeicherzelle mit einem Graben und einem planaren Auswahltransistor und Verfahren zu ihrer Herstellung

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US10/913,797 Continuation US7256440B2 (en) 2002-02-07 2004-08-06 Semiconductor memory cell having a trench and a planar selection transistor and method for producing the same

Publications (2)

Publication Number Publication Date
WO2003067596A2 WO2003067596A2 (de) 2003-08-14
WO2003067596A3 true WO2003067596A3 (de) 2003-10-09

Family

ID=27634790

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2003/000284 WO2003067596A2 (de) 2002-02-07 2003-01-31 Halbleiterspeicherzelle mit einem graben und einem planaren auswahltransistor und verfahren zu ihrer herstellung

Country Status (5)

Country Link
US (1) US7256440B2 (de)
KR (1) KR100585440B1 (de)
DE (1) DE10205077B4 (de)
TW (1) TWI223893B (de)
WO (1) WO2003067596A2 (de)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10334547B4 (de) 2003-07-29 2006-07-27 Infineon Technologies Ag Herstellungsverfahren für einen Grabenkondensator mit einem Isolationskragen, der über einen vergrabenen Kontakt einseitig mit einem Substrat elektrisch verbunden ist
DE10355225B3 (de) * 2003-11-26 2005-03-31 Infineon Technologies Ag Herstellungsverfahren für einen Grabenkondensator mit einem Isolationskragen, der über einen vergrabenen Kontakt einseitig mit einem Substrat elektrisch verbunden ist, insbesondere für eine Halbleiterspeicherzelle
TWI235426B (en) * 2004-01-28 2005-07-01 Nanya Technology Corp Method for manufacturing single-sided buried strap
JP4398829B2 (ja) * 2004-09-17 2010-01-13 株式会社東芝 半導体装置
DE102004049667B3 (de) * 2004-10-12 2006-05-18 Infineon Technologies Ag Herstellungsverfahren für einen Grabenkondensator mit einem Isolationskragen, der über einen vergrabenen Kontakt einseitig mit einem Substrat elektrisch verbunden ist, insbesondere für eine Halbleiterspeicherzelle und entsprechender Grabenkondensator
US7179748B1 (en) * 2005-08-02 2007-02-20 Nanya Technology Corporation Method for forming recesses
US7316978B2 (en) * 2005-08-02 2008-01-08 Nanya Technology Corporation Method for forming recesses
US7371645B2 (en) * 2005-12-30 2008-05-13 Infineon Technologies Ag Method of manufacturing a field effect transistor device with recessed channel and corner gate device
US7777266B2 (en) * 2007-11-29 2010-08-17 Qimonda Ag Conductive line comprising a capping layer
US8008160B2 (en) 2008-01-21 2011-08-30 International Business Machines Corporation Method and structure for forming trench DRAM with asymmetric strap
TWI455290B (zh) * 2008-11-13 2014-10-01 Inotera Memories Inc 記憶體元件及其製造方法
TWI440190B (zh) * 2009-09-11 2014-06-01 Inotera Memories Inc 堆疊式隨機動態存取記憶體之雙面電容之製造方法
TWI418018B (zh) * 2009-11-03 2013-12-01 Taiwan Memory Corp 電子裝置及其製造方法、記憶體裝置
US10229832B2 (en) * 2016-09-22 2019-03-12 Varian Semiconductor Equipment Associates, Inc. Techniques for forming patterned features using directional ions

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0908948A2 (de) * 1997-09-23 1999-04-14 Siemens Aktiengesellschaft Flachgraben-Isolation für DRAM Grabenkondensator
EP0949684A2 (de) * 1998-04-06 1999-10-13 Siemens Aktiengesellschaft Grabenkondensator mit epitaktischer vergrabener Schicht

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5936271A (en) * 1994-11-15 1999-08-10 Siemens Aktiengesellschaft Unit cell layout and transfer gate design for high density DRAMs having a trench capacitor with signal electrode composed of three differently doped polysilicon layers
US6100131A (en) * 1997-06-11 2000-08-08 Siemens Aktiengesellschaft Method of fabricating a random access memory cell
US6018174A (en) * 1998-04-06 2000-01-25 Siemens Aktiengesellschaft Bottle-shaped trench capacitor with epi buried layer
US5945704A (en) * 1998-04-06 1999-08-31 Siemens Aktiengesellschaft Trench capacitor with epi buried layer
DE10120053A1 (de) * 2001-04-24 2002-11-14 Infineon Technologies Ag Stressreduziertes Schichtsystem

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0908948A2 (de) * 1997-09-23 1999-04-14 Siemens Aktiengesellschaft Flachgraben-Isolation für DRAM Grabenkondensator
EP0949684A2 (de) * 1998-04-06 1999-10-13 Siemens Aktiengesellschaft Grabenkondensator mit epitaktischer vergrabener Schicht

Also Published As

Publication number Publication date
US20050077563A1 (en) 2005-04-14
DE10205077B4 (de) 2007-03-08
TW200303086A (en) 2003-08-16
US7256440B2 (en) 2007-08-14
DE10205077A1 (de) 2003-08-28
TWI223893B (en) 2004-11-11
KR20040086344A (ko) 2004-10-08
WO2003067596A2 (de) 2003-08-14
KR100585440B1 (ko) 2006-06-07

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