Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F15/00—Digital computers in general; Data processing equipment in general
  • G06F15/76—Architectures of general purpose stored program computers
  • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
  • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F15/00—Digital computers in general; Data processing equipment in general
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B10/00—Static random access memory [SRAM] devices
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B20/00—Read-only memory [ROM] devices
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/30—Die-attach connectors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
  • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
  • Y10S257/922—Active solid-state devices, e.g. transistors, solid-state diodes with means to prevent inspection of or tampering with an integrated circuit, e.g. "smart card", anti-tamper

Definitions

• the present invention relates, in general, to the field of systems and methods for reconfigurable, or adaptive, data processing. More particularly, the present invention relates to an extremely compact reconfigurable processor module comprising hybrid stacked integrated circuit ("IC") die elements.
• IC integrated circuit
• reconfigurable processors In addition to current commodity IC microprocessors, another type of processing element is commonly referred to as a reconfigurable, or adaptive, processor. These reconfigurable processors exhibit a number of advantages over commodity microprocessors in many applications. Rather than using the conventional "load/store" paradigm to execute an application using a set of limited functional resources as a microprocessor does, the reconfigurable processor actually creates the number of functional units it needs for each application in hardware. This results in greater parallelism and, thus, higher throughput for many applications. Conventionally, the ability for a reconfigurable processor to alter its hardware compliment is typically accomplished through the use of some form of field programmable gate array (“FPGA”) such as those produced by Altera Corporation, Xilinx, Inc., Lucent Technologies, Inc. and others.
• FPGA field programmable gate array
• Context-switching is a process wherein the operating system will temporarily terminate a job that is currently running in order to process a job of higher priority. For the GPRP this would mean it would have to again reconfigure itself thereby wasting even more time.
• FPGAs, microprocessors and cache memory may be combined through the use of recently available wafer processing techniques to create a particularly advantageous form of hybrid, reconfigurable processor module that overcomes the limitations of present discrete, integrated circuit device implementations of GPRP systems.
• this new processor module may be conveniently denominated as a Stacked Die Hybrid ("SDH") Processor.
• Tru-Si Technologies of Sunnyvale, CA http://www.trusi.com has developed a process wherein semiconductor wafers may be thinned to a point where metal contacts can traverse the thickness of the wafer creating small bumps on the back side much like those of a BGA package.
• cache memory and FPGA wafers all three die, or combinations of two or more of them, may be advantageously assembled into a single very compact structure thus eliminating or ameliorating each of the enumerated known difficulties encountered with existing reconfigurable technology discussed above.
• a processor module with reconfigurable capability constructed by stacking and interconnecting bare die elements.
• a processor module with reconfigurable capability may be constructed by stacking thinned die elements and interconnecting the same utilizing contacts that traverse the thickness of the die.
• such a processor module may comprise a microprocessor, memory and FPGA die stacked into a single block.
• a processor module with reconfigurable capability may include, for example, a microprocessor, memory and FPGA die stacked into a single block for the purpose of accelerating the sharing of data between the microprocessor and FPGA.
• Such a processor module block configuration advantageously increases final assembly yield while concomitantly reducing final assembly cost.
• an FPGA module that uses stacking techniques to combine it with a memory die for the purpose of accelerating FPGA reconfiguration.
• the FPGA module may employ stacking techniques to combine it with a memory die for the purpose of accelerating external memory references as well as to expand its on chip block memory.
• an FPGA module that uses stacking techniques to combine it with other die for the purpose of providing test stimulus during manufacturing as well as expanding the FPGA's capacity and performance.
• the technique of the present invention may also be used to advantageously provide a memory or input/output (“I/O") module with reconfigurable capability that includes a memory or I/O controller and FPGA die stacked into a single block.
• I/O input/output
• Fig. 1 is a simplified functional block diagram of a portion of a prior art computer system incorporating one or more multi-adaptive processing (MAPTM is a trademark of SRC Computers, Inc., Colorado Springs, CO) elements;
• Fig. 2 is a more detailed, simplified functional block diagram of the multi-adaptive processing element illustrated in Fig. 1 illustrating the user logic block (which may comprise a field programmable gate array "FPGA") with its associated configuration read only memory (“ROM");
• FPGA field programmable gate array
• ROM configuration read only memory
• Fig. 3 is a functional block diagram of a representative configuration data bus comprising a number of static random access memory (“SRAM”) cells distributed throughout the FPGA comprising the user logic lock of Fig. 2;
• Fig. 4 is a simplified, exploded isometric view of a reconfigurable processor module in accordance with the present invention comprising a hybrid device incorporating a number of stacked integrated circuit die elements; and
• Fig. 5 is a corresponding functional block diagram of the configuration cells of the reconfigurable processor module of Fig. 4 wherein the FPGA may be totally reconfigured in one clock cycle by updating all of the configuration cells in parallel.
• a simplified functional block diagram of a portion of a prior art reconfigurable computer system 10 is shown.
• the computer system 10 incorporates, in pertinent part, one or more microprocessors 12, one or more multi-adaptive processing (MAPTM) elements 14 and an associated system memory 16.
• a system bus 18 bidirectionally couples a MAP element 14 to the microprocessor 12 by means of a bridge 22 as well as to the system memory 16 by means of a crossbar switch 24.
• Each MAP element 14 may also include one or more bidirectional connections 20 to other adjacent MAP elements 14 as shown.
• the multi- adaptive processing element 14 comprises, in pertinent part, a user logic block 32, which may comprise an FPGA together with its associated configuration ROM 34.
• a MAP control block 36 and associated direct memory access (“DMA") engine 38 as well as an on- board memory array 40 is coupled to the user logic block 32 as well as the system bus 18.
• DMA direct memory access
• a functional block diagram of a representative configuration data bus 50 comprising a number of SRAM cells distributed throughout an FPGA comprising the user logic block 32 of the preceding figure.
• the configuration information that programs the functionality of the chip is held in SRAM cells distributed throughout the FPGA as shown.
• Configuration data is loaded through a configuration data port 52 in a byte serial fashion and must configure the cells sequentially progressing through the entire array of logic cells 54 and associated configuration memory 56. It is the loading of this data through a relatively narrow, for example, 8 bit port that results in the long reconfiguration times.
• a simplified, exploded isometric view of a reconfigurable processor module 60 in accordance with a representative embodiment of the present invention comprising a hybrid device incorporating a number of stacked integrated circuit die elements.
• the module 60 comprises a die package 62 to which is coupled a microprocessor die 64, memory die 66 and FPGA die 68, all of which have a number of corresponding contact points, or holes, 70 formed throughout the area of the package 62 and various die 64, 66 and 68.
• a module 60 in accordance with the present invention may also comprise any combination of one or more of the microprocessor die 64, memory die 66 or FPGA 68 with any other of a microprocessor die 64, memory die 66 or FPGA die 68.
• the contact holes 70 are formed in the front side of the wafer and an insulating layer of oxide is added to separate the silicon from the metal.
• the wafer is thinned to expose the through-silicon contacts.
• ADP atmospheric downstream plasma
• the oxide is etched to expose the metal. Given that this etching process etches the silicon faster, the silicon remains insulated from the contacts.
• the cache memory die 66 actually serves two purposes. The first of these is its traditional role of fast access memory. However in this new assembly it is accessible by both the microprocessor 64 and the FPGA 68 with equal speed. In those applications wherein the memory 66 is tri-ported, the bandwidth for the system can be further increased. This feature clearly solves a number of the problems inherent in existing reconfigurable computing systems and the capability of utilizing the memory die 66 for other functions is potentially very important.
• a corresponding functional block diagram of the configuration cells 80 of the reconfigurable processor module 60 of the preceding figure is shown wherein the FPGA 70 may be totally reconfigured in one clock cycle by updating all of the configuration cells in parallel.
• a wide configuration data port 82 is included to update the various logic cells 84 through an associated configuration memory 86 and buffer cell 88.
• the buffer cells 88 are preferably a portion of the memory die 66 (Fig. 4). In this manner, they can be loaded while the FPGA 68 comprising the logic cells 84 are in operation. This then enables the FPGA 68 to be totally reconfigured in one clock cycle with all of it configuration logic cells 84 updated in parallel.
• the FPGA 68 can be configured in such a way as to provide test stimulus to the microprocessor 64, or other chips in the stack of the die package 62 during manufacture and prior to the completion of the module packaging. After test, the FPGA 68 can then be reconfigured for whatever function is desired. This then allows more thorough testing of the assembly earlier in the manufacturing process than could be otherwise achieved with traditional packaged part test systems thus reducing the costs of manufacturing.
• FPGA die 68 may be included in the reconfigurable module 60.
• inter-cell connections currently limited to two dimensions of a single die, may be routed up and down the stack in three dimensions. This is not known to be possible with any other currently available stacking techniques since they all require the stacking contacts to be located on the periphery of the die. In this fashion, the number of FPGA die 68 cells that may be accessed within a specified time period is increased by up to 4VT/3, where "V" is the propagation velocity of the wafer and "T" is the specified time of propagation.
• Another option would be to fabricate a single die containing microprocessor, memory and FPGA. Such a die could use metalization layers to interconnect the three functions and achieve much of the benefits of die stacking. However such a die would be extremely large resulting in a much lower production yield than the three separate die used in a stacked configuration. In addition, stacking allows for a ready mix of technology families on different die as well as offering a mix of processor and FPGA numbers and types. Attempting to effectuate this with a single large die would require differing mask sets for each combination, which would be very costly to implement.

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• Engineering & Computer Science (AREA)
• Theoretical Computer Science (AREA)
• Computer Hardware Design (AREA)
• Physics & Mathematics (AREA)
• General Engineering & Computer Science (AREA)
• General Physics & Mathematics (AREA)
• Design And Manufacture Of Integrated Circuits (AREA)
• Semiconductor Integrated Circuits (AREA)
• Microcomputers (AREA)

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• 2001
  • 2001-12-05 US US10/012,057 patent/US6627985B2/en not_active Ceased
• 2002
  • 2002-11-08 JP JP2003551682A patent/JP2005512229A/ja active Pending
  • 2002-11-08 AU AU2002352582A patent/AU2002352582A1/en not_active Abandoned
  • 2002-11-08 CA CA002467821A patent/CA2467821C/en not_active Expired - Fee Related
  • 2002-11-08 KR KR10-2004-7008724A patent/KR20040072645A/ko not_active Ceased
  • 2002-11-08 EP EP02789540A patent/EP1461715A4/en not_active Withdrawn
  • 2002-11-08 WO PCT/US2002/035972 patent/WO2003050694A1/en not_active Ceased
• 2003
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• 2008
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