WO2002102061A1 - Detecteur d'images - Google Patents
Detecteur d'images Download PDFInfo
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- WO2002102061A1 WO2002102061A1 PCT/JP2002/003481 JP0203481W WO02102061A1 WO 2002102061 A1 WO2002102061 A1 WO 2002102061A1 JP 0203481 W JP0203481 W JP 0203481W WO 02102061 A1 WO02102061 A1 WO 02102061A1
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- pixel
- sensor
- signal
- image sensor
- circuit
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- 239000011159 matrix material Substances 0.000 claims abstract description 13
- 230000003287 optical effect Effects 0.000 claims description 12
- 238000003384 imaging method Methods 0.000 claims description 9
- 238000006243 chemical reaction Methods 0.000 claims description 7
- 238000001514 detection method Methods 0.000 claims description 7
- 230000003071 parasitic effect Effects 0.000 claims description 4
- 238000000034 method Methods 0.000 claims 1
- 239000007787 solid Substances 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 11
- 239000008186 active pharmaceutical agent Substances 0.000 description 3
- 101710179738 6,7-dimethyl-8-ribityllumazine synthase 1 Proteins 0.000 description 2
- 101710186608 Lipoyl synthase 1 Proteins 0.000 description 2
- 101710137584 Lipoyl synthase 1, chloroplastic Proteins 0.000 description 2
- 101710090391 Lipoyl synthase 1, mitochondrial Proteins 0.000 description 2
- 206010047571 Visual impairment Diseases 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 238000001444 catalytic combustion detection Methods 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/50—Control of the SSIS exposure
- H04N25/57—Control of the dynamic range
- H04N25/571—Control of the dynamic range involving a non-linear response
- H04N25/573—Control of the dynamic range involving a non-linear response the logarithmic type
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/779—Circuitry for scanning or addressing the pixel array
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/7795—Circuitry for generating timing or clock signals
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N3/00—Scanning details of television systems; Combination thereof with generation of supply voltages
- H04N3/10—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical
- H04N3/14—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical by means of electrically scanned solid-state devices
- H04N3/15—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical by means of electrically scanned solid-state devices for picture signal generation
- H04N3/1506—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical by means of electrically scanned solid-state devices for picture signal generation with addressing of the image-sensor elements
- H04N3/1512—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical by means of electrically scanned solid-state devices for picture signal generation with addressing of the image-sensor elements for MOS image-sensors, e.g. MOS-CCD
Definitions
- a solid-state image pickup device based on pixel units is arranged in a matrix, and a line of pixel lines for one line is sequentially selected, and each element in the sequentially selected pixel line is sequentially detected.
- an image sensor that selectively reads out a sensor signal of each pixel in a time-series manner.
- Figure 1 shows a conventional solid-state image sensor that is a pixel unit in an image sensor.
- optical sensor circuit configured as described above.
- the optical sensor circuit uses a photodiode PD as a photoelectric conversion element that generates a sensor current corresponding to the amount of incident light Ls at the time of light detection, and uses the characteristics of the sub-threshold region for the sensor current flowing through the photodiode PD.
- Transistor Q1 that converts to a voltage signal Vpd with a logarithmic characteristic in the weakly inverted state
- transistor Q2 that amplifies the converted voltage signal Vpd
- sensor it with pulse timing of readout signal Vs It is composed of a transistor Q 3 that outputs 3 ⁇ 4 'S o, so that the optical signal can be detected with high sensitivity by expanding the dynamic range.
- the drain voltage VD of the transistor Q1 Prior to the light detection, the drain voltage VD of the transistor Q1 is set lower than a steady value for a predetermined time, and the residual charge accumulated in the parasitic capacitance C of the photodiode PD is discharged and initialized. Even if a sudden change occurs in the sensor current, a voltage signal V ⁇ d corresponding to the amount of incident light L s at that time can be obtained immediately, so that an afterimage does not occur even when the amount of incident light is small. (See Japanese Patent Application Laid-Open No. 2000-320926).
- FIG. 2 shows a time chart of each signal of the optical sensor path.
- t 1 indicates the initialization timing
- t 2 indicates the output timing of the sensor signal S o
- T indicates the charge accumulation period in the parasitic capacitance C at the time of light detection.
- FIG. 3 shows the output characteristics of the sensor if'So with respect to the sensor current according to the amount of incident light in the optical sensor circuit. It shows logarithmic output characteristics when the sensor current flowing through the photodiode PD is large, and The response of the charging of the raw capacity c is delayed, and the output shows an almost linear non-logarithmic output characteristic.
- WA indicates a non-logarithmic response region
- WB indicates a logarithmic response region.
- Fig. 4 shows such a photosensor circuit as a pixel unit, where a plurality of pixels are arranged in a matrix so that each pixel sensor can read out signals in time series.
- 3 shows an example of the configuration of the image sensor.
- each pixel consisting of Dl 1 to D 44 is arranged in a matrix, and under control of an ECU (not shown), one row of each pixel is selected as a pixel column selection circuit.
- the selection signals LS 1 to LS 4 sequentially output from 1 are selected, and each pixel in the selected pixel column is selected in the switch circuit 3 by the selection signals DS 1 to DS 4 sequentially output from the pixel selection circuit 2.
- the sensor signal So of each pixel is read out in time series. Then, the sensor signal S o of each pixel sequentially read out is output as a voltage signal V o defined by applying a bias voltage V cc via a reference resistor R.
- reference numeral 4 denotes a power supply for the gate voltage VG of the transistor Q1 in each pixel
- reference numeral 6 denotes a power supply for the drain voltage VD
- Reference numeral 5 denotes a voltage switching circuit that switches the drain voltage V D of the transistor Q 1 to a high level H in a steady state and a low level L in an initialization with a predetermined timing.
- FIG. 5 shows a time chart of each signal of the image sensor configured as described above.
- the driving capability for converting the sensor signal S o of each pixel into a voltage ⁇ V o and outputting the voltage is low. Since the voltage signal Vo of the pixel is output before reaching a sufficient saturation level, it is impossible to perform a high-speed readout operation.
- the sensor -S 0 read from each of the lines is output to the output system of each line for one line by the reference resistor R to which the bias voltage V cc is applied.
- a bias circuit 11 that converts each to a voltage signal V o is provided to increase the fil driving capability and to perform readout scanning at high speed. I am able to do it.
- a buffer circuit 12 connected to a buffer BF was connected to each of the tying lines on the output side of the bias circuit 11 and selected by the pixel selection circuit 2.
- the solid-state image pickup devices in pixel units are arranged in a matrix, and the ⁇ columns for each line are sequentially selected, and each pixel in the sequentially selected pixel column is sequentially selected to select each pixel.
- the sequentially readout sensor signals of each pixel are converted into voltage signals defined by applying a bias voltage via a reference resistor. If output is used, there is a problem that the signal drive capability is low and high-speed read scanning cannot be performed.
- a bias circuit is provided in the output system of each pixel for one line to convert the sensor signal read from each pixel into a voltage signal by defining the sensor signal with a reference resistor to which a bias voltage is applied.
- solid-state imaging devices in pixel units are arranged in a matrix, pixel rows for one line are sequentially selected, and pixels in the sequentially selected pixel rows are sequentially selected, and a sensor signal of each pixel is obtained.
- the sensor signal read out from each pixel is specified by the reference resistance to which the bias voltage is applied to the output system of each pixel for one line, so that each voltage signal
- a buffer circuit is connected to each of the bias circuits for conversion and each signal line on the output side, and a buffer amplifier is connected to each of the signal lines. Voltage signals of each pixel sequentially output from the bias circuit are temporarily accumulated in the buffer circuit.
- a solid-state imaging device in pixel units is arranged in a matrix, a pixel row for each one line is sequentially selected, and each pixel in a sequentially selected pixel row is sequentially selected, and a sensor of each pixel is sequentially selected.
- a pixel row for one line consists of a predetermined number of pixel configurations.
- a first scanning unit that divides the sensor signal of each pixel sequentially into ⁇ from the first block obtained by dividing the block equally into a plurality of blocks, and a sensor signal of each pixel in the read block.
- a second scanning means for sequentially reading is provided.
- the present invention provides a solid-state imaging device in pixel units arranged in a matrix, sequentially selects a pixel line for each one line, sequentially selects each pixel in the sequentially selected pixel line, and selects each pixel.
- First scanning means for equally reading out the sensor signal of each pixel in order from the first project divided into a plurality of equal parts by a block having a pixel configuration, and a sensor of each pixel in the read out block;
- a buffer means for temporarily accumulating the sensor signals and a second scanning means for sequentially reading the sensor signals of the pixels temporarily accumulated are provided.
- FIG. 1 is an electrical circuit diagram showing a configuration example of an optical sensor circuit used for a pixel of an image sensor.
- FIG. 2 is a time chart of signals of various parts in the optical sensor circuit.
- FIG. 3 is a diagram illustrating output characteristics of a sensor signal with respect to a sensor current in the optical sensor circuit.
- FIG. 4 is a circuit diagram showing a configuration example of an image sensor using a conventional optical sensor circuit for a pixel.
- FIG. 5 is a time chart of each part of the conventional image sensor.
- FIG. 6 is a circuit configuration diagram showing another configuration example of a conventional image sensor.
- FIG. 7 is a circuit diagram showing an embodiment of the image sensor according to the present invention.
- FIG. 8 is a time chart of each part showing an example of an operation state of the image sensor due to the projecting application.
- Ninth is a circuit configuration diagram showing a configuration example of a shift register used for a pixel selection circuit in the image sensor according to the embodiment.
- FIG. 10 is a circuit diagram showing a configuration example of a decoder circuit used in a pixel selection circuit in the image sensor according to the embodiment.
- 11th is a time chart of each part signal showing another example of the operation state of the image sensor according to the embodiment.
- FIG. 12 is a circuit configuration diagram showing another configuration example of a decoder circuit used for a pixel selection circuit in the image sensor according to the embodiment.
- FIG. 13 is a circuit diagram showing another embodiment of the image sensor according to the present invention.
- a fourteenth paragraph is a time chart of each part signal showing an example of an operation state in the image sensor according to another embodiment.
- FIG. 15 is a circuit diagram showing still another example of the configuration of a conventional image sensor. You.
- FIG. 16 is a circuit configuration 1 showing still another embodiment of the image sensor according to the present invention.
- FIG. 17M is a circuit configuration diagram showing still another embodiment of the image sensor according to the present invention.
- FIG. 7 shows an embodiment of the image sensor according to the present invention.
- the photosensor circuit is a pixel unit ..
- a plurality of pixels are arranged in a matrix .
- Pixel column selection circuit 1 and pixel selection The configuration is such that the driving of the circuit 2 causes the sensor signal of each pixel to be read out in time series through the switch circuit 3.
- the pixel column for one line is composed of 16 pixels, the pixels in the first column are Dl 1 to D 1 16 and the pixels in the second column are D 21 1 to D Displayed as 2 1 6
- a pixel row for one line is set to a set of two pylons (for example, D 11 and D 12, D 13 and D 14.
- the same pixel is divided into eight equal parts by the CJK consisting of each pair of 1 1 1 5 and D 1 1 6, and the first pixel in each block, that is, the odd-numbered pixel (D 1 1, D 1 1.3, ⁇ , D 1 15) and the second pixel in each project, that is, the even-numbered image (D 1 2 , D 1,..., D 1 16), and the b 'line b, which has a common output line for the sensor signal, is drawn out.
- a pixel row for one line is formed by combining two pixels (for example, ⁇ 11 and D 12, D 13 and D 1 '1,'..., D 1 1 5 and D 1 16) are equally divided into eight blocks, and the first pixel in each block, that is, the odd-numbered ⁇ '(D 11, ⁇ 13, , D 115), the output of the sensor signal of the sensor line, and the second pixel in each business, that is, the pixel of the even-numbered pixel (1) 1 2, [) 1 4,..., D1 16) i and b lines, which share the output line of the sensor signal ⁇ , are drawn out.
- two pixels for example, ⁇ 11 and D 12, D 13 and D 1 '1,'..., D 1 1 5 and D 1 16
- a pixel selection circuit 7 for sending out signals for sequentially selecting one sensor signal B 1, ⁇ 2 for one cycle to each of the ⁇ 33 ⁇ 4 lines a, b, and its selection output No.
- a switch circuit 8 for sequentially turning on the analog switches T 1 and ⁇ 2 to output the sensor signals ⁇ 1 and ⁇ 2 of each pixel is provided, and the sensor signal of the pixels read from each block is provided.
- a bias circuit 9 is provided which is specified as a voltage value by a reference resistor R to which a bias voltage Vcc is applied.
- a resistance load a transistor load, or the like can be used as the reference resistance R. If the sensor signal of each pixel is output as a voltage signal, there is no need to provide this bias circuit 9.
- FIG. 8 is a time chart of each part signal showing an example of an operation state of the image sensor having the configuration of FIG.
- Pixel row selection The pixel row consisting of D 1 1 to D 1 16 is selected by the LS 1 and the analog switches SW 1 to SW 16 are sequentially turned on according to the pixel selection signals DS 1 to DS 16
- the sensor signal B 1 of the odd-numbered pixel (D 11, D 13, ' ⁇ ', D 11 5) is read out to the signal line a.
- the even-numbered pixel (D 1 2, D 14,..., ⁇ 1 16)
- the sensor signal ⁇ 2 is read out to the signal line b.
- the analog switches are switched according to the selection signal from the pixel selection circuit 7.
- Tl and T2 are alternately turned on and off, the sensor signals ⁇ V0 of the respective elements Dl1 to D116 are output in time series.
- Reading of the sensor signal Vo of each pixel in such an image sensor is executed under the control of an ECU (not shown).
- FIG. 9 shows a configuration example when a shift register is used for the screen selection circuit 2.
- each of the register outputs DS1 to DS16 .
- the analog switches SV1 to SW16 are turned on only while each ⁇ is selected. Then it can be turned on.
- Reference numeral 10 denotes a configuration example in the case where a decoder circuit is used for the 'Yu' selection circuit 2.
- each pixel is output by four bits A0 to A3, each of the decoder outputs 1 to DS1 corresponding to human power, as shown in FIG.
- the analog switches SW1 to SW16 are turned on sequentially only during the power cycle.
- Can be A similar decoder circuit is used for the pixel selection circuit 7 as well.
- FIG. 11 is a time chart of signals of each section showing another example of the operation state of the image sensor having the configuration of FIG.
- each analog switch SW1 to SW1 is maintained by maintaining the pixel selection signal (DS1 to DS16) by the pixel selection circuit 2 for a time corresponding to selecting two pixels for one block. 6 is turned on during that time. That is, in this case, the ON period of each of the analog switches SW1 to SW16 is twice as long as that in the case of the control of FIG. This means that the time required for the sensor signal read out from each pixel to stabilize is twice as long, and if the stability time is the same, the Yansa signal of each captured image is read out compared to the control in Fig. 8. Scanning time can be doubled.
- FIG. 12 shows a decoder circuit used in the pixel selection circuit 2 in this case.
- US1 and DS2, DS2 and DS3, ' ⁇ ', DS15 and DS16 can be sequentially selected by the 4-bit signal input of A0 to A3. it can.
- FIG. 13 shows another embodiment of the image sensor according to the present invention.
- one block is composed of four pixels, the pixel row for one line is equally divided into one, and the output signal line of the sensor signal of the first pixel in each block is shared.
- a signal line a having a common output line for the sensor signal of the second pixel, a signal line c having a common output line for the third pixel sensor ⁇ , and a signal line c having a common output line for the sensor signal of the second pixel.
- the signal line d which shares the output line of the sensor ⁇ of the fourth pixel, is drawn out.
- each of the signal lines a to d transmits a signal for sequentially selecting sensor signals B 1, B 2, B 3, and B 4 of each pixel for one pro and a request.
- the analog switches T 1, T 2, T 3, and T 4 are sequentially turned on in accordance with the selection circuit 7 ′ and the selection output thereof, and the sensor signals “ ⁇ 1, ⁇ 2, ⁇ 3, ⁇ Switch circuit that outputs 4 8 ' And a bias circuit 9 'for defining a pixel sensor signal read from each block as a voltage value by a reference resistor R to which a bias voltage Vcc is applied.
- FIG. 14 is a time chart of each signal showing an example of an operation state of the image sensor having the configuration of FIG.
- the pixel sequence composed of D11 to D116 is selected by the pixel sequence selection signal ⁇ LS1, and the analog switches SW1 to SW16 are sequentially turned on according to the pixel selection signals DS1 to DS16. ..
- the sensor signal B1 of the first pixel (D11, D15, D19, D113) in each block is read out to the signal line a, and the second signal in each block is read out.
- the sensor signal B2 of the pixel (D12, D16, D11, D11) is read out to the signal line b ..
- the third pixel (D13, D13) in each block 17, D 11 1, D 11 5) The sensor signal B 3 is read out to the signal line c, and the fourth pixel (D 14, D 18, D 1 12, The sensor signal B 4 of D 1 16) is read out to the signal line d. And .. After the sensor signals '1 1 to B4 respectively read out to the signal lines a to (!)
- the bias circuit 9' By the bias circuit 9' are converted into the voltage signals, the selection signals from the Accordingly, the analog switches T1 to T4 are sequentially turned on and off, so that the sensor signals Vo of the pixels Dl1 to D116 are output in time series.
- the analog selection switches SW 1 to SW 16 are maintained by maintaining the pixel selection signals (DS 1 to DS 16) by the pixel selection circuit 2 for a time equivalent to selecting four pixels for one block. Is turned on during this time. That is, in this case, the ON period of each of the analog switches SW1 to SW16 is four times as long as that in the case of the control of the 81st]. This means that the time required for the sensor signal read out from each pixel to stabilize can be increased by a factor of .4. If the stabilization time is the same, the sensor signal of each pixel can be compared to the control in Fig. 8. The scanning time for reading out data can be quadrupled.
- FIG. 16 shows still another embodiment of the image sensor according to the present invention.
- a buffer circuit 10 in which a buzzy amplifier BF is connected to each of the signal lines a and b on the output side of the bias circuit 9 is provided, and the voltage signal Vo of each pixel is intensively concentrated.
- the stored voltage signals Vo of the respective pixels are sequentially output to the outside by switching the analog switches T 1 and T 2 by the pixel selection circuit 7.
- the bias circuit 9 and the buffer circuit 10 are provided only on the two signal lines a and b that are drawn by dividing the pixel column for one line into blocks, so that the power consumption is minimized. Can be suppressed to a minimum.
- the basic operation state of the image sensor having the configuration shown in FIG. 16 is the same as that described above, as shown in the time chart of each signal shown in FIG. 8 or FIG. .
- FIG. 17 shows still another embodiment of the image sensor according to the present invention.
- a pixel selection circuit 7 ′ that transmits a signal for sequentially selecting the sensor signals 3 ⁇ 4 B 1, ⁇ 2, ⁇ 3, ⁇ of each pixel for one block to the system of each signal line a to d.
- the analog switches ⁇ 1, ⁇ 2, ⁇ 3, ⁇ ⁇ 4 are sequentially turned on in accordance with the selected output, and the switches for outputting the sensor signals ⁇ 1, 2, 3, ⁇ 4 of each pixel are output.
- the bias circuit 9 ' which defines the sensor signal of the pixel read from each block as a voltage value by the reference resistor R to which the bias voltage Vcc is applied, and the bias circuit 9'
- a buffer circuit 10 ' is provided for temporarily storing the voltage of each pixel.
- the basic operation state of the image sensor having the configuration shown in FIG. 17 is the same as that described above, as shown in the time chart of each signal in FIG.
- the pixels used in the image sensor of the present invention are not limited to the optical sensor circuit shown in FIG. 1 and other solid-state image sensors such as CCDs and MOS image sensors are widely used. Applied.
- the solid-state imaging devices in pixel units are arranged in a matrix, the pixel rows for one line are sequentially selected, and the pixels in the sequentially selected pixel rows are sequentially selected.
- a pixel row for one line is equally divided into a plurality of parts by a project having a predetermined number of pixel configurations, and the first divided part
- a first scanning means for sequentially reading out the sensor signal of each pixel in order from the block and a second scanning means for sequentially reading out the sensor signal of each pixel in the read-out block are provided. Therefore, it is possible to perform high-speed read scanning of each pixel while effectively suppressing power consumption.
- the solid-state imaging devices in pixel units are arranged in a matrix, and the pixel columns for each one line are sequentially selected, and each pixel in the sequentially selected pixel columns is sequentially selected.
- the sensor signal of each pixel is read out in chronological order, and a pixel row for one line is equally divided into a plurality of blocks by a block having a predetermined number of pixel configurations, and the divided First scanning means for sequentially reading the sensor signal of each pixel in order from the first buzzer's jig, buffer means for accumulating the sensor signal of each pixel in the read block in one block, and temporary storage thereof
- a second scanning means for sequentially reading out the sensor signals of the respective pixels.
- the reading operation of each pixel is performed at high speed while effectively suppressing power consumption. This makes it possible to 's.
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Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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JP2003504666A JP3924754B2 (ja) | 2001-06-06 | 2002-04-08 | イメージセンサ |
US10/729,577 US7414652B2 (en) | 2001-06-06 | 2003-12-03 | Image sensor and method |
Applications Claiming Priority (4)
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JP2001-209985 | 2001-06-06 | ||
JP2001209985 | 2001-06-06 | ||
JP2001-209983 | 2001-06-06 | ||
JP2001209983 | 2001-06-06 |
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US10/729,577 Continuation US7414652B2 (en) | 2001-06-06 | 2003-12-03 | Image sensor and method |
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PCT/JP2002/003481 WO2002102061A1 (fr) | 2001-06-06 | 2002-04-08 | Detecteur d'images |
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US (1) | US7414652B2 (ja) |
JP (1) | JP3924754B2 (ja) |
TW (1) | TW571584B (ja) |
WO (1) | WO2002102061A1 (ja) |
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JP4254388B2 (ja) * | 2003-06-11 | 2009-04-15 | 本田技研工業株式会社 | イメージセンサの走査回路 |
JP2007228019A (ja) * | 2006-02-21 | 2007-09-06 | Olympus Corp | 撮像装置 |
JP4893042B2 (ja) * | 2006-03-20 | 2012-03-07 | コニカミノルタホールディングス株式会社 | 撮像装置 |
JP5101972B2 (ja) * | 2007-10-02 | 2012-12-19 | オリンパス株式会社 | 固体撮像装置 |
JP5935274B2 (ja) | 2011-09-22 | 2016-06-15 | ソニー株式会社 | 固体撮像装置、固体撮像装置の制御方法および固体撮像装置の制御プログラム |
US9880688B2 (en) * | 2015-08-05 | 2018-01-30 | Synaptics Incorporated | Active matrix capacitive sensor for common-mode cancellation |
US10430633B2 (en) | 2017-01-13 | 2019-10-01 | Synaptics Incorporated | Pixel architecture and driving scheme for biometric sensing |
US10216972B2 (en) | 2017-01-13 | 2019-02-26 | Synaptics Incorporated | Pixel architecture and driving scheme for biometric sensing |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0993492A (ja) * | 1995-09-27 | 1997-04-04 | Nippon Hoso Kyokai <Nhk> | 固体撮像装置 |
JP2000115642A (ja) * | 1998-10-09 | 2000-04-21 | Honda Motor Co Ltd | イメージセンサ |
JP2000329616A (ja) * | 1999-05-18 | 2000-11-30 | Honda Motor Co Ltd | 光センサ回路 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4899220A (en) * | 1987-06-02 | 1990-02-06 | North American Philips Corporation | Method and apparatus for recombining a main panel component with a augmentation panel component to create a wide aspect ratio televison display |
US5933189A (en) * | 1995-03-09 | 1999-08-03 | Nikon Corporation | Solid state image pickup apparatus |
US5604534A (en) * | 1995-05-24 | 1997-02-18 | Omni Solutions International, Ltd. | Direct digital airborne panoramic camera system and method |
KR100263500B1 (ko) * | 1996-12-24 | 2000-08-01 | 다니구찌 이찌로오 | 고체 촬상 소자 및 그 구동 방법 |
US6665010B1 (en) * | 1998-07-21 | 2003-12-16 | Intel Corporation | Controlling integration times of pixel sensors |
TW530287B (en) * | 1998-09-03 | 2003-05-01 | Samsung Electronics Co Ltd | Display device, and apparatus and method for driving display device |
DE60030828T2 (de) * | 1999-07-09 | 2007-02-08 | Bts Holding International Bv | Optische abtastvorrichtung mit umschaltbarer auflösung |
US6975355B1 (en) * | 2000-02-22 | 2005-12-13 | Pixim, Inc. | Multiple sampling via a time-indexed method to achieve wide dynamic ranges |
JP4179719B2 (ja) * | 1999-10-07 | 2008-11-12 | 株式会社東芝 | 固体撮像装置 |
WO2001063910A1 (en) * | 2000-02-22 | 2001-08-30 | Photobit Corporation | Frame shuttering scheme for increased frame rate |
JP2002204398A (ja) * | 2000-10-05 | 2002-07-19 | Honda Motor Co Ltd | イメージセンサ |
US6531266B1 (en) * | 2001-03-16 | 2003-03-11 | Taiwan Semiconductor Manufacturing Company | Rework procedure for the microlens element of a CMOS image sensor |
JP4550350B2 (ja) * | 2002-02-01 | 2010-09-22 | 株式会社ニコン | 電子カメラ |
US6868231B2 (en) * | 2002-06-12 | 2005-03-15 | Eastman Kodak Company | Imaging using silver halide films with micro-lens capture and optical reconstruction |
US7808063B2 (en) * | 2005-05-26 | 2010-10-05 | Micron Technology, Inc. | Structure and method for FPN reduction in imaging devices |
-
2002
- 2002-04-08 WO PCT/JP2002/003481 patent/WO2002102061A1/ja active Application Filing
- 2002-04-08 JP JP2003504666A patent/JP3924754B2/ja not_active Expired - Fee Related
- 2002-04-10 TW TW091107159A patent/TW571584B/zh not_active IP Right Cessation
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2003
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Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0993492A (ja) * | 1995-09-27 | 1997-04-04 | Nippon Hoso Kyokai <Nhk> | 固体撮像装置 |
JP2000115642A (ja) * | 1998-10-09 | 2000-04-21 | Honda Motor Co Ltd | イメージセンサ |
JP2000329616A (ja) * | 1999-05-18 | 2000-11-30 | Honda Motor Co Ltd | 光センサ回路 |
Also Published As
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US20070273780A9 (en) | 2007-11-29 |
US20040169755A1 (en) | 2004-09-02 |
TW571584B (en) | 2004-01-11 |
JP3924754B2 (ja) | 2007-06-06 |
US7414652B2 (en) | 2008-08-19 |
JPWO2002102061A1 (ja) | 2004-09-30 |
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